1 /* SPDX-License-Identifier: GPL-2.0-or-later 2 * Aquantia Corp. Aquantia AQtion USB to 5GbE Controller 3 * Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com> 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 5 * Copyright (C) 2002-2003 TiVo Inc. 6 * Copyright (C) 2017-2018 ASIX 7 * Copyright (C) 2018 Aquantia Corp. 8 */ 9 10 #ifndef __LINUX_USBNET_AQC111_H 11 #define __LINUX_USBNET_AQC111_H 12 13 #define URB_SIZE (1024 * 62) 14 15 #define AQ_ACCESS_MAC 0x01 16 #define AQ_FLASH_PARAMETERS 0x20 17 #define AQ_PHY_POWER 0x31 18 #define AQ_PHY_OPS 0x61 19 20 #define AQ_USB_PHY_SET_TIMEOUT 10000 21 #define AQ_USB_SET_TIMEOUT 4000 22 23 /* Feature. ********************************************/ 24 #define AQ_SUPPORT_FEATURE (NETIF_F_SG) 25 #define AQ_SUPPORT_HW_FEATURE (NETIF_F_SG) 26 27 /* SFR Reg. ********************************************/ 28 29 #define SFR_GENERAL_STATUS 0x03 30 #define SFR_CHIP_STATUS 0x05 31 #define SFR_RX_CTL 0x0B 32 #define SFR_RX_CTL_TXPADCRC 0x0400 33 #define SFR_RX_CTL_IPE 0x0200 34 #define SFR_RX_CTL_DROPCRCERR 0x0100 35 #define SFR_RX_CTL_START 0x0080 36 #define SFR_RX_CTL_RF_WAK 0x0040 37 #define SFR_RX_CTL_AP 0x0020 38 #define SFR_RX_CTL_AM 0x0010 39 #define SFR_RX_CTL_AB 0x0008 40 #define SFR_RX_CTL_AMALL 0x0002 41 #define SFR_RX_CTL_PRO 0x0001 42 #define SFR_RX_CTL_STOP 0x0000 43 #define SFR_INTER_PACKET_GAP_0 0x0D 44 #define SFR_NODE_ID 0x10 45 #define SFR_MULTI_FILTER_ARRY 0x16 46 #define SFR_MEDIUM_STATUS_MODE 0x22 47 #define SFR_MEDIUM_XGMIIMODE 0x0001 48 #define SFR_MEDIUM_FULL_DUPLEX 0x0002 49 #define SFR_MEDIUM_RXFLOW_CTRLEN 0x0010 50 #define SFR_MEDIUM_TXFLOW_CTRLEN 0x0020 51 #define SFR_MEDIUM_JUMBO_EN 0x0040 52 #define SFR_MEDIUM_RECEIVE_EN 0x0100 53 #define SFR_MONITOR_MODE 0x24 54 #define SFR_MONITOR_MODE_EPHYRW 0x01 55 #define SFR_MONITOR_MODE_RWLC 0x02 56 #define SFR_MONITOR_MODE_RWMP 0x04 57 #define SFR_MONITOR_MODE_RWWF 0x08 58 #define SFR_MONITOR_MODE_RW_FLAG 0x10 59 #define SFR_MONITOR_MODE_PMEPOL 0x20 60 #define SFR_MONITOR_MODE_PMETYPE 0x40 61 #define SFR_PHYPWR_RSTCTL 0x26 62 #define SFR_PHYPWR_RSTCTL_BZ 0x0010 63 #define SFR_PHYPWR_RSTCTL_IPRL 0x0020 64 #define SFR_VLAN_ID_ADDRESS 0x2A 65 #define SFR_VLAN_ID_CONTROL 0x2B 66 #define SFR_VLAN_CONTROL_WE 0x0001 67 #define SFR_VLAN_CONTROL_RD 0x0002 68 #define SFR_VLAN_CONTROL_VSO 0x0010 69 #define SFR_VLAN_CONTROL_VFE 0x0020 70 #define SFR_VLAN_ID_DATA0 0x2C 71 #define SFR_VLAN_ID_DATA1 0x2D 72 #define SFR_RX_BULKIN_QCTRL 0x2E 73 #define SFR_RX_BULKIN_QCTRL_TIME 0x01 74 #define SFR_RX_BULKIN_QCTRL_IFG 0x02 75 #define SFR_RX_BULKIN_QCTRL_SIZE 0x04 76 #define SFR_RX_BULKIN_QTIMR_LOW 0x2F 77 #define SFR_RX_BULKIN_QTIMR_HIGH 0x30 78 #define SFR_RX_BULKIN_QSIZE 0x31 79 #define SFR_RX_BULKIN_QIFG 0x32 80 #define SFR_RXCOE_CTL 0x34 81 #define SFR_RXCOE_IP 0x01 82 #define SFR_RXCOE_TCP 0x02 83 #define SFR_RXCOE_UDP 0x04 84 #define SFR_RXCOE_ICMP 0x08 85 #define SFR_RXCOE_IGMP 0x10 86 #define SFR_RXCOE_TCPV6 0x20 87 #define SFR_RXCOE_UDPV6 0x40 88 #define SFR_RXCOE_ICMV6 0x80 89 #define SFR_TXCOE_CTL 0x35 90 #define SFR_TXCOE_IP 0x01 91 #define SFR_TXCOE_TCP 0x02 92 #define SFR_TXCOE_UDP 0x04 93 #define SFR_TXCOE_ICMP 0x08 94 #define SFR_TXCOE_IGMP 0x10 95 #define SFR_TXCOE_TCPV6 0x20 96 #define SFR_TXCOE_UDPV6 0x40 97 #define SFR_TXCOE_ICMV6 0x80 98 #define SFR_BM_INT_MASK 0x41 99 #define SFR_BMRX_DMA_CONTROL 0x43 100 #define SFR_BMRX_DMA_EN 0x80 101 #define SFR_BMTX_DMA_CONTROL 0x46 102 #define SFR_PAUSE_WATERLVL_LOW 0x54 103 #define SFR_PAUSE_WATERLVL_HIGH 0x55 104 #define SFR_ARC_CTRL 0x9E 105 #define SFR_SWP_CTRL 0xB1 106 #define SFR_TX_PAUSE_RESEND_T 0xB2 107 #define SFR_ETH_MAC_PATH 0xB7 108 #define SFR_RX_PATH_READY 0x01 109 #define SFR_BULK_OUT_CTRL 0xB9 110 #define SFR_BULK_OUT_FLUSH_EN 0x01 111 #define SFR_BULK_OUT_EFF_EN 0x02 112 113 #define AQ_FW_VER_MAJOR 0xDA 114 #define AQ_FW_VER_MINOR 0xDB 115 #define AQ_FW_VER_REV 0xDC 116 117 /*PHY_OPS**********************************************************************/ 118 119 #define AQ_ADV_100M BIT(0) 120 #define AQ_ADV_1G BIT(1) 121 #define AQ_ADV_2G5 BIT(2) 122 #define AQ_ADV_5G BIT(3) 123 #define AQ_ADV_MASK 0x0F 124 125 #define AQ_PAUSE BIT(16) 126 #define AQ_ASYM_PAUSE BIT(17) 127 #define AQ_LOW_POWER BIT(18) 128 #define AQ_PHY_POWER_EN BIT(19) 129 #define AQ_WOL BIT(20) 130 #define AQ_DOWNSHIFT BIT(21) 131 132 #define AQ_DSH_RETRIES_SHIFT 0x18 133 #define AQ_DSH_RETRIES_MASK 0xF000000 134 135 /******************************************************************************/ 136 137 struct aqc111_data { 138 u8 link_speed; 139 u8 link; 140 u8 autoneg; 141 u32 advertised_speed; 142 struct { 143 u8 major; 144 u8 minor; 145 u8 rev; 146 } fw_ver; 147 u32 phy_cfg; 148 }; 149 150 #define AQ_LS_MASK 0x8000 151 #define AQ_SPEED_MASK 0x7F00 152 #define AQ_SPEED_SHIFT 0x0008 153 #define AQ_INT_SPEED_5G 0x000F 154 #define AQ_INT_SPEED_2_5G 0x0010 155 #define AQ_INT_SPEED_1G 0x0011 156 #define AQ_INT_SPEED_100M 0x0013 157 158 /* TX Descriptor */ 159 #define AQ_TX_DESC_LEN_MASK 0x1FFFFF 160 #define AQ_TX_DESC_DROP_PADD BIT(28) 161 162 #define AQ_RX_HW_PAD 0x02 163 164 /* RX Packet Descriptor */ 165 #define AQ_RX_PD_RX_OK BIT(11) 166 #define AQ_RX_PD_DROP BIT(31) 167 #define AQ_RX_PD_LEN_MASK 0x7FFF0000 168 #define AQ_RX_PD_LEN_SHIFT 0x10 169 170 /* RX Descriptor header */ 171 #define AQ_RX_DH_PKT_CNT_MASK 0x1FFF 172 #define AQ_RX_DH_DESC_OFFSET_MASK 0xFFFFE000 173 #define AQ_RX_DH_DESC_OFFSET_SHIFT 0x0D 174 175 static struct { 176 unsigned char ctrl; 177 unsigned char timer_l; 178 unsigned char timer_h; 179 unsigned char size; 180 unsigned char ifg; 181 } AQC111_BULKIN_SIZE[] = { 182 /* xHCI & EHCI & OHCI */ 183 {7, 0x00, 0x01, 0x1E, 0xFF},/* 10G, 5G, 2.5G, 1G */ 184 {7, 0xA0, 0x00, 0x14, 0x00},/* 100M */ 185 /* Jumbo packet */ 186 {7, 0x00, 0x01, 0x18, 0xFF}, 187 }; 188 189 #endif /* __LINUX_USBNET_AQC111_H */ 190