ocelot.c (5bc9d2e6e7d546548ae1a7cd3de37672db4075ce) ocelot.c (fa914e9c4d9485f06b3676791a74587d2642fca3)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/etherdevice.h>
8#include <linux/ethtool.h>

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2092 /* There is no device reconfiguration, PTP Rx stamping is always
2093 * enabled.
2094 */
2095 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2096
2097 return 0;
2098}
2099
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/etherdevice.h>
8#include <linux/ethtool.h>

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2092 /* There is no device reconfiguration, PTP Rx stamping is always
2093 * enabled.
2094 */
2095 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
2096
2097 return 0;
2098}
2099
2100static void ocelot_init_port(struct ocelot *ocelot, int port)
2100static void ocelot_port_set_mtu(struct ocelot *ocelot, int port, size_t mtu)
2101{
2102 struct ocelot_port *ocelot_port = ocelot->ports[port];
2103 int atop_wm;
2104
2101{
2102 struct ocelot_port *ocelot_port = ocelot->ports[port];
2103 int atop_wm;
2104
2105 ocelot_port_writel(ocelot_port, mtu, DEV_MAC_MAXLEN_CFG);
2106
2107 /* Set Pause WM hysteresis
2108 * 152 = 6 * mtu / OCELOT_BUFFER_CELL_SZ
2109 * 101 = 4 * mtu / OCELOT_BUFFER_CELL_SZ
2110 */
2111 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
2112 SYS_PAUSE_CFG_PAUSE_STOP(101) |
2113 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
2114
2115 /* Tail dropping watermark */
2116 atop_wm = (ocelot->shared_queue_sz - 9 * mtu) / OCELOT_BUFFER_CELL_SZ;
2117 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * mtu),
2118 SYS_ATOP, port);
2119 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
2120}
2121
2122static void ocelot_init_port(struct ocelot *ocelot, int port)
2123{
2124 struct ocelot_port *ocelot_port = ocelot->ports[port];
2125
2105 INIT_LIST_HEAD(&ocelot_port->skbs);
2106
2107 /* Basic L2 initialization */
2108
2109 /* Set MAC IFG Gaps
2110 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
2111 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
2112 */

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2117 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
2118 DEV_MAC_HDX_CFG_SEED_LOAD,
2119 DEV_MAC_HDX_CFG);
2120 mdelay(1);
2121 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
2122 DEV_MAC_HDX_CFG);
2123
2124 /* Set Max Length and maximum tags allowed */
2126 INIT_LIST_HEAD(&ocelot_port->skbs);
2127
2128 /* Basic L2 initialization */
2129
2130 /* Set MAC IFG Gaps
2131 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
2132 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
2133 */

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2138 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
2139 DEV_MAC_HDX_CFG_SEED_LOAD,
2140 DEV_MAC_HDX_CFG);
2141 mdelay(1);
2142 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
2143 DEV_MAC_HDX_CFG);
2144
2145 /* Set Max Length and maximum tags allowed */
2125 ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN,
2126 DEV_MAC_MAXLEN_CFG);
2146 ocelot_port_set_mtu(ocelot, port, VLAN_ETH_FRAME_LEN);
2127 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
2128 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
2129 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
2130 DEV_MAC_TAGS_CFG);
2131
2132 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
2133 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
2134 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
2135
2147 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
2148 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
2149 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
2150 DEV_MAC_TAGS_CFG);
2151
2152 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
2153 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
2154 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
2155
2136 /* Set Pause WM hysteresis
2137 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
2138 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ
2139 */
2140 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA |
2141 SYS_PAUSE_CFG_PAUSE_STOP(101) |
2142 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port);
2143
2144 /* Tail dropping watermark */
2145 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ;
2146 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN),
2147 SYS_ATOP, port);
2148 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
2149
2150 /* Drop frames with multicast source address */
2151 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2152 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2153 ANA_PORT_DROP_CFG, port);
2154
2155 /* Set default VLAN and tag type to 8021Q. */
2156 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2157 REW_PORT_VLAN_CFG_PORT_TPID_M,

--- 254 unchanged lines hidden --- 		2156 /* Drop frames with multicast source address */
2157 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2158 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2159 ANA_PORT_DROP_CFG, port);
2160
2161 /* Set default VLAN and tag type to 8021Q. */
2162 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2163 REW_PORT_VLAN_CFG_PORT_TPID_M,

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