1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/skbuff.h> 19 #include <linux/iopoll.h> 20 #include <net/arp.h> 21 #include <net/netevent.h> 22 #include <net/rtnetlink.h> 23 #include <net/switchdev.h> 24 #include <net/dsa.h> 25 26 #include "ocelot.h" 27 #include "ocelot_ace.h" 28 29 #define TABLE_UPDATE_SLEEP_US 10 30 #define TABLE_UPDATE_TIMEOUT_US 100000 31 32 /* MAC table entry types. 33 * ENTRYTYPE_NORMAL is subject to aging. 34 * ENTRYTYPE_LOCKED is not subject to aging. 35 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 36 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 37 */ 38 enum macaccess_entry_type { 39 ENTRYTYPE_NORMAL = 0, 40 ENTRYTYPE_LOCKED, 41 ENTRYTYPE_MACv4, 42 ENTRYTYPE_MACv6, 43 }; 44 45 struct ocelot_mact_entry { 46 u8 mac[ETH_ALEN]; 47 u16 vid; 48 enum macaccess_entry_type type; 49 }; 50 51 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 52 { 53 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 54 } 55 56 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 57 { 58 u32 val; 59 60 return readx_poll_timeout(ocelot_mact_read_macaccess, 61 ocelot, val, 62 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 63 MACACCESS_CMD_IDLE, 64 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 65 } 66 67 static void ocelot_mact_select(struct ocelot *ocelot, 68 const unsigned char mac[ETH_ALEN], 69 unsigned int vid) 70 { 71 u32 macl = 0, mach = 0; 72 73 /* Set the MAC address to handle and the vlan associated in a format 74 * understood by the hardware. 75 */ 76 mach |= vid << 16; 77 mach |= mac[0] << 8; 78 mach |= mac[1] << 0; 79 macl |= mac[2] << 24; 80 macl |= mac[3] << 16; 81 macl |= mac[4] << 8; 82 macl |= mac[5] << 0; 83 84 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 85 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 86 87 } 88 89 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 90 const unsigned char mac[ETH_ALEN], 91 unsigned int vid, 92 enum macaccess_entry_type type) 93 { 94 ocelot_mact_select(ocelot, mac, vid); 95 96 /* Issue a write command */ 97 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 98 ANA_TABLES_MACACCESS_DEST_IDX(port) | 99 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 100 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 101 ANA_TABLES_MACACCESS); 102 103 return ocelot_mact_wait_for_completion(ocelot); 104 } 105 106 static int ocelot_mact_forget(struct ocelot *ocelot, 107 const unsigned char mac[ETH_ALEN], 108 unsigned int vid) 109 { 110 ocelot_mact_select(ocelot, mac, vid); 111 112 /* Issue a forget command */ 113 ocelot_write(ocelot, 114 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 115 ANA_TABLES_MACACCESS); 116 117 return ocelot_mact_wait_for_completion(ocelot); 118 } 119 120 static void ocelot_mact_init(struct ocelot *ocelot) 121 { 122 /* Configure the learning mode entries attributes: 123 * - Do not copy the frame to the CPU extraction queues. 124 * - Use the vlan and mac_cpoy for dmac lookup. 125 */ 126 ocelot_rmw(ocelot, 0, 127 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 128 | ANA_AGENCTRL_LEARN_FWD_KILL 129 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 130 ANA_AGENCTRL); 131 132 /* Clear the MAC table */ 133 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 134 } 135 136 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 137 { 138 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 139 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 140 ANA_PORT_VCAP_S2_CFG, port); 141 } 142 143 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 144 { 145 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 146 } 147 148 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 149 { 150 u32 val; 151 152 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 153 ocelot, 154 val, 155 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 156 ANA_TABLES_VLANACCESS_CMD_IDLE, 157 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 158 } 159 160 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 161 { 162 /* Select the VID to configure */ 163 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 164 ANA_TABLES_VLANTIDX); 165 /* Set the vlan port members mask and issue a write command */ 166 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 167 ANA_TABLES_VLANACCESS_CMD_WRITE, 168 ANA_TABLES_VLANACCESS); 169 170 return ocelot_vlant_wait_for_completion(ocelot); 171 } 172 173 static void ocelot_vlan_mode(struct ocelot *ocelot, int port, 174 netdev_features_t features) 175 { 176 u32 val; 177 178 /* Filtering */ 179 val = ocelot_read(ocelot, ANA_VLANMASK); 180 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 181 val |= BIT(port); 182 else 183 val &= ~BIT(port); 184 ocelot_write(ocelot, val, ANA_VLANMASK); 185 } 186 187 static void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 188 bool vlan_aware) 189 { 190 struct ocelot_port *ocelot_port = ocelot->ports[port]; 191 u32 val; 192 193 if (vlan_aware) 194 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 195 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 196 else 197 val = 0; 198 ocelot_rmw_gix(ocelot, val, 199 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 200 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 201 ANA_PORT_VLAN_CFG, port); 202 203 if (vlan_aware && !ocelot_port->vid) 204 /* If port is vlan-aware and tagged, drop untagged and priority 205 * tagged frames. 206 */ 207 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 208 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 209 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 210 else 211 val = 0; 212 ocelot_rmw_gix(ocelot, val, 213 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 214 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 215 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 216 ANA_PORT_DROP_CFG, port); 217 218 if (vlan_aware) { 219 if (ocelot_port->vid) 220 /* Tag all frames except when VID == DEFAULT_VLAN */ 221 val |= REW_TAG_CFG_TAG_CFG(1); 222 else 223 /* Tag all frames */ 224 val |= REW_TAG_CFG_TAG_CFG(3); 225 } else { 226 /* Port tagging disabled. */ 227 val = REW_TAG_CFG_TAG_CFG(0); 228 } 229 ocelot_rmw_gix(ocelot, val, 230 REW_TAG_CFG_TAG_CFG_M, 231 REW_TAG_CFG, port); 232 } 233 234 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 235 u16 vid) 236 { 237 struct ocelot_port *ocelot_port = ocelot->ports[port]; 238 239 if (ocelot_port->vid != vid) { 240 /* Always permit deleting the native VLAN (vid = 0) */ 241 if (ocelot_port->vid && vid) { 242 dev_err(ocelot->dev, 243 "Port already has a native VLAN: %d\n", 244 ocelot_port->vid); 245 return -EBUSY; 246 } 247 ocelot_port->vid = vid; 248 } 249 250 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 251 REW_PORT_VLAN_CFG_PORT_VID_M, 252 REW_PORT_VLAN_CFG, port); 253 254 return 0; 255 } 256 257 /* Default vlan to clasify for untagged frames (may be zero) */ 258 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 259 { 260 struct ocelot_port *ocelot_port = ocelot->ports[port]; 261 262 ocelot_rmw_gix(ocelot, 263 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 264 ANA_PORT_VLAN_CFG_VLAN_VID_M, 265 ANA_PORT_VLAN_CFG, port); 266 267 ocelot_port->pvid = pvid; 268 } 269 270 static int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 271 bool untagged) 272 { 273 int ret; 274 275 /* Make the port a member of the VLAN */ 276 ocelot->vlan_mask[vid] |= BIT(port); 277 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 278 if (ret) 279 return ret; 280 281 /* Default ingress vlan classification */ 282 if (pvid) 283 ocelot_port_set_pvid(ocelot, port, vid); 284 285 /* Untagged egress vlan clasification */ 286 if (untagged) { 287 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 288 if (ret) 289 return ret; 290 } 291 292 return 0; 293 } 294 295 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 296 bool untagged) 297 { 298 struct ocelot_port_private *priv = netdev_priv(dev); 299 struct ocelot_port *ocelot_port = &priv->port; 300 struct ocelot *ocelot = ocelot_port->ocelot; 301 int port = priv->chip_port; 302 int ret; 303 304 ret = ocelot_vlan_add(ocelot, port, vid, pvid, untagged); 305 if (ret) 306 return ret; 307 308 /* Add the port MAC address to with the right VLAN information */ 309 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 310 ENTRYTYPE_LOCKED); 311 312 return 0; 313 } 314 315 static int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 316 { 317 struct ocelot_port *ocelot_port = ocelot->ports[port]; 318 int ret; 319 320 /* Stop the port from being a member of the vlan */ 321 ocelot->vlan_mask[vid] &= ~BIT(port); 322 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 323 if (ret) 324 return ret; 325 326 /* Ingress */ 327 if (ocelot_port->pvid == vid) 328 ocelot_port_set_pvid(ocelot, port, 0); 329 330 /* Egress */ 331 if (ocelot_port->vid == vid) 332 ocelot_port_set_native_vlan(ocelot, port, 0); 333 334 return 0; 335 } 336 337 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 338 { 339 struct ocelot_port_private *priv = netdev_priv(dev); 340 struct ocelot *ocelot = priv->port.ocelot; 341 int port = priv->chip_port; 342 int ret; 343 344 /* 8021q removes VID 0 on module unload for all interfaces 345 * with VLAN filtering feature. We need to keep it to receive 346 * untagged traffic. 347 */ 348 if (vid == 0) 349 return 0; 350 351 ret = ocelot_vlan_del(ocelot, port, vid); 352 if (ret) 353 return ret; 354 355 /* Del the port MAC address to with the right VLAN information */ 356 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 357 358 return 0; 359 } 360 361 static void ocelot_vlan_init(struct ocelot *ocelot) 362 { 363 u16 port, vid; 364 365 /* Clear VLAN table, by default all ports are members of all VLANs */ 366 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 367 ANA_TABLES_VLANACCESS); 368 ocelot_vlant_wait_for_completion(ocelot); 369 370 /* Configure the port VLAN memberships */ 371 for (vid = 1; vid < VLAN_N_VID; vid++) { 372 ocelot->vlan_mask[vid] = 0; 373 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 374 } 375 376 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 377 * traffic. It is added automatically if 8021q module is loaded, but 378 * we can't rely on it since module may be not loaded. 379 */ 380 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 381 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 382 383 /* Set vlan ingress filter mask to all ports but the CPU port by 384 * default. 385 */ 386 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 387 ANA_VLANMASK); 388 389 for (port = 0; port < ocelot->num_phys_ports; port++) { 390 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 391 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 392 } 393 } 394 395 /* Watermark encode 396 * Bit 8: Unit; 0:1, 1:16 397 * Bit 7-0: Value to be multiplied with unit 398 */ 399 static u16 ocelot_wm_enc(u16 value) 400 { 401 if (value >= BIT(8)) 402 return BIT(8) | (value / 16); 403 404 return value; 405 } 406 407 static void ocelot_adjust_link(struct ocelot *ocelot, int port, 408 struct phy_device *phydev) 409 { 410 struct ocelot_port *ocelot_port = ocelot->ports[port]; 411 int speed, mode = 0; 412 413 switch (phydev->speed) { 414 case SPEED_10: 415 speed = OCELOT_SPEED_10; 416 break; 417 case SPEED_100: 418 speed = OCELOT_SPEED_100; 419 break; 420 case SPEED_1000: 421 speed = OCELOT_SPEED_1000; 422 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 423 break; 424 case SPEED_2500: 425 speed = OCELOT_SPEED_2500; 426 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 427 break; 428 default: 429 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 430 port, phydev->speed); 431 return; 432 } 433 434 phy_print_status(phydev); 435 436 if (!phydev->link) 437 return; 438 439 /* Only full duplex supported for now */ 440 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 441 mode, DEV_MAC_MODE_CFG); 442 443 if (ocelot->ops->pcs_init) 444 ocelot->ops->pcs_init(ocelot, port); 445 446 /* Enable MAC module */ 447 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 448 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 449 450 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 451 * reset */ 452 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 453 DEV_CLOCK_CFG); 454 455 /* No PFC */ 456 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 457 ANA_PFC_PFC_CFG, port); 458 459 /* Core: Enable port for frame transfer */ 460 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 461 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 462 QSYS_SWITCH_PORT_MODE_PORT_ENA, 463 QSYS_SWITCH_PORT_MODE, port); 464 465 /* Flow control */ 466 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 467 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 468 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 469 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 470 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 471 SYS_MAC_FC_CFG, port); 472 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 473 } 474 475 static void ocelot_port_adjust_link(struct net_device *dev) 476 { 477 struct ocelot_port_private *priv = netdev_priv(dev); 478 struct ocelot *ocelot = priv->port.ocelot; 479 int port = priv->chip_port; 480 481 ocelot_adjust_link(ocelot, port, dev->phydev); 482 } 483 484 static void ocelot_port_enable(struct ocelot *ocelot, int port, 485 struct phy_device *phy) 486 { 487 /* Enable receiving frames on the port, and activate auto-learning of 488 * MAC addresses. 489 */ 490 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 491 ANA_PORT_PORT_CFG_RECV_ENA | 492 ANA_PORT_PORT_CFG_PORTID_VAL(port), 493 ANA_PORT_PORT_CFG, port); 494 } 495 496 static int ocelot_port_open(struct net_device *dev) 497 { 498 struct ocelot_port_private *priv = netdev_priv(dev); 499 struct ocelot *ocelot = priv->port.ocelot; 500 int port = priv->chip_port; 501 int err; 502 503 if (priv->serdes) { 504 err = phy_set_mode_ext(priv->serdes, PHY_MODE_ETHERNET, 505 priv->phy_mode); 506 if (err) { 507 netdev_err(dev, "Could not set mode of SerDes\n"); 508 return err; 509 } 510 } 511 512 err = phy_connect_direct(dev, priv->phy, &ocelot_port_adjust_link, 513 priv->phy_mode); 514 if (err) { 515 netdev_err(dev, "Could not attach to PHY\n"); 516 return err; 517 } 518 519 dev->phydev = priv->phy; 520 521 phy_attached_info(priv->phy); 522 phy_start(priv->phy); 523 524 ocelot_port_enable(ocelot, port, priv->phy); 525 526 return 0; 527 } 528 529 static void ocelot_port_disable(struct ocelot *ocelot, int port) 530 { 531 struct ocelot_port *ocelot_port = ocelot->ports[port]; 532 533 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 534 ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 535 QSYS_SWITCH_PORT_MODE, port); 536 } 537 538 static int ocelot_port_stop(struct net_device *dev) 539 { 540 struct ocelot_port_private *priv = netdev_priv(dev); 541 struct ocelot *ocelot = priv->port.ocelot; 542 int port = priv->chip_port; 543 544 phy_disconnect(priv->phy); 545 546 dev->phydev = NULL; 547 548 ocelot_port_disable(ocelot, port); 549 550 return 0; 551 } 552 553 /* Generate the IFH for frame injection 554 * 555 * The IFH is a 128bit-value 556 * bit 127: bypass the analyzer processing 557 * bit 56-67: destination mask 558 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 559 * bit 20-27: cpu extraction queue mask 560 * bit 16: tag type 0: C-tag, 1: S-tag 561 * bit 0-11: VID 562 */ 563 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 564 { 565 ifh[0] = IFH_INJ_BYPASS | ((0x1ff & info->rew_op) << 21); 566 ifh[1] = (0xf00 & info->port) >> 8; 567 ifh[2] = (0xff & info->port) << 24; 568 ifh[3] = (info->tag_type << 16) | info->vid; 569 570 return 0; 571 } 572 573 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 574 { 575 struct ocelot_port_private *priv = netdev_priv(dev); 576 struct skb_shared_info *shinfo = skb_shinfo(skb); 577 struct ocelot_port *ocelot_port = &priv->port; 578 struct ocelot *ocelot = ocelot_port->ocelot; 579 struct frame_info info = {}; 580 u8 grp = 0; /* Send everything on CPU group 0 */ 581 unsigned int i, count, last; 582 int port = priv->chip_port; 583 u32 val, ifh[IFH_LEN]; 584 585 val = ocelot_read(ocelot, QS_INJ_STATUS); 586 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 587 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 588 return NETDEV_TX_BUSY; 589 590 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 591 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 592 593 info.port = BIT(port); 594 info.tag_type = IFH_TAG_TYPE_C; 595 info.vid = skb_vlan_tag_get(skb); 596 597 /* Check if timestamping is needed */ 598 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) { 599 info.rew_op = ocelot_port->ptp_cmd; 600 if (ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) 601 info.rew_op |= (ocelot_port->ts_id % 4) << 3; 602 } 603 604 ocelot_gen_ifh(ifh, &info); 605 606 for (i = 0; i < IFH_LEN; i++) 607 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 608 QS_INJ_WR, grp); 609 610 count = (skb->len + 3) / 4; 611 last = skb->len % 4; 612 for (i = 0; i < count; i++) { 613 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 614 } 615 616 /* Add padding */ 617 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 618 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 619 i++; 620 } 621 622 /* Indicate EOF and valid bytes in last word */ 623 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 624 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 625 QS_INJ_CTRL_EOF, 626 QS_INJ_CTRL, grp); 627 628 /* Add dummy CRC */ 629 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 630 skb_tx_timestamp(skb); 631 632 dev->stats.tx_packets++; 633 dev->stats.tx_bytes += skb->len; 634 635 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP && 636 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 637 struct ocelot_skb *oskb = 638 kzalloc(sizeof(struct ocelot_skb), GFP_ATOMIC); 639 640 if (unlikely(!oskb)) 641 goto out; 642 643 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 644 645 oskb->skb = skb; 646 oskb->id = ocelot_port->ts_id % 4; 647 ocelot_port->ts_id++; 648 649 list_add_tail(&oskb->head, &ocelot_port->skbs); 650 651 return NETDEV_TX_OK; 652 } 653 654 out: 655 dev_kfree_skb_any(skb); 656 return NETDEV_TX_OK; 657 } 658 659 void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts) 660 { 661 unsigned long flags; 662 u32 val; 663 664 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 665 666 /* Read current PTP time to get seconds */ 667 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 668 669 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 670 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 671 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 672 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 673 674 /* Read packet HW timestamp from FIFO */ 675 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 676 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 677 678 /* Sec has incremented since the ts was registered */ 679 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 680 ts->tv_sec--; 681 682 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 683 } 684 EXPORT_SYMBOL(ocelot_get_hwtimestamp); 685 686 static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr) 687 { 688 struct ocelot_port_private *priv = netdev_priv(dev); 689 struct ocelot_port *ocelot_port = &priv->port; 690 struct ocelot *ocelot = ocelot_port->ocelot; 691 692 return ocelot_mact_forget(ocelot, addr, ocelot_port->pvid); 693 } 694 695 static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr) 696 { 697 struct ocelot_port_private *priv = netdev_priv(dev); 698 struct ocelot_port *ocelot_port = &priv->port; 699 struct ocelot *ocelot = ocelot_port->ocelot; 700 701 return ocelot_mact_learn(ocelot, PGID_CPU, addr, ocelot_port->pvid, 702 ENTRYTYPE_LOCKED); 703 } 704 705 static void ocelot_set_rx_mode(struct net_device *dev) 706 { 707 struct ocelot_port_private *priv = netdev_priv(dev); 708 struct ocelot *ocelot = priv->port.ocelot; 709 u32 val; 710 int i; 711 712 /* This doesn't handle promiscuous mode because the bridge core is 713 * setting IFF_PROMISC on all slave interfaces and all frames would be 714 * forwarded to the CPU port. 715 */ 716 val = GENMASK(ocelot->num_phys_ports - 1, 0); 717 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 718 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 719 720 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync); 721 } 722 723 static int ocelot_port_get_phys_port_name(struct net_device *dev, 724 char *buf, size_t len) 725 { 726 struct ocelot_port_private *priv = netdev_priv(dev); 727 int port = priv->chip_port; 728 int ret; 729 730 ret = snprintf(buf, len, "p%d", port); 731 if (ret >= len) 732 return -EINVAL; 733 734 return 0; 735 } 736 737 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 738 { 739 struct ocelot_port_private *priv = netdev_priv(dev); 740 struct ocelot_port *ocelot_port = &priv->port; 741 struct ocelot *ocelot = ocelot_port->ocelot; 742 const struct sockaddr *addr = p; 743 744 /* Learn the new net device MAC address in the mac table. */ 745 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, ocelot_port->pvid, 746 ENTRYTYPE_LOCKED); 747 /* Then forget the previous one. */ 748 ocelot_mact_forget(ocelot, dev->dev_addr, ocelot_port->pvid); 749 750 ether_addr_copy(dev->dev_addr, addr->sa_data); 751 return 0; 752 } 753 754 static void ocelot_get_stats64(struct net_device *dev, 755 struct rtnl_link_stats64 *stats) 756 { 757 struct ocelot_port_private *priv = netdev_priv(dev); 758 struct ocelot *ocelot = priv->port.ocelot; 759 int port = priv->chip_port; 760 761 /* Configure the port to read the stats from */ 762 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port), 763 SYS_STAT_CFG); 764 765 /* Get Rx stats */ 766 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 767 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 768 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 769 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 770 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 771 ocelot_read(ocelot, SYS_COUNT_RX_64) + 772 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 773 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 774 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 775 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 776 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 777 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 778 stats->rx_dropped = dev->stats.rx_dropped; 779 780 /* Get Tx stats */ 781 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 782 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 783 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 784 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 785 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 786 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 787 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 788 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 789 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 790 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 791 } 792 793 static int ocelot_fdb_add(struct ocelot *ocelot, int port, 794 const unsigned char *addr, u16 vid, 795 bool vlan_aware) 796 { 797 struct ocelot_port *ocelot_port = ocelot->ports[port]; 798 799 if (!vid) { 800 if (!vlan_aware) 801 /* If the bridge is not VLAN aware and no VID was 802 * provided, set it to pvid to ensure the MAC entry 803 * matches incoming untagged packets 804 */ 805 vid = ocelot_port->pvid; 806 else 807 /* If the bridge is VLAN aware a VID must be provided as 808 * otherwise the learnt entry wouldn't match any frame. 809 */ 810 return -EINVAL; 811 } 812 813 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED); 814 } 815 816 static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 817 struct net_device *dev, 818 const unsigned char *addr, 819 u16 vid, u16 flags, 820 struct netlink_ext_ack *extack) 821 { 822 struct ocelot_port_private *priv = netdev_priv(dev); 823 struct ocelot *ocelot = priv->port.ocelot; 824 int port = priv->chip_port; 825 826 return ocelot_fdb_add(ocelot, port, addr, vid, priv->vlan_aware); 827 } 828 829 static int ocelot_fdb_del(struct ocelot *ocelot, int port, 830 const unsigned char *addr, u16 vid) 831 { 832 return ocelot_mact_forget(ocelot, addr, vid); 833 } 834 835 static int ocelot_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 836 struct net_device *dev, 837 const unsigned char *addr, u16 vid) 838 { 839 struct ocelot_port_private *priv = netdev_priv(dev); 840 struct ocelot *ocelot = priv->port.ocelot; 841 int port = priv->chip_port; 842 843 return ocelot_fdb_del(ocelot, port, addr, vid); 844 } 845 846 struct ocelot_dump_ctx { 847 struct net_device *dev; 848 struct sk_buff *skb; 849 struct netlink_callback *cb; 850 int idx; 851 }; 852 853 static int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 854 bool is_static, void *data) 855 { 856 struct ocelot_dump_ctx *dump = data; 857 u32 portid = NETLINK_CB(dump->cb->skb).portid; 858 u32 seq = dump->cb->nlh->nlmsg_seq; 859 struct nlmsghdr *nlh; 860 struct ndmsg *ndm; 861 862 if (dump->idx < dump->cb->args[2]) 863 goto skip; 864 865 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 866 sizeof(*ndm), NLM_F_MULTI); 867 if (!nlh) 868 return -EMSGSIZE; 869 870 ndm = nlmsg_data(nlh); 871 ndm->ndm_family = AF_BRIDGE; 872 ndm->ndm_pad1 = 0; 873 ndm->ndm_pad2 = 0; 874 ndm->ndm_flags = NTF_SELF; 875 ndm->ndm_type = 0; 876 ndm->ndm_ifindex = dump->dev->ifindex; 877 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 878 879 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 880 goto nla_put_failure; 881 882 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 883 goto nla_put_failure; 884 885 nlmsg_end(dump->skb, nlh); 886 887 skip: 888 dump->idx++; 889 return 0; 890 891 nla_put_failure: 892 nlmsg_cancel(dump->skb, nlh); 893 return -EMSGSIZE; 894 } 895 896 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 897 struct ocelot_mact_entry *entry) 898 { 899 u32 val, dst, macl, mach; 900 char mac[ETH_ALEN]; 901 902 /* Set row and column to read from */ 903 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 904 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 905 906 /* Issue a read command */ 907 ocelot_write(ocelot, 908 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 909 ANA_TABLES_MACACCESS); 910 911 if (ocelot_mact_wait_for_completion(ocelot)) 912 return -ETIMEDOUT; 913 914 /* Read the entry flags */ 915 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 916 if (!(val & ANA_TABLES_MACACCESS_VALID)) 917 return -EINVAL; 918 919 /* If the entry read has another port configured as its destination, 920 * do not report it. 921 */ 922 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 923 if (dst != port) 924 return -EINVAL; 925 926 /* Get the entry's MAC address and VLAN id */ 927 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 928 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 929 930 mac[0] = (mach >> 8) & 0xff; 931 mac[1] = (mach >> 0) & 0xff; 932 mac[2] = (macl >> 24) & 0xff; 933 mac[3] = (macl >> 16) & 0xff; 934 mac[4] = (macl >> 8) & 0xff; 935 mac[5] = (macl >> 0) & 0xff; 936 937 entry->vid = (mach >> 16) & 0xfff; 938 ether_addr_copy(entry->mac, mac); 939 940 return 0; 941 } 942 943 static int ocelot_fdb_dump(struct ocelot *ocelot, int port, 944 dsa_fdb_dump_cb_t *cb, void *data) 945 { 946 int i, j; 947 948 /* Loop through all the mac tables entries. There are 1024 rows of 4 949 * entries. 950 */ 951 for (i = 0; i < 1024; i++) { 952 for (j = 0; j < 4; j++) { 953 struct ocelot_mact_entry entry; 954 bool is_static; 955 int ret; 956 957 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 958 /* If the entry is invalid (wrong port, invalid...), 959 * skip it. 960 */ 961 if (ret == -EINVAL) 962 continue; 963 else if (ret) 964 return ret; 965 966 is_static = (entry.type == ENTRYTYPE_LOCKED); 967 968 ret = cb(entry.mac, entry.vid, is_static, data); 969 if (ret) 970 return ret; 971 } 972 } 973 974 return 0; 975 } 976 977 static int ocelot_port_fdb_dump(struct sk_buff *skb, 978 struct netlink_callback *cb, 979 struct net_device *dev, 980 struct net_device *filter_dev, int *idx) 981 { 982 struct ocelot_port_private *priv = netdev_priv(dev); 983 struct ocelot *ocelot = priv->port.ocelot; 984 struct ocelot_dump_ctx dump = { 985 .dev = dev, 986 .skb = skb, 987 .cb = cb, 988 .idx = *idx, 989 }; 990 int port = priv->chip_port; 991 int ret; 992 993 ret = ocelot_fdb_dump(ocelot, port, ocelot_port_fdb_do_dump, &dump); 994 995 *idx = dump.idx; 996 997 return ret; 998 } 999 1000 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 1001 u16 vid) 1002 { 1003 return ocelot_vlan_vid_add(dev, vid, false, false); 1004 } 1005 1006 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 1007 u16 vid) 1008 { 1009 return ocelot_vlan_vid_del(dev, vid); 1010 } 1011 1012 static int ocelot_set_features(struct net_device *dev, 1013 netdev_features_t features) 1014 { 1015 netdev_features_t changed = dev->features ^ features; 1016 struct ocelot_port_private *priv = netdev_priv(dev); 1017 struct ocelot *ocelot = priv->port.ocelot; 1018 int port = priv->chip_port; 1019 1020 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 1021 priv->tc.offload_cnt) { 1022 netdev_err(dev, 1023 "Cannot disable HW TC offload while offloads active\n"); 1024 return -EBUSY; 1025 } 1026 1027 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 1028 ocelot_vlan_mode(ocelot, port, features); 1029 1030 return 0; 1031 } 1032 1033 static int ocelot_get_port_parent_id(struct net_device *dev, 1034 struct netdev_phys_item_id *ppid) 1035 { 1036 struct ocelot_port_private *priv = netdev_priv(dev); 1037 struct ocelot *ocelot = priv->port.ocelot; 1038 1039 ppid->id_len = sizeof(ocelot->base_mac); 1040 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len); 1041 1042 return 0; 1043 } 1044 1045 static int ocelot_hwstamp_get(struct ocelot *ocelot, int port, 1046 struct ifreq *ifr) 1047 { 1048 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1049 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1050 } 1051 1052 static int ocelot_hwstamp_set(struct ocelot *ocelot, int port, 1053 struct ifreq *ifr) 1054 { 1055 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1056 struct hwtstamp_config cfg; 1057 1058 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1059 return -EFAULT; 1060 1061 /* reserved for future extensions */ 1062 if (cfg.flags) 1063 return -EINVAL; 1064 1065 /* Tx type sanity check */ 1066 switch (cfg.tx_type) { 1067 case HWTSTAMP_TX_ON: 1068 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1069 break; 1070 case HWTSTAMP_TX_ONESTEP_SYNC: 1071 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1072 * need to update the origin time. 1073 */ 1074 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1075 break; 1076 case HWTSTAMP_TX_OFF: 1077 ocelot_port->ptp_cmd = 0; 1078 break; 1079 default: 1080 return -ERANGE; 1081 } 1082 1083 mutex_lock(&ocelot->ptp_lock); 1084 1085 switch (cfg.rx_filter) { 1086 case HWTSTAMP_FILTER_NONE: 1087 break; 1088 case HWTSTAMP_FILTER_ALL: 1089 case HWTSTAMP_FILTER_SOME: 1090 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1091 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1092 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1093 case HWTSTAMP_FILTER_NTP_ALL: 1094 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1095 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1096 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1097 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1098 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1099 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1100 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1101 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1102 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1103 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1104 break; 1105 default: 1106 mutex_unlock(&ocelot->ptp_lock); 1107 return -ERANGE; 1108 } 1109 1110 /* Commit back the result & save it */ 1111 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1112 mutex_unlock(&ocelot->ptp_lock); 1113 1114 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1115 } 1116 1117 static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1118 { 1119 struct ocelot_port_private *priv = netdev_priv(dev); 1120 struct ocelot *ocelot = priv->port.ocelot; 1121 int port = priv->chip_port; 1122 1123 /* The function is only used for PTP operations for now */ 1124 if (!ocelot->ptp) 1125 return -EOPNOTSUPP; 1126 1127 switch (cmd) { 1128 case SIOCSHWTSTAMP: 1129 return ocelot_hwstamp_set(ocelot, port, ifr); 1130 case SIOCGHWTSTAMP: 1131 return ocelot_hwstamp_get(ocelot, port, ifr); 1132 default: 1133 return -EOPNOTSUPP; 1134 } 1135 } 1136 1137 static const struct net_device_ops ocelot_port_netdev_ops = { 1138 .ndo_open = ocelot_port_open, 1139 .ndo_stop = ocelot_port_stop, 1140 .ndo_start_xmit = ocelot_port_xmit, 1141 .ndo_set_rx_mode = ocelot_set_rx_mode, 1142 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 1143 .ndo_set_mac_address = ocelot_port_set_mac_address, 1144 .ndo_get_stats64 = ocelot_get_stats64, 1145 .ndo_fdb_add = ocelot_port_fdb_add, 1146 .ndo_fdb_del = ocelot_port_fdb_del, 1147 .ndo_fdb_dump = ocelot_port_fdb_dump, 1148 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 1149 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 1150 .ndo_set_features = ocelot_set_features, 1151 .ndo_get_port_parent_id = ocelot_get_port_parent_id, 1152 .ndo_setup_tc = ocelot_setup_tc, 1153 .ndo_do_ioctl = ocelot_ioctl, 1154 }; 1155 1156 static void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, 1157 u8 *data) 1158 { 1159 int i; 1160 1161 if (sset != ETH_SS_STATS) 1162 return; 1163 1164 for (i = 0; i < ocelot->num_stats; i++) 1165 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1166 ETH_GSTRING_LEN); 1167 } 1168 1169 static void ocelot_port_get_strings(struct net_device *netdev, u32 sset, 1170 u8 *data) 1171 { 1172 struct ocelot_port_private *priv = netdev_priv(netdev); 1173 struct ocelot *ocelot = priv->port.ocelot; 1174 int port = priv->chip_port; 1175 1176 ocelot_get_strings(ocelot, port, sset, data); 1177 } 1178 1179 static void ocelot_update_stats(struct ocelot *ocelot) 1180 { 1181 int i, j; 1182 1183 mutex_lock(&ocelot->stats_lock); 1184 1185 for (i = 0; i < ocelot->num_phys_ports; i++) { 1186 /* Configure the port to read the stats from */ 1187 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1188 1189 for (j = 0; j < ocelot->num_stats; j++) { 1190 u32 val; 1191 unsigned int idx = i * ocelot->num_stats + j; 1192 1193 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1194 ocelot->stats_layout[j].offset); 1195 1196 if (val < (ocelot->stats[idx] & U32_MAX)) 1197 ocelot->stats[idx] += (u64)1 << 32; 1198 1199 ocelot->stats[idx] = (ocelot->stats[idx] & 1200 ~(u64)U32_MAX) + val; 1201 } 1202 } 1203 1204 mutex_unlock(&ocelot->stats_lock); 1205 } 1206 1207 static void ocelot_check_stats_work(struct work_struct *work) 1208 { 1209 struct delayed_work *del_work = to_delayed_work(work); 1210 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1211 stats_work); 1212 1213 ocelot_update_stats(ocelot); 1214 1215 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1216 OCELOT_STATS_CHECK_DELAY); 1217 } 1218 1219 static void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1220 { 1221 int i; 1222 1223 /* check and update now */ 1224 ocelot_update_stats(ocelot); 1225 1226 /* Copy all counters */ 1227 for (i = 0; i < ocelot->num_stats; i++) 1228 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1229 } 1230 1231 static void ocelot_port_get_ethtool_stats(struct net_device *dev, 1232 struct ethtool_stats *stats, 1233 u64 *data) 1234 { 1235 struct ocelot_port_private *priv = netdev_priv(dev); 1236 struct ocelot *ocelot = priv->port.ocelot; 1237 int port = priv->chip_port; 1238 1239 ocelot_get_ethtool_stats(ocelot, port, data); 1240 } 1241 1242 static int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1243 { 1244 if (sset != ETH_SS_STATS) 1245 return -EOPNOTSUPP; 1246 1247 return ocelot->num_stats; 1248 } 1249 1250 static int ocelot_port_get_sset_count(struct net_device *dev, int sset) 1251 { 1252 struct ocelot_port_private *priv = netdev_priv(dev); 1253 struct ocelot *ocelot = priv->port.ocelot; 1254 int port = priv->chip_port; 1255 1256 return ocelot_get_sset_count(ocelot, port, sset); 1257 } 1258 1259 static int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1260 struct ethtool_ts_info *info) 1261 { 1262 info->phc_index = ocelot->ptp_clock ? 1263 ptp_clock_index(ocelot->ptp_clock) : -1; 1264 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1265 SOF_TIMESTAMPING_RX_SOFTWARE | 1266 SOF_TIMESTAMPING_SOFTWARE | 1267 SOF_TIMESTAMPING_TX_HARDWARE | 1268 SOF_TIMESTAMPING_RX_HARDWARE | 1269 SOF_TIMESTAMPING_RAW_HARDWARE; 1270 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1271 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1272 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1273 1274 return 0; 1275 } 1276 1277 static int ocelot_port_get_ts_info(struct net_device *dev, 1278 struct ethtool_ts_info *info) 1279 { 1280 struct ocelot_port_private *priv = netdev_priv(dev); 1281 struct ocelot *ocelot = priv->port.ocelot; 1282 int port = priv->chip_port; 1283 1284 if (!ocelot->ptp) 1285 return ethtool_op_get_ts_info(dev, info); 1286 1287 return ocelot_get_ts_info(ocelot, port, info); 1288 } 1289 1290 static const struct ethtool_ops ocelot_ethtool_ops = { 1291 .get_strings = ocelot_port_get_strings, 1292 .get_ethtool_stats = ocelot_port_get_ethtool_stats, 1293 .get_sset_count = ocelot_port_get_sset_count, 1294 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1295 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1296 .get_ts_info = ocelot_port_get_ts_info, 1297 }; 1298 1299 static void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, 1300 u8 state) 1301 { 1302 u32 port_cfg; 1303 int p, i; 1304 1305 if (!(BIT(port) & ocelot->bridge_mask)) 1306 return; 1307 1308 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1309 1310 switch (state) { 1311 case BR_STATE_FORWARDING: 1312 ocelot->bridge_fwd_mask |= BIT(port); 1313 /* Fallthrough */ 1314 case BR_STATE_LEARNING: 1315 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1316 break; 1317 1318 default: 1319 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1320 ocelot->bridge_fwd_mask &= ~BIT(port); 1321 break; 1322 } 1323 1324 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 1325 1326 /* Apply FWD mask. The loop is needed to add/remove the current port as 1327 * a source for the other ports. 1328 */ 1329 for (p = 0; p < ocelot->num_phys_ports; p++) { 1330 if (p == ocelot->cpu || (ocelot->bridge_fwd_mask & BIT(p))) { 1331 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 1332 1333 for (i = 0; i < ocelot->num_phys_ports; i++) { 1334 unsigned long bond_mask = ocelot->lags[i]; 1335 1336 if (!bond_mask) 1337 continue; 1338 1339 if (bond_mask & BIT(p)) { 1340 mask &= ~bond_mask; 1341 break; 1342 } 1343 } 1344 1345 /* Avoid the NPI port from looping back to itself */ 1346 if (p != ocelot->cpu) 1347 mask |= BIT(ocelot->cpu); 1348 1349 ocelot_write_rix(ocelot, mask, 1350 ANA_PGID_PGID, PGID_SRC + p); 1351 } else { 1352 /* Only the CPU port, this is compatible with link 1353 * aggregation. 1354 */ 1355 ocelot_write_rix(ocelot, 1356 BIT(ocelot->cpu), 1357 ANA_PGID_PGID, PGID_SRC + p); 1358 } 1359 } 1360 } 1361 1362 static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port, 1363 struct switchdev_trans *trans, 1364 u8 state) 1365 { 1366 if (switchdev_trans_ph_prepare(trans)) 1367 return; 1368 1369 ocelot_bridge_stp_state_set(ocelot, port, state); 1370 } 1371 1372 static void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1373 { 1374 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(msecs / 2), 1375 ANA_AUTOAGE); 1376 } 1377 1378 static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port, 1379 unsigned long ageing_clock_t) 1380 { 1381 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1382 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 1383 1384 ocelot_set_ageing_time(ocelot, ageing_time); 1385 } 1386 1387 static void ocelot_port_attr_mc_set(struct ocelot *ocelot, int port, bool mc) 1388 { 1389 u32 cpu_fwd_mcast = ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1390 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1391 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1392 u32 val = 0; 1393 1394 if (mc) 1395 val = cpu_fwd_mcast; 1396 1397 ocelot_rmw_gix(ocelot, val, cpu_fwd_mcast, 1398 ANA_PORT_CPU_FWD_CFG, port); 1399 } 1400 1401 static int ocelot_port_attr_set(struct net_device *dev, 1402 const struct switchdev_attr *attr, 1403 struct switchdev_trans *trans) 1404 { 1405 struct ocelot_port_private *priv = netdev_priv(dev); 1406 struct ocelot *ocelot = priv->port.ocelot; 1407 int port = priv->chip_port; 1408 int err = 0; 1409 1410 switch (attr->id) { 1411 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1412 ocelot_port_attr_stp_state_set(ocelot, port, trans, 1413 attr->u.stp_state); 1414 break; 1415 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1416 ocelot_port_attr_ageing_set(ocelot, port, attr->u.ageing_time); 1417 break; 1418 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1419 priv->vlan_aware = attr->u.vlan_filtering; 1420 ocelot_port_vlan_filtering(ocelot, port, priv->vlan_aware); 1421 break; 1422 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1423 ocelot_port_attr_mc_set(ocelot, port, !attr->u.mc_disabled); 1424 break; 1425 default: 1426 err = -EOPNOTSUPP; 1427 break; 1428 } 1429 1430 return err; 1431 } 1432 1433 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1434 const struct switchdev_obj_port_vlan *vlan, 1435 struct switchdev_trans *trans) 1436 { 1437 int ret; 1438 u16 vid; 1439 1440 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1441 ret = ocelot_vlan_vid_add(dev, vid, 1442 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1443 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1444 if (ret) 1445 return ret; 1446 } 1447 1448 return 0; 1449 } 1450 1451 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1452 const struct switchdev_obj_port_vlan *vlan) 1453 { 1454 int ret; 1455 u16 vid; 1456 1457 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1458 ret = ocelot_vlan_vid_del(dev, vid); 1459 1460 if (ret) 1461 return ret; 1462 } 1463 1464 return 0; 1465 } 1466 1467 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1468 const unsigned char *addr, 1469 u16 vid) 1470 { 1471 struct ocelot_multicast *mc; 1472 1473 list_for_each_entry(mc, &ocelot->multicast, list) { 1474 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1475 return mc; 1476 } 1477 1478 return NULL; 1479 } 1480 1481 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1482 const struct switchdev_obj_port_mdb *mdb, 1483 struct switchdev_trans *trans) 1484 { 1485 struct ocelot_port_private *priv = netdev_priv(dev); 1486 struct ocelot_port *ocelot_port = &priv->port; 1487 struct ocelot *ocelot = ocelot_port->ocelot; 1488 unsigned char addr[ETH_ALEN]; 1489 struct ocelot_multicast *mc; 1490 int port = priv->chip_port; 1491 u16 vid = mdb->vid; 1492 bool new = false; 1493 1494 if (!vid) 1495 vid = ocelot_port->pvid; 1496 1497 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1498 if (!mc) { 1499 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1500 if (!mc) 1501 return -ENOMEM; 1502 1503 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1504 mc->vid = vid; 1505 1506 list_add_tail(&mc->list, &ocelot->multicast); 1507 new = true; 1508 } 1509 1510 memcpy(addr, mc->addr, ETH_ALEN); 1511 addr[0] = 0; 1512 1513 if (!new) { 1514 addr[2] = mc->ports << 0; 1515 addr[1] = mc->ports << 8; 1516 ocelot_mact_forget(ocelot, addr, vid); 1517 } 1518 1519 mc->ports |= BIT(port); 1520 addr[2] = mc->ports << 0; 1521 addr[1] = mc->ports << 8; 1522 1523 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1524 } 1525 1526 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1527 const struct switchdev_obj_port_mdb *mdb) 1528 { 1529 struct ocelot_port_private *priv = netdev_priv(dev); 1530 struct ocelot_port *ocelot_port = &priv->port; 1531 struct ocelot *ocelot = ocelot_port->ocelot; 1532 unsigned char addr[ETH_ALEN]; 1533 struct ocelot_multicast *mc; 1534 int port = priv->chip_port; 1535 u16 vid = mdb->vid; 1536 1537 if (!vid) 1538 vid = ocelot_port->pvid; 1539 1540 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1541 if (!mc) 1542 return -ENOENT; 1543 1544 memcpy(addr, mc->addr, ETH_ALEN); 1545 addr[2] = mc->ports << 0; 1546 addr[1] = mc->ports << 8; 1547 addr[0] = 0; 1548 ocelot_mact_forget(ocelot, addr, vid); 1549 1550 mc->ports &= ~BIT(port); 1551 if (!mc->ports) { 1552 list_del(&mc->list); 1553 devm_kfree(ocelot->dev, mc); 1554 return 0; 1555 } 1556 1557 addr[2] = mc->ports << 0; 1558 addr[1] = mc->ports << 8; 1559 1560 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1561 } 1562 1563 static int ocelot_port_obj_add(struct net_device *dev, 1564 const struct switchdev_obj *obj, 1565 struct switchdev_trans *trans, 1566 struct netlink_ext_ack *extack) 1567 { 1568 int ret = 0; 1569 1570 switch (obj->id) { 1571 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1572 ret = ocelot_port_obj_add_vlan(dev, 1573 SWITCHDEV_OBJ_PORT_VLAN(obj), 1574 trans); 1575 break; 1576 case SWITCHDEV_OBJ_ID_PORT_MDB: 1577 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1578 trans); 1579 break; 1580 default: 1581 return -EOPNOTSUPP; 1582 } 1583 1584 return ret; 1585 } 1586 1587 static int ocelot_port_obj_del(struct net_device *dev, 1588 const struct switchdev_obj *obj) 1589 { 1590 int ret = 0; 1591 1592 switch (obj->id) { 1593 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1594 ret = ocelot_port_vlan_del_vlan(dev, 1595 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1596 break; 1597 case SWITCHDEV_OBJ_ID_PORT_MDB: 1598 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1599 break; 1600 default: 1601 return -EOPNOTSUPP; 1602 } 1603 1604 return ret; 1605 } 1606 1607 static int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1608 struct net_device *bridge) 1609 { 1610 if (!ocelot->bridge_mask) { 1611 ocelot->hw_bridge_dev = bridge; 1612 } else { 1613 if (ocelot->hw_bridge_dev != bridge) 1614 /* This is adding the port to a second bridge, this is 1615 * unsupported */ 1616 return -ENODEV; 1617 } 1618 1619 ocelot->bridge_mask |= BIT(port); 1620 1621 return 0; 1622 } 1623 1624 static int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1625 struct net_device *bridge) 1626 { 1627 ocelot->bridge_mask &= ~BIT(port); 1628 1629 if (!ocelot->bridge_mask) 1630 ocelot->hw_bridge_dev = NULL; 1631 1632 ocelot_port_vlan_filtering(ocelot, port, 0); 1633 ocelot_port_set_pvid(ocelot, port, 0); 1634 return ocelot_port_set_native_vlan(ocelot, port, 0); 1635 } 1636 1637 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1638 { 1639 int i, port, lag; 1640 1641 /* Reset destination and aggregation PGIDS */ 1642 for (port = 0; port < ocelot->num_phys_ports; port++) 1643 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1644 1645 for (i = PGID_AGGR; i < PGID_SRC; i++) 1646 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1647 ANA_PGID_PGID, i); 1648 1649 /* Now, set PGIDs for each LAG */ 1650 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1651 unsigned long bond_mask; 1652 int aggr_count = 0; 1653 u8 aggr_idx[16]; 1654 1655 bond_mask = ocelot->lags[lag]; 1656 if (!bond_mask) 1657 continue; 1658 1659 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1660 // Destination mask 1661 ocelot_write_rix(ocelot, bond_mask, 1662 ANA_PGID_PGID, port); 1663 aggr_idx[aggr_count] = port; 1664 aggr_count++; 1665 } 1666 1667 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1668 u32 ac; 1669 1670 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1671 ac &= ~bond_mask; 1672 ac |= BIT(aggr_idx[i % aggr_count]); 1673 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1674 } 1675 } 1676 } 1677 1678 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1679 { 1680 unsigned long bond_mask = ocelot->lags[lag]; 1681 unsigned int p; 1682 1683 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1684 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1685 1686 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1687 1688 /* Use lag port as logical port for port i */ 1689 ocelot_write_gix(ocelot, port_cfg | 1690 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1691 ANA_PORT_PORT_CFG, p); 1692 } 1693 } 1694 1695 static int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1696 struct net_device *bond) 1697 { 1698 struct net_device *ndev; 1699 u32 bond_mask = 0; 1700 int lag, lp; 1701 1702 rcu_read_lock(); 1703 for_each_netdev_in_bond_rcu(bond, ndev) { 1704 struct ocelot_port_private *priv = netdev_priv(ndev); 1705 1706 bond_mask |= BIT(priv->chip_port); 1707 } 1708 rcu_read_unlock(); 1709 1710 lp = __ffs(bond_mask); 1711 1712 /* If the new port is the lowest one, use it as the logical port from 1713 * now on 1714 */ 1715 if (port == lp) { 1716 lag = port; 1717 ocelot->lags[port] = bond_mask; 1718 bond_mask &= ~BIT(port); 1719 if (bond_mask) { 1720 lp = __ffs(bond_mask); 1721 ocelot->lags[lp] = 0; 1722 } 1723 } else { 1724 lag = lp; 1725 ocelot->lags[lp] |= BIT(port); 1726 } 1727 1728 ocelot_setup_lag(ocelot, lag); 1729 ocelot_set_aggr_pgids(ocelot); 1730 1731 return 0; 1732 } 1733 1734 static void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1735 struct net_device *bond) 1736 { 1737 u32 port_cfg; 1738 int i; 1739 1740 /* Remove port from any lag */ 1741 for (i = 0; i < ocelot->num_phys_ports; i++) 1742 ocelot->lags[i] &= ~BIT(port); 1743 1744 /* if it was the logical port of the lag, move the lag config to the 1745 * next port 1746 */ 1747 if (ocelot->lags[port]) { 1748 int n = __ffs(ocelot->lags[port]); 1749 1750 ocelot->lags[n] = ocelot->lags[port]; 1751 ocelot->lags[port] = 0; 1752 1753 ocelot_setup_lag(ocelot, n); 1754 } 1755 1756 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1757 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1758 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1759 ANA_PORT_PORT_CFG, port); 1760 1761 ocelot_set_aggr_pgids(ocelot); 1762 } 1763 1764 /* Checks if the net_device instance given to us originate from our driver. */ 1765 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1766 { 1767 return dev->netdev_ops == &ocelot_port_netdev_ops; 1768 } 1769 1770 static int ocelot_netdevice_port_event(struct net_device *dev, 1771 unsigned long event, 1772 struct netdev_notifier_changeupper_info *info) 1773 { 1774 struct ocelot_port_private *priv = netdev_priv(dev); 1775 struct ocelot_port *ocelot_port = &priv->port; 1776 struct ocelot *ocelot = ocelot_port->ocelot; 1777 int port = priv->chip_port; 1778 int err = 0; 1779 1780 switch (event) { 1781 case NETDEV_CHANGEUPPER: 1782 if (netif_is_bridge_master(info->upper_dev)) { 1783 if (info->linking) { 1784 err = ocelot_port_bridge_join(ocelot, port, 1785 info->upper_dev); 1786 } else { 1787 err = ocelot_port_bridge_leave(ocelot, port, 1788 info->upper_dev); 1789 priv->vlan_aware = false; 1790 } 1791 } 1792 if (netif_is_lag_master(info->upper_dev)) { 1793 if (info->linking) 1794 err = ocelot_port_lag_join(ocelot, port, 1795 info->upper_dev); 1796 else 1797 ocelot_port_lag_leave(ocelot, port, 1798 info->upper_dev); 1799 } 1800 break; 1801 default: 1802 break; 1803 } 1804 1805 return err; 1806 } 1807 1808 static int ocelot_netdevice_event(struct notifier_block *unused, 1809 unsigned long event, void *ptr) 1810 { 1811 struct netdev_notifier_changeupper_info *info = ptr; 1812 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1813 int ret = 0; 1814 1815 if (!ocelot_netdevice_dev_check(dev)) 1816 return 0; 1817 1818 if (event == NETDEV_PRECHANGEUPPER && 1819 netif_is_lag_master(info->upper_dev)) { 1820 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1821 struct netlink_ext_ack *extack; 1822 1823 if (lag_upper_info && 1824 lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1825 extack = netdev_notifier_info_to_extack(&info->info); 1826 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1827 1828 ret = -EINVAL; 1829 goto notify; 1830 } 1831 } 1832 1833 if (netif_is_lag_master(dev)) { 1834 struct net_device *slave; 1835 struct list_head *iter; 1836 1837 netdev_for_each_lower_dev(dev, slave, iter) { 1838 ret = ocelot_netdevice_port_event(slave, event, info); 1839 if (ret) 1840 goto notify; 1841 } 1842 } else { 1843 ret = ocelot_netdevice_port_event(dev, event, info); 1844 } 1845 1846 notify: 1847 return notifier_from_errno(ret); 1848 } 1849 1850 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1851 .notifier_call = ocelot_netdevice_event, 1852 }; 1853 EXPORT_SYMBOL(ocelot_netdevice_nb); 1854 1855 static int ocelot_switchdev_event(struct notifier_block *unused, 1856 unsigned long event, void *ptr) 1857 { 1858 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1859 int err; 1860 1861 switch (event) { 1862 case SWITCHDEV_PORT_ATTR_SET: 1863 err = switchdev_handle_port_attr_set(dev, ptr, 1864 ocelot_netdevice_dev_check, 1865 ocelot_port_attr_set); 1866 return notifier_from_errno(err); 1867 } 1868 1869 return NOTIFY_DONE; 1870 } 1871 1872 struct notifier_block ocelot_switchdev_nb __read_mostly = { 1873 .notifier_call = ocelot_switchdev_event, 1874 }; 1875 EXPORT_SYMBOL(ocelot_switchdev_nb); 1876 1877 static int ocelot_switchdev_blocking_event(struct notifier_block *unused, 1878 unsigned long event, void *ptr) 1879 { 1880 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1881 int err; 1882 1883 switch (event) { 1884 /* Blocking events. */ 1885 case SWITCHDEV_PORT_OBJ_ADD: 1886 err = switchdev_handle_port_obj_add(dev, ptr, 1887 ocelot_netdevice_dev_check, 1888 ocelot_port_obj_add); 1889 return notifier_from_errno(err); 1890 case SWITCHDEV_PORT_OBJ_DEL: 1891 err = switchdev_handle_port_obj_del(dev, ptr, 1892 ocelot_netdevice_dev_check, 1893 ocelot_port_obj_del); 1894 return notifier_from_errno(err); 1895 case SWITCHDEV_PORT_ATTR_SET: 1896 err = switchdev_handle_port_attr_set(dev, ptr, 1897 ocelot_netdevice_dev_check, 1898 ocelot_port_attr_set); 1899 return notifier_from_errno(err); 1900 } 1901 1902 return NOTIFY_DONE; 1903 } 1904 1905 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = { 1906 .notifier_call = ocelot_switchdev_blocking_event, 1907 }; 1908 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb); 1909 1910 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts) 1911 { 1912 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1913 unsigned long flags; 1914 time64_t s; 1915 u32 val; 1916 s64 ns; 1917 1918 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1919 1920 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1921 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1922 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 1923 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1924 1925 s = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN) & 0xffff; 1926 s <<= 32; 1927 s += ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 1928 ns = ocelot_read_rix(ocelot, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 1929 1930 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1931 1932 /* Deal with negative values */ 1933 if (ns >= 0x3ffffff0 && ns <= 0x3fffffff) { 1934 s--; 1935 ns &= 0xf; 1936 ns += 999999984; 1937 } 1938 1939 set_normalized_timespec64(ts, s, ns); 1940 return 0; 1941 } 1942 EXPORT_SYMBOL(ocelot_ptp_gettime64); 1943 1944 static int ocelot_ptp_settime64(struct ptp_clock_info *ptp, 1945 const struct timespec64 *ts) 1946 { 1947 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1948 unsigned long flags; 1949 u32 val; 1950 1951 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1952 1953 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1954 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1955 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); 1956 1957 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1958 1959 ocelot_write_rix(ocelot, lower_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_LSB, 1960 TOD_ACC_PIN); 1961 ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB, 1962 TOD_ACC_PIN); 1963 ocelot_write_rix(ocelot, ts->tv_nsec, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 1964 1965 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1966 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1967 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD); 1968 1969 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1970 1971 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 1972 return 0; 1973 } 1974 1975 static int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 1976 { 1977 if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) { 1978 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1979 unsigned long flags; 1980 u32 val; 1981 1982 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 1983 1984 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1985 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1986 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); 1987 1988 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1989 1990 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 1991 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN); 1992 ocelot_write_rix(ocelot, delta, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 1993 1994 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 1995 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 1996 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA); 1997 1998 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 1999 2000 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2001 } else { 2002 /* Fall back using ocelot_ptp_settime64 which is not exact. */ 2003 struct timespec64 ts; 2004 u64 now; 2005 2006 ocelot_ptp_gettime64(ptp, &ts); 2007 2008 now = ktime_to_ns(timespec64_to_ktime(ts)); 2009 ts = ns_to_timespec64(now + delta); 2010 2011 ocelot_ptp_settime64(ptp, &ts); 2012 } 2013 return 0; 2014 } 2015 2016 static int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 2017 { 2018 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 2019 u32 unit = 0, direction = 0; 2020 unsigned long flags; 2021 u64 adj = 0; 2022 2023 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 2024 2025 if (!scaled_ppm) 2026 goto disable_adj; 2027 2028 if (scaled_ppm < 0) { 2029 direction = PTP_CFG_CLK_ADJ_CFG_DIR; 2030 scaled_ppm = -scaled_ppm; 2031 } 2032 2033 adj = PSEC_PER_SEC << 16; 2034 do_div(adj, scaled_ppm); 2035 do_div(adj, 1000); 2036 2037 /* If the adjustment value is too large, use ns instead */ 2038 if (adj >= (1L << 30)) { 2039 unit = PTP_CFG_CLK_ADJ_FREQ_NS; 2040 do_div(adj, 1000); 2041 } 2042 2043 /* Still too big */ 2044 if (adj >= (1L << 30)) 2045 goto disable_adj; 2046 2047 ocelot_write(ocelot, unit | adj, PTP_CLK_CFG_ADJ_FREQ); 2048 ocelot_write(ocelot, PTP_CFG_CLK_ADJ_CFG_ENA | direction, 2049 PTP_CLK_CFG_ADJ_CFG); 2050 2051 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2052 return 0; 2053 2054 disable_adj: 2055 ocelot_write(ocelot, 0, PTP_CLK_CFG_ADJ_CFG); 2056 2057 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2058 return 0; 2059 } 2060 2061 static struct ptp_clock_info ocelot_ptp_clock_info = { 2062 .owner = THIS_MODULE, 2063 .name = "ocelot ptp", 2064 .max_adj = 0x7fffffff, 2065 .n_alarm = 0, 2066 .n_ext_ts = 0, 2067 .n_per_out = 0, 2068 .n_pins = 0, 2069 .pps = 0, 2070 .gettime64 = ocelot_ptp_gettime64, 2071 .settime64 = ocelot_ptp_settime64, 2072 .adjtime = ocelot_ptp_adjtime, 2073 .adjfine = ocelot_ptp_adjfine, 2074 }; 2075 2076 static int ocelot_init_timestamp(struct ocelot *ocelot) 2077 { 2078 ocelot->ptp_info = ocelot_ptp_clock_info; 2079 ocelot->ptp_clock = ptp_clock_register(&ocelot->ptp_info, ocelot->dev); 2080 if (IS_ERR(ocelot->ptp_clock)) 2081 return PTR_ERR(ocelot->ptp_clock); 2082 /* Check if PHC support is missing at the configuration level */ 2083 if (!ocelot->ptp_clock) 2084 return 0; 2085 2086 ocelot_write(ocelot, SYS_PTP_CFG_PTP_STAMP_WID(30), SYS_PTP_CFG); 2087 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_LOW); 2088 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_HIGH); 2089 2090 ocelot_write(ocelot, PTP_CFG_MISC_PTP_EN, PTP_CFG_MISC); 2091 2092 /* There is no device reconfiguration, PTP Rx stamping is always 2093 * enabled. 2094 */ 2095 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 2096 2097 return 0; 2098 } 2099 2100 static void ocelot_init_port(struct ocelot *ocelot, int port) 2101 { 2102 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2103 int atop_wm; 2104 2105 INIT_LIST_HEAD(&ocelot_port->skbs); 2106 2107 /* Basic L2 initialization */ 2108 2109 /* Set MAC IFG Gaps 2110 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2111 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2112 */ 2113 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2114 DEV_MAC_IFG_CFG); 2115 2116 /* Load seed (0) and set MAC HDX late collision */ 2117 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2118 DEV_MAC_HDX_CFG_SEED_LOAD, 2119 DEV_MAC_HDX_CFG); 2120 mdelay(1); 2121 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2122 DEV_MAC_HDX_CFG); 2123 2124 /* Set Max Length and maximum tags allowed */ 2125 ocelot_port_writel(ocelot_port, VLAN_ETH_FRAME_LEN, 2126 DEV_MAC_MAXLEN_CFG); 2127 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2128 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2129 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2130 DEV_MAC_TAGS_CFG); 2131 2132 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2133 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2134 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2135 2136 /* Set Pause WM hysteresis 2137 * 152 = 6 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 2138 * 101 = 4 * VLAN_ETH_FRAME_LEN / OCELOT_BUFFER_CELL_SZ 2139 */ 2140 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 2141 SYS_PAUSE_CFG_PAUSE_STOP(101) | 2142 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port); 2143 2144 /* Tail dropping watermark */ 2145 atop_wm = (ocelot->shared_queue_sz - 9 * VLAN_ETH_FRAME_LEN) / OCELOT_BUFFER_CELL_SZ; 2146 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * VLAN_ETH_FRAME_LEN), 2147 SYS_ATOP, port); 2148 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 2149 2150 /* Drop frames with multicast source address */ 2151 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2152 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2153 ANA_PORT_DROP_CFG, port); 2154 2155 /* Set default VLAN and tag type to 8021Q. */ 2156 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2157 REW_PORT_VLAN_CFG_PORT_TPID_M, 2158 REW_PORT_VLAN_CFG, port); 2159 2160 /* Enable vcap lookups */ 2161 ocelot_vcap_enable(ocelot, port); 2162 } 2163 2164 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 2165 void __iomem *regs, 2166 struct phy_device *phy) 2167 { 2168 struct ocelot_port_private *priv; 2169 struct ocelot_port *ocelot_port; 2170 struct net_device *dev; 2171 int err; 2172 2173 dev = alloc_etherdev(sizeof(struct ocelot_port_private)); 2174 if (!dev) 2175 return -ENOMEM; 2176 SET_NETDEV_DEV(dev, ocelot->dev); 2177 priv = netdev_priv(dev); 2178 priv->dev = dev; 2179 priv->phy = phy; 2180 priv->chip_port = port; 2181 ocelot_port = &priv->port; 2182 ocelot_port->ocelot = ocelot; 2183 ocelot_port->regs = regs; 2184 ocelot->ports[port] = ocelot_port; 2185 2186 dev->netdev_ops = &ocelot_port_netdev_ops; 2187 dev->ethtool_ops = &ocelot_ethtool_ops; 2188 2189 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS | 2190 NETIF_F_HW_TC; 2191 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2192 2193 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 2194 dev->dev_addr[ETH_ALEN - 1] += port; 2195 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 2196 ENTRYTYPE_LOCKED); 2197 2198 ocelot_init_port(ocelot, port); 2199 2200 err = register_netdev(dev); 2201 if (err) { 2202 dev_err(ocelot->dev, "register_netdev failed\n"); 2203 free_netdev(dev); 2204 } 2205 2206 return err; 2207 } 2208 EXPORT_SYMBOL(ocelot_probe_port); 2209 2210 void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu, 2211 enum ocelot_tag_prefix injection, 2212 enum ocelot_tag_prefix extraction) 2213 { 2214 /* Configure and enable the CPU port. */ 2215 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2216 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2217 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2218 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2219 ANA_PORT_PORT_CFG, cpu); 2220 2221 /* If the CPU port is a physical port, set up the port in Node 2222 * Processor Interface (NPI) mode. This is the mode through which 2223 * frames can be injected from and extracted to an external CPU. 2224 * Only one port can be an NPI at the same time. 2225 */ 2226 if (cpu < ocelot->num_phys_ports) { 2227 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 2228 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(cpu), 2229 QSYS_EXT_CPU_CFG); 2230 } 2231 2232 /* CPU port Injection/Extraction configuration */ 2233 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 2234 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 2235 QSYS_SWITCH_PORT_MODE_PORT_ENA, 2236 QSYS_SWITCH_PORT_MODE, cpu); 2237 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) | 2238 SYS_PORT_MODE_INCL_INJ_HDR(injection), 2239 SYS_PORT_MODE, cpu); 2240 2241 /* Configure the CPU port to be VLAN aware */ 2242 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 2243 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2244 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2245 ANA_PORT_VLAN_CFG, cpu); 2246 2247 ocelot->cpu = cpu; 2248 } 2249 EXPORT_SYMBOL(ocelot_set_cpu_port); 2250 2251 int ocelot_init(struct ocelot *ocelot) 2252 { 2253 char queue_name[32]; 2254 int i, ret; 2255 u32 port; 2256 2257 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 2258 sizeof(u32), GFP_KERNEL); 2259 if (!ocelot->lags) 2260 return -ENOMEM; 2261 2262 ocelot->stats = devm_kcalloc(ocelot->dev, 2263 ocelot->num_phys_ports * ocelot->num_stats, 2264 sizeof(u64), GFP_KERNEL); 2265 if (!ocelot->stats) 2266 return -ENOMEM; 2267 2268 mutex_init(&ocelot->stats_lock); 2269 mutex_init(&ocelot->ptp_lock); 2270 spin_lock_init(&ocelot->ptp_clock_lock); 2271 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2272 dev_name(ocelot->dev)); 2273 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2274 if (!ocelot->stats_queue) 2275 return -ENOMEM; 2276 2277 INIT_LIST_HEAD(&ocelot->multicast); 2278 ocelot_mact_init(ocelot); 2279 ocelot_vlan_init(ocelot); 2280 ocelot_ace_init(ocelot); 2281 2282 for (port = 0; port < ocelot->num_phys_ports; port++) { 2283 /* Clear all counters (5 groups) */ 2284 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2285 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2286 SYS_STAT_CFG); 2287 } 2288 2289 /* Only use S-Tag */ 2290 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2291 2292 /* Aggregation mode */ 2293 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2294 ANA_AGGR_CFG_AC_DMAC_ENA | 2295 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2296 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 2297 2298 /* Set MAC age time to default value. The entry is aged after 2299 * 2*AGE_PERIOD 2300 */ 2301 ocelot_write(ocelot, 2302 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2303 ANA_AUTOAGE); 2304 2305 /* Disable learning for frames discarded by VLAN ingress filtering */ 2306 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2307 2308 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2309 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2310 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2311 2312 /* Setup flooding PGIDs */ 2313 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2314 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 2315 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2316 ANA_FLOODING, 0); 2317 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2318 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2319 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2320 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2321 ANA_FLOODING_IPMC); 2322 2323 for (port = 0; port < ocelot->num_phys_ports; port++) { 2324 /* Transmit the frame to the local port. */ 2325 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2326 /* Do not forward BPDU frames to the front ports. */ 2327 ocelot_write_gix(ocelot, 2328 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2329 ANA_PORT_CPU_FWD_BPDU_CFG, 2330 port); 2331 /* Ensure bridging is disabled */ 2332 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2333 } 2334 2335 /* Allow broadcast MAC frames. */ 2336 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 2337 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2338 2339 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2340 } 2341 ocelot_write_rix(ocelot, 2342 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 2343 ANA_PGID_PGID, PGID_MC); 2344 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2345 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2346 2347 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2348 * registers endianness. 2349 */ 2350 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2351 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2352 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2353 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2354 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2355 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2356 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2357 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2358 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2359 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2360 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2361 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2362 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2363 for (i = 0; i < 16; i++) 2364 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2365 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2366 ANA_CPUQ_8021_CFG, i); 2367 2368 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2369 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2370 OCELOT_STATS_CHECK_DELAY); 2371 2372 if (ocelot->ptp) { 2373 ret = ocelot_init_timestamp(ocelot); 2374 if (ret) { 2375 dev_err(ocelot->dev, 2376 "Timestamp initialization failed\n"); 2377 return ret; 2378 } 2379 } 2380 2381 return 0; 2382 } 2383 EXPORT_SYMBOL(ocelot_init); 2384 2385 void ocelot_deinit(struct ocelot *ocelot) 2386 { 2387 struct list_head *pos, *tmp; 2388 struct ocelot_port *port; 2389 struct ocelot_skb *entry; 2390 int i; 2391 2392 cancel_delayed_work(&ocelot->stats_work); 2393 destroy_workqueue(ocelot->stats_queue); 2394 mutex_destroy(&ocelot->stats_lock); 2395 ocelot_ace_deinit(); 2396 2397 for (i = 0; i < ocelot->num_phys_ports; i++) { 2398 port = ocelot->ports[i]; 2399 2400 list_for_each_safe(pos, tmp, &port->skbs) { 2401 entry = list_entry(pos, struct ocelot_skb, head); 2402 2403 list_del(pos); 2404 dev_kfree_skb_any(entry->skb); 2405 kfree(entry); 2406 } 2407 } 2408 } 2409 EXPORT_SYMBOL(ocelot_deinit); 2410 2411 MODULE_LICENSE("Dual MIT/GPL"); 2412