ixgbe.h (9c63cd5a955ce8a3de1776a9e4b6b89c69b2a09e) ixgbe.h (800bd607c31e648267e8a1055b14ad27bde943f5)
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.

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273#define IXGBE_MAX_FCOE_INDICES 8
274#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
275#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
276#else
277#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
278#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
279#endif /* IXGBE_FCOE */
280struct ixgbe_ring_feature {
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.

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273#define IXGBE_MAX_FCOE_INDICES 8
274#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
275#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
276#else
277#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
278#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
279#endif /* IXGBE_FCOE */
280struct ixgbe_ring_feature {
281 int indices;
282 int mask;
281 u16 limit; /* upper limit on feature indices */
282 u16 indices; /* current value of indices */
283 u16 mask; /* Mask used for feature to ring mapping */
284 u16 offset; /* offset to start of feature */
283} ____cacheline_internodealigned_in_smp;
284
285/*
286 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
287 * this is twice the size of a half page we need to double the page order
288 * for FCoE enabled Rx queues.
289 */
290#if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)

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310/* iterator for handling rings in ring container */
311#define ixgbe_for_each_ring(pos, head) \
312 for (pos = (head).ring; pos != NULL; pos = pos->next)
313
314#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
315 ? 8 : 1)
316#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
317
285} ____cacheline_internodealigned_in_smp;
286
287/*
288 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
289 * this is twice the size of a half page we need to double the page order
290 * for FCoE enabled Rx queues.
291 */
292#if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)

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312/* iterator for handling rings in ring container */
313#define ixgbe_for_each_ring(pos, head) \
314 for (pos = (head).ring; pos != NULL; pos = pos->next)
315
316#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
317 ? 8 : 1)
318#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
319
318/* MAX_MSIX_Q_VECTORS of these are allocated,
320/* MAX_Q_VECTORS of these are allocated,
319 * but we only use one per queue-specific vector.
320 */
321struct ixgbe_q_vector {
322 struct ixgbe_adapter *adapter;
323#ifdef CONFIG_IXGBE_DCA
324 int cpu; /* CPU for DCA */
325#endif
326 u16 v_idx; /* index of q_vector within array, also used for

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396/* Use 3K as the baby jumbo frame size for FCoE */
397#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
398#endif /* IXGBE_FCOE */
399
400#define OTHER_VECTOR 1
401#define NON_Q_VECTORS (OTHER_VECTOR)
402
403#define MAX_MSIX_VECTORS_82599 64
321 * but we only use one per queue-specific vector.
322 */
323struct ixgbe_q_vector {
324 struct ixgbe_adapter *adapter;
325#ifdef CONFIG_IXGBE_DCA
326 int cpu; /* CPU for DCA */
327#endif
328 u16 v_idx; /* index of q_vector within array, also used for

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398/* Use 3K as the baby jumbo frame size for FCoE */
399#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
400#endif /* IXGBE_FCOE */
401
402#define OTHER_VECTOR 1
403#define NON_Q_VECTORS (OTHER_VECTOR)
404
405#define MAX_MSIX_VECTORS_82599 64
404#define MAX_MSIX_Q_VECTORS_82599 64
406#define MAX_Q_VECTORS_82599 64
405#define MAX_MSIX_VECTORS_82598 18
407#define MAX_MSIX_VECTORS_82598 18
406#define MAX_MSIX_Q_VECTORS_82598 16
408#define MAX_Q_VECTORS_82598 16
407
409
408#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
410#define MAX_Q_VECTORS MAX_Q_VECTORS_82599
409#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
410
411#define MIN_MSIX_Q_VECTORS 1
412#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
413
414/* default to trying for four seconds */
415#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
416

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491 u64 hw_csum_rx_error;
492 u64 hw_rx_no_dma_resources;
493 u64 rsc_total_count;
494 u64 rsc_total_flush;
495 u64 non_eop_descs;
496 u32 alloc_rx_page_failed;
497 u32 alloc_rx_buff_failed;
498
411#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
412
413#define MIN_MSIX_Q_VECTORS 1
414#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
415
416/* default to trying for four seconds */
417#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
418

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493 u64 hw_csum_rx_error;
494 u64 hw_rx_no_dma_resources;
495 u64 rsc_total_count;
496 u64 rsc_total_flush;
497 u64 non_eop_descs;
498 u32 alloc_rx_page_failed;
499 u32 alloc_rx_buff_failed;
500
499 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
501 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
500
501 /* DCB parameters */
502 struct ieee_pfc *ixgbe_ieee_pfc;
503 struct ieee_ets *ixgbe_ieee_ets;
504 struct ixgbe_dcb_config dcb_cfg;
505 struct ixgbe_dcb_config temp_dcb_cfg;
506 u8 dcb_set_bitmap;
507 u8 dcbx_cap;
508 enum ixgbe_fc_mode last_lfc_mode;
509
502
503 /* DCB parameters */
504 struct ieee_pfc *ixgbe_ieee_pfc;
505 struct ieee_ets *ixgbe_ieee_ets;
506 struct ixgbe_dcb_config dcb_cfg;
507 struct ixgbe_dcb_config temp_dcb_cfg;
508 u8 dcb_set_bitmap;
509 u8 dcbx_cap;
510 enum ixgbe_fc_mode last_lfc_mode;
511
510 int num_msix_vectors;
511 int max_msix_q_vectors; /* true count of q_vectors for device */
512 int num_q_vectors; /* current number of q_vectors for device */
513 int max_q_vectors; /* true count of q_vectors for device */
512 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
513 struct msix_entry *msix_entries;
514
515 u32 test_icr;
516 struct ixgbe_ring test_tx_ring;
517 struct ixgbe_ring test_rx_ring;
518
519 /* structs defined in ixgbe_hw.h */

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556
557#ifdef CONFIG_IXGBE_PTP
558 struct ptp_clock *ptp_clock;
559 struct ptp_clock_info ptp_caps;
560 unsigned long last_overflow_check;
561 spinlock_t tmreg_lock;
562 struct cyclecounter cc;
563 struct timecounter tc;
514 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
515 struct msix_entry *msix_entries;
516
517 u32 test_icr;
518 struct ixgbe_ring test_tx_ring;
519 struct ixgbe_ring test_rx_ring;
520
521 /* structs defined in ixgbe_hw.h */

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558
559#ifdef CONFIG_IXGBE_PTP
560 struct ptp_clock *ptp_clock;
561 struct ptp_clock_info ptp_caps;
562 unsigned long last_overflow_check;
563 spinlock_t tmreg_lock;
564 struct cyclecounter cc;
565 struct timecounter tc;
566 int rx_hwtstamp_filter;
564 u32 base_incval;
565 u32 cycle_speed;
566#endif /* CONFIG_IXGBE_PTP */
567
568 /* SR-IOV */
569 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
570 unsigned int num_vfs;
571 struct vf_data_storage *vfinfo;

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699extern int ixgbe_fcoe_disable(struct net_device *netdev);
700#ifdef CONFIG_IXGBE_DCB
701extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
702extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
703#endif /* CONFIG_IXGBE_DCB */
704extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
705extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
706 struct netdev_fcoe_hbainfo *info);
567 u32 base_incval;
568 u32 cycle_speed;
569#endif /* CONFIG_IXGBE_PTP */
570
571 /* SR-IOV */
572 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
573 unsigned int num_vfs;
574 struct vf_data_storage *vfinfo;

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702extern int ixgbe_fcoe_disable(struct net_device *netdev);
703#ifdef CONFIG_IXGBE_DCB
704extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
705extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
706#endif /* CONFIG_IXGBE_DCB */
707extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
708extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
709 struct netdev_fcoe_hbainfo *info);
710extern u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
707#endif /* IXGBE_FCOE */
708
709static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
710{
711 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
712}
713
714#ifdef CONFIG_IXGBE_PTP
715extern void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
716extern void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
717extern void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
718extern void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector,
719 struct sk_buff *skb);
720extern void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
711#endif /* IXGBE_FCOE */
712
713static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
714{
715 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
716}
717
718#ifdef CONFIG_IXGBE_PTP
719extern void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
720extern void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
721extern void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
722extern void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector,
723 struct sk_buff *skb);
724extern void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
725 union ixgbe_adv_rx_desc *rx_desc,
721 struct sk_buff *skb);
722extern int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
723 struct ifreq *ifr, int cmd);
724extern void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
725extern void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
726#endif /* CONFIG_IXGBE_PTP */
727
728#endif /* _IXGBE_H_ */
726 struct sk_buff *skb);
727extern int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
728 struct ifreq *ifr, int cmd);
729extern void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
730extern void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
731#endif /* CONFIG_IXGBE_PTP */
732
733#endif /* _IXGBE_H_ */