1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #ifndef _IXGBE_H_ 29 #define _IXGBE_H_ 30 31 #include <linux/bitops.h> 32 #include <linux/types.h> 33 #include <linux/pci.h> 34 #include <linux/netdevice.h> 35 #include <linux/cpumask.h> 36 #include <linux/aer.h> 37 #include <linux/if_vlan.h> 38 39 #ifdef CONFIG_IXGBE_PTP 40 #include <linux/clocksource.h> 41 #include <linux/net_tstamp.h> 42 #include <linux/ptp_clock_kernel.h> 43 #endif /* CONFIG_IXGBE_PTP */ 44 45 #include "ixgbe_type.h" 46 #include "ixgbe_common.h" 47 #include "ixgbe_dcb.h" 48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 49 #define IXGBE_FCOE 50 #include "ixgbe_fcoe.h" 51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ 52 #ifdef CONFIG_IXGBE_DCA 53 #include <linux/dca.h> 54 #endif 55 56 /* common prefix used by pr_<> macros */ 57 #undef pr_fmt 58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 59 60 /* TX/RX descriptor defines */ 61 #define IXGBE_DEFAULT_TXD 512 62 #define IXGBE_DEFAULT_TX_WORK 256 63 #define IXGBE_MAX_TXD 4096 64 #define IXGBE_MIN_TXD 64 65 66 #define IXGBE_DEFAULT_RXD 512 67 #define IXGBE_MAX_RXD 4096 68 #define IXGBE_MIN_RXD 64 69 70 /* flow control */ 71 #define IXGBE_MIN_FCRTL 0x40 72 #define IXGBE_MAX_FCRTL 0x7FF80 73 #define IXGBE_MIN_FCRTH 0x600 74 #define IXGBE_MAX_FCRTH 0x7FFF0 75 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 76 #define IXGBE_MIN_FCPAUSE 0 77 #define IXGBE_MAX_FCPAUSE 0xFFFF 78 79 /* Supported Rx Buffer Sizes */ 80 #define IXGBE_RXBUFFER_512 512 /* Used for packet split */ 81 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 82 83 /* 84 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we 85 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 86 * this adds up to 512 bytes of extra data meaning the smallest allocation 87 * we could have is 1K. 88 * i.e. RXBUFFER_512 --> size-1024 slab 89 */ 90 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512 91 92 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 93 94 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 95 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 96 97 #define IXGBE_TX_FLAGS_CSUM (u32)(1) 98 #define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1) 99 #define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2) 100 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 3) 101 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4) 102 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5) 103 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 6) 104 #define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7) 105 #define IXGBE_TX_FLAGS_TSTAMP (u32)(1 << 8) 106 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 107 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 108 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 109 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 110 111 #define IXGBE_MAX_VF_MC_ENTRIES 30 112 #define IXGBE_MAX_VF_FUNCTIONS 64 113 #define IXGBE_MAX_VFTA_ENTRIES 128 114 #define MAX_EMULATION_MAC_ADDRS 16 115 #define IXGBE_MAX_PF_MACVLANS 15 116 #define VMDQ_P(p) ((p) + adapter->num_vfs) 117 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 118 #define IXGBE_X540_VF_DEVICE_ID 0x1515 119 120 struct vf_data_storage { 121 unsigned char vf_mac_addresses[ETH_ALEN]; 122 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 123 u16 num_vf_mc_hashes; 124 u16 default_vf_vlan_id; 125 u16 vlans_enabled; 126 bool clear_to_send; 127 bool pf_set_mac; 128 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 129 u16 pf_qos; 130 u16 tx_rate; 131 u16 vlan_count; 132 u8 spoofchk_enabled; 133 struct pci_dev *vfdev; 134 }; 135 136 struct vf_macvlans { 137 struct list_head l; 138 int vf; 139 int rar_entry; 140 bool free; 141 bool is_macvlan; 142 u8 vf_macvlan[ETH_ALEN]; 143 }; 144 145 #define IXGBE_MAX_TXD_PWR 14 146 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) 147 148 /* Tx Descriptors needed, worst case */ 149 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 150 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4) 151 152 /* wrapper around a pointer to a socket buffer, 153 * so a DMA handle can be stored along with the buffer */ 154 struct ixgbe_tx_buffer { 155 union ixgbe_adv_tx_desc *next_to_watch; 156 unsigned long time_stamp; 157 struct sk_buff *skb; 158 unsigned int bytecount; 159 unsigned short gso_segs; 160 __be16 protocol; 161 DEFINE_DMA_UNMAP_ADDR(dma); 162 DEFINE_DMA_UNMAP_LEN(len); 163 u32 tx_flags; 164 }; 165 166 struct ixgbe_rx_buffer { 167 struct sk_buff *skb; 168 dma_addr_t dma; 169 struct page *page; 170 unsigned int page_offset; 171 }; 172 173 struct ixgbe_queue_stats { 174 u64 packets; 175 u64 bytes; 176 }; 177 178 struct ixgbe_tx_queue_stats { 179 u64 restart_queue; 180 u64 tx_busy; 181 u64 tx_done_old; 182 }; 183 184 struct ixgbe_rx_queue_stats { 185 u64 rsc_count; 186 u64 rsc_flush; 187 u64 non_eop_descs; 188 u64 alloc_rx_page_failed; 189 u64 alloc_rx_buff_failed; 190 u64 csum_err; 191 }; 192 193 enum ixgbe_ring_state_t { 194 __IXGBE_TX_FDIR_INIT_DONE, 195 __IXGBE_TX_DETECT_HANG, 196 __IXGBE_HANG_CHECK_ARMED, 197 __IXGBE_RX_RSC_ENABLED, 198 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 199 __IXGBE_RX_FCOE, 200 }; 201 202 #define check_for_tx_hang(ring) \ 203 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 204 #define set_check_for_tx_hang(ring) \ 205 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 206 #define clear_check_for_tx_hang(ring) \ 207 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 208 #define ring_is_rsc_enabled(ring) \ 209 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 210 #define set_ring_rsc_enabled(ring) \ 211 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 212 #define clear_ring_rsc_enabled(ring) \ 213 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 214 struct ixgbe_ring { 215 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 216 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 217 struct net_device *netdev; /* netdev ring belongs to */ 218 struct device *dev; /* device for DMA mapping */ 219 void *desc; /* descriptor ring memory */ 220 union { 221 struct ixgbe_tx_buffer *tx_buffer_info; 222 struct ixgbe_rx_buffer *rx_buffer_info; 223 }; 224 unsigned long state; 225 u8 __iomem *tail; 226 dma_addr_t dma; /* phys. address of descriptor ring */ 227 unsigned int size; /* length in bytes */ 228 229 u16 count; /* amount of descriptors */ 230 231 u8 queue_index; /* needed for multiqueue queue management */ 232 u8 reg_idx; /* holds the special value that gets 233 * the hardware register offset 234 * associated with this ring, which is 235 * different for DCB and RSS modes 236 */ 237 u16 next_to_use; 238 u16 next_to_clean; 239 240 union { 241 u16 next_to_alloc; 242 struct { 243 u8 atr_sample_rate; 244 u8 atr_count; 245 }; 246 }; 247 248 u8 dcb_tc; 249 struct ixgbe_queue_stats stats; 250 struct u64_stats_sync syncp; 251 union { 252 struct ixgbe_tx_queue_stats tx_stats; 253 struct ixgbe_rx_queue_stats rx_stats; 254 }; 255 } ____cacheline_internodealigned_in_smp; 256 257 enum ixgbe_ring_f_enum { 258 RING_F_NONE = 0, 259 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 260 RING_F_RSS, 261 RING_F_FDIR, 262 #ifdef IXGBE_FCOE 263 RING_F_FCOE, 264 #endif /* IXGBE_FCOE */ 265 266 RING_F_ARRAY_SIZE /* must be last in enum set */ 267 }; 268 269 #define IXGBE_MAX_RSS_INDICES 16 270 #define IXGBE_MAX_VMDQ_INDICES 64 271 #define IXGBE_MAX_FDIR_INDICES 64 272 #ifdef IXGBE_FCOE 273 #define IXGBE_MAX_FCOE_INDICES 8 274 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) 275 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) 276 #else 277 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES 278 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES 279 #endif /* IXGBE_FCOE */ 280 struct ixgbe_ring_feature { 281 u16 limit; /* upper limit on feature indices */ 282 u16 indices; /* current value of indices */ 283 u16 mask; /* Mask used for feature to ring mapping */ 284 u16 offset; /* offset to start of feature */ 285 } ____cacheline_internodealigned_in_smp; 286 287 /* 288 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 289 * this is twice the size of a half page we need to double the page order 290 * for FCoE enabled Rx queues. 291 */ 292 #if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192) 293 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 294 { 295 return test_bit(__IXGBE_RX_FCOE, &ring->state) ? 1 : 0; 296 } 297 #else 298 #define ixgbe_rx_pg_order(_ring) 0 299 #endif 300 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 301 #define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring)) 302 303 struct ixgbe_ring_container { 304 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 305 unsigned int total_bytes; /* total bytes processed this int */ 306 unsigned int total_packets; /* total packets processed this int */ 307 u16 work_limit; /* total work allowed per interrupt */ 308 u8 count; /* total number of rings in vector */ 309 u8 itr; /* current ITR setting for ring */ 310 }; 311 312 /* iterator for handling rings in ring container */ 313 #define ixgbe_for_each_ring(pos, head) \ 314 for (pos = (head).ring; pos != NULL; pos = pos->next) 315 316 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 317 ? 8 : 1) 318 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 319 320 /* MAX_Q_VECTORS of these are allocated, 321 * but we only use one per queue-specific vector. 322 */ 323 struct ixgbe_q_vector { 324 struct ixgbe_adapter *adapter; 325 #ifdef CONFIG_IXGBE_DCA 326 int cpu; /* CPU for DCA */ 327 #endif 328 u16 v_idx; /* index of q_vector within array, also used for 329 * finding the bit in EICR and friends that 330 * represents the vector for this ring */ 331 u16 itr; /* Interrupt throttle rate written to EITR */ 332 struct ixgbe_ring_container rx, tx; 333 334 struct napi_struct napi; 335 cpumask_t affinity_mask; 336 int numa_node; 337 struct rcu_head rcu; /* to avoid race with update stats on free */ 338 char name[IFNAMSIZ + 9]; 339 340 /* for dynamic allocation of rings associated with this q_vector */ 341 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; 342 }; 343 #ifdef CONFIG_IXGBE_HWMON 344 345 #define IXGBE_HWMON_TYPE_LOC 0 346 #define IXGBE_HWMON_TYPE_TEMP 1 347 #define IXGBE_HWMON_TYPE_CAUTION 2 348 #define IXGBE_HWMON_TYPE_MAX 3 349 350 struct hwmon_attr { 351 struct device_attribute dev_attr; 352 struct ixgbe_hw *hw; 353 struct ixgbe_thermal_diode_data *sensor; 354 char name[12]; 355 }; 356 357 struct hwmon_buff { 358 struct device *device; 359 struct hwmon_attr *hwmon_list; 360 unsigned int n_hwmon; 361 }; 362 #endif /* CONFIG_IXGBE_HWMON */ 363 364 /* 365 * microsecond values for various ITR rates shifted by 2 to fit itr register 366 * with the first 3 bits reserved 0 367 */ 368 #define IXGBE_MIN_RSC_ITR 24 369 #define IXGBE_100K_ITR 40 370 #define IXGBE_20K_ITR 200 371 #define IXGBE_10K_ITR 400 372 #define IXGBE_8K_ITR 500 373 374 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 375 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 376 const u32 stat_err_bits) 377 { 378 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 379 } 380 381 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 382 { 383 u16 ntc = ring->next_to_clean; 384 u16 ntu = ring->next_to_use; 385 386 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 387 } 388 389 #define IXGBE_RX_DESC(R, i) \ 390 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 391 #define IXGBE_TX_DESC(R, i) \ 392 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 393 #define IXGBE_TX_CTXTDESC(R, i) \ 394 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 395 396 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128 397 #ifdef IXGBE_FCOE 398 /* Use 3K as the baby jumbo frame size for FCoE */ 399 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 400 #endif /* IXGBE_FCOE */ 401 402 #define OTHER_VECTOR 1 403 #define NON_Q_VECTORS (OTHER_VECTOR) 404 405 #define MAX_MSIX_VECTORS_82599 64 406 #define MAX_Q_VECTORS_82599 64 407 #define MAX_MSIX_VECTORS_82598 18 408 #define MAX_Q_VECTORS_82598 16 409 410 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 411 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 412 413 #define MIN_MSIX_Q_VECTORS 1 414 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 415 416 /* default to trying for four seconds */ 417 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 418 419 /* board specific private data structure */ 420 struct ixgbe_adapter { 421 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 422 /* OS defined structs */ 423 struct net_device *netdev; 424 struct pci_dev *pdev; 425 426 unsigned long state; 427 428 /* Some features need tri-state capability, 429 * thus the additional *_CAPABLE flags. 430 */ 431 u32 flags; 432 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1) 433 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2) 434 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3) 435 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4) 436 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6) 437 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7) 438 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8) 439 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9) 440 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10) 441 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11) 442 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12) 443 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13) 444 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14) 445 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16) 446 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17) 447 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18) 448 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19) 449 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20) 450 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22) 451 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23) 452 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24) 453 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25) 454 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26) 455 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27) 456 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28) 457 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29) 458 459 u32 flags2; 460 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1) 461 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 462 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 463 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) 464 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) 465 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) 466 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) 467 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) 468 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8) 469 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9) 470 #define IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED (u32)(1 << 10) 471 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 11) 472 473 /* Tx fast path data */ 474 int num_tx_queues; 475 u16 tx_itr_setting; 476 u16 tx_work_limit; 477 478 /* Rx fast path data */ 479 int num_rx_queues; 480 u16 rx_itr_setting; 481 482 /* TX */ 483 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 484 485 u64 restart_queue; 486 u64 lsc_int; 487 u32 tx_timeout_count; 488 489 /* RX */ 490 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 491 int num_rx_pools; /* == num_rx_queues in 82598 */ 492 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 493 u64 hw_csum_rx_error; 494 u64 hw_rx_no_dma_resources; 495 u64 rsc_total_count; 496 u64 rsc_total_flush; 497 u64 non_eop_descs; 498 u32 alloc_rx_page_failed; 499 u32 alloc_rx_buff_failed; 500 501 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 502 503 /* DCB parameters */ 504 struct ieee_pfc *ixgbe_ieee_pfc; 505 struct ieee_ets *ixgbe_ieee_ets; 506 struct ixgbe_dcb_config dcb_cfg; 507 struct ixgbe_dcb_config temp_dcb_cfg; 508 u8 dcb_set_bitmap; 509 u8 dcbx_cap; 510 enum ixgbe_fc_mode last_lfc_mode; 511 512 int num_q_vectors; /* current number of q_vectors for device */ 513 int max_q_vectors; /* true count of q_vectors for device */ 514 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 515 struct msix_entry *msix_entries; 516 517 u32 test_icr; 518 struct ixgbe_ring test_tx_ring; 519 struct ixgbe_ring test_rx_ring; 520 521 /* structs defined in ixgbe_hw.h */ 522 struct ixgbe_hw hw; 523 u16 msg_enable; 524 struct ixgbe_hw_stats stats; 525 526 u64 tx_busy; 527 unsigned int tx_ring_count; 528 unsigned int rx_ring_count; 529 530 u32 link_speed; 531 bool link_up; 532 unsigned long link_check_timeout; 533 534 struct timer_list service_timer; 535 struct work_struct service_task; 536 537 struct hlist_head fdir_filter_list; 538 unsigned long fdir_overflow; /* number of times ATR was backed off */ 539 union ixgbe_atr_input fdir_mask; 540 int fdir_filter_count; 541 u32 fdir_pballoc; 542 u32 atr_sample_rate; 543 spinlock_t fdir_perfect_lock; 544 545 #ifdef IXGBE_FCOE 546 struct ixgbe_fcoe fcoe; 547 #endif /* IXGBE_FCOE */ 548 u32 wol; 549 550 u16 bd_number; 551 552 u16 eeprom_verh; 553 u16 eeprom_verl; 554 u16 eeprom_cap; 555 556 u32 interrupt_event; 557 u32 led_reg; 558 559 #ifdef CONFIG_IXGBE_PTP 560 struct ptp_clock *ptp_clock; 561 struct ptp_clock_info ptp_caps; 562 unsigned long last_overflow_check; 563 spinlock_t tmreg_lock; 564 struct cyclecounter cc; 565 struct timecounter tc; 566 int rx_hwtstamp_filter; 567 u32 base_incval; 568 u32 cycle_speed; 569 #endif /* CONFIG_IXGBE_PTP */ 570 571 /* SR-IOV */ 572 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 573 unsigned int num_vfs; 574 struct vf_data_storage *vfinfo; 575 int vf_rate_link_speed; 576 struct vf_macvlans vf_mvs; 577 struct vf_macvlans *mv_list; 578 579 u32 timer_event_accumulator; 580 u32 vferr_refcount; 581 struct kobject *info_kobj; 582 #ifdef CONFIG_IXGBE_HWMON 583 struct hwmon_buff ixgbe_hwmon_buff; 584 #endif /* CONFIG_IXGBE_HWMON */ 585 }; 586 587 struct ixgbe_fdir_filter { 588 struct hlist_node fdir_node; 589 union ixgbe_atr_input filter; 590 u16 sw_idx; 591 u16 action; 592 }; 593 594 enum ixgbe_state_t { 595 __IXGBE_TESTING, 596 __IXGBE_RESETTING, 597 __IXGBE_DOWN, 598 __IXGBE_SERVICE_SCHED, 599 __IXGBE_IN_SFP_INIT, 600 }; 601 602 struct ixgbe_cb { 603 union { /* Union defining head/tail partner */ 604 struct sk_buff *head; 605 struct sk_buff *tail; 606 }; 607 dma_addr_t dma; 608 u16 append_cnt; 609 bool page_released; 610 }; 611 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 612 613 enum ixgbe_boards { 614 board_82598, 615 board_82599, 616 board_X540, 617 }; 618 619 extern struct ixgbe_info ixgbe_82598_info; 620 extern struct ixgbe_info ixgbe_82599_info; 621 extern struct ixgbe_info ixgbe_X540_info; 622 #ifdef CONFIG_IXGBE_DCB 623 extern const struct dcbnl_rtnl_ops dcbnl_ops; 624 #endif 625 626 extern char ixgbe_driver_name[]; 627 extern const char ixgbe_driver_version[]; 628 #ifdef IXGBE_FCOE 629 extern char ixgbe_default_device_descr[]; 630 #endif /* IXGBE_FCOE */ 631 632 extern void ixgbe_up(struct ixgbe_adapter *adapter); 633 extern void ixgbe_down(struct ixgbe_adapter *adapter); 634 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 635 extern void ixgbe_reset(struct ixgbe_adapter *adapter); 636 extern void ixgbe_set_ethtool_ops(struct net_device *netdev); 637 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *); 638 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *); 639 extern void ixgbe_free_rx_resources(struct ixgbe_ring *); 640 extern void ixgbe_free_tx_resources(struct ixgbe_ring *); 641 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); 642 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); 643 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 644 struct ixgbe_ring *); 645 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); 646 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 647 extern int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 648 u16 subdevice_id); 649 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 650 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, 651 struct ixgbe_adapter *, 652 struct ixgbe_ring *); 653 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 654 struct ixgbe_tx_buffer *); 655 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 656 extern void ixgbe_write_eitr(struct ixgbe_q_vector *); 657 extern int ixgbe_poll(struct napi_struct *napi, int budget); 658 extern int ethtool_ioctl(struct ifreq *ifr); 659 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 660 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 661 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 662 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 663 union ixgbe_atr_hash_dword input, 664 union ixgbe_atr_hash_dword common, 665 u8 queue); 666 extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 667 union ixgbe_atr_input *input_mask); 668 extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 669 union ixgbe_atr_input *input, 670 u16 soft_id, u8 queue); 671 extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 672 union ixgbe_atr_input *input, 673 u16 soft_id); 674 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 675 union ixgbe_atr_input *mask); 676 extern void ixgbe_set_rx_mode(struct net_device *netdev); 677 #ifdef CONFIG_IXGBE_DCB 678 extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 679 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc); 680 #endif 681 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 682 extern void ixgbe_do_reset(struct net_device *netdev); 683 #ifdef CONFIG_IXGBE_HWMON 684 extern void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 685 extern int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 686 #endif /* CONFIG_IXGBE_HWMON */ 687 #ifdef IXGBE_FCOE 688 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 689 extern int ixgbe_fso(struct ixgbe_ring *tx_ring, 690 struct ixgbe_tx_buffer *first, 691 u8 *hdr_len); 692 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter); 693 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 694 union ixgbe_adv_rx_desc *rx_desc, 695 struct sk_buff *skb); 696 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 697 struct scatterlist *sgl, unsigned int sgc); 698 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 699 struct scatterlist *sgl, unsigned int sgc); 700 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 701 extern int ixgbe_fcoe_enable(struct net_device *netdev); 702 extern int ixgbe_fcoe_disable(struct net_device *netdev); 703 #ifdef CONFIG_IXGBE_DCB 704 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 705 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 706 #endif /* CONFIG_IXGBE_DCB */ 707 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 708 extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 709 struct netdev_fcoe_hbainfo *info); 710 extern u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 711 #endif /* IXGBE_FCOE */ 712 713 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 714 { 715 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 716 } 717 718 #ifdef CONFIG_IXGBE_PTP 719 extern void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 720 extern void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 721 extern void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 722 extern void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector, 723 struct sk_buff *skb); 724 extern void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector, 725 union ixgbe_adv_rx_desc *rx_desc, 726 struct sk_buff *skb); 727 extern int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, 728 struct ifreq *ifr, int cmd); 729 extern void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 730 extern void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr); 731 #endif /* CONFIG_IXGBE_PTP */ 732 733 #endif /* _IXGBE_H_ */ 734