ccs-pll.c (f25d3962ac8f23ab4871cef1d79e10a8c34f7908) ccs-pll.c (594f1e93bb2c48bcc14a020448b46eed15be7ef7)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * drivers/media/i2c/ccs-pll.c
4 *
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
6 *
7 * Copyright (C) 2020 Intel Corporation
8 * Copyright (C) 2011--2012 Nokia Corporation

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234
235static void
236ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
237 const struct ccs_pll_branch_limits_bk *op_lim_bk,
238 struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
239 struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
240 uint32_t phy_const)
241{
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * drivers/media/i2c/ccs-pll.c
4 *
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
6 *
7 * Copyright (C) 2020 Intel Corporation
8 * Copyright (C) 2011--2012 Nokia Corporation

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234
235static void
236ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
237 const struct ccs_pll_branch_limits_bk *op_lim_bk,
238 struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
239 struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
240 uint32_t phy_const)
241{
242 uint32_t sys_div;
243 uint32_t best_pix_div = INT_MAX >> 1;
244 uint32_t vt_op_binning_div;
245 uint32_t min_vt_div, max_vt_div, vt_div;
246 uint32_t min_sys_div, max_sys_div;
242 uint16_t sys_div;
243 uint16_t best_pix_div = SHRT_MAX >> 1;
244 uint16_t vt_op_binning_div;
245 uint16_t min_vt_div, max_vt_div, vt_div;
246 uint16_t min_sys_div, max_sys_div;
247
248 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
249 goto out_calc_pixel_rate;
250
251 /*
252 * Find out whether a sensor supports derating. If it does not, VT and
253 * OP domains are required to run at the same pixel rate.
254 */

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292 CCS_PLL_FLAG_LANE_SPEED_MODEL ?
293 pll->csi2.lanes : 1)
294 * vt_op_binning_div * pll->scale_m
295 * PHY_CONST_DIV);
296 }
297
298 /* Find smallest and biggest allowed vt divisor. */
299 dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
247
248 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
249 goto out_calc_pixel_rate;
250
251 /*
252 * Find out whether a sensor supports derating. If it does not, VT and
253 * OP domains are required to run at the same pixel rate.
254 */

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292 CCS_PLL_FLAG_LANE_SPEED_MODEL ?
293 pll->csi2.lanes : 1)
294 * vt_op_binning_div * pll->scale_m
295 * PHY_CONST_DIV);
296 }
297
298 /* Find smallest and biggest allowed vt divisor. */
299 dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
300 min_vt_div = max(min_vt_div,
301 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
302 lim->vt_bk.max_pix_clk_freq_hz));
300 min_vt_div = max_t(uint16_t, min_vt_div,
301 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
302 lim->vt_bk.max_pix_clk_freq_hz));
303 dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
304 min_vt_div);
303 dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
304 min_vt_div);
305 min_vt_div = max_t(uint32_t, min_vt_div,
306 lim->vt_bk.min_pix_clk_div
307 * lim->vt_bk.min_sys_clk_div);
305 min_vt_div = max_t(uint16_t, min_vt_div, lim->vt_bk.min_pix_clk_div
306 * lim->vt_bk.min_sys_clk_div);
308 dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
309
310 max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
311 dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
307 dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
308
309 max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
310 dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
312 max_vt_div = min(max_vt_div,
313 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
311 max_vt_div = min_t(uint16_t, max_vt_div,
312 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
314 lim->vt_bk.min_pix_clk_freq_hz));
315 dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
316 max_vt_div);
317
318 /*
319 * Find limitsits for sys_clk_div. Not all values are possible
320 * with all values of pix_clk_div.
321 */
322 min_sys_div = lim->vt_bk.min_sys_clk_div;
323 dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
313 lim->vt_bk.min_pix_clk_freq_hz));
314 dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
315 max_vt_div);
316
317 /*
318 * Find limitsits for sys_clk_div. Not all values are possible
319 * with all values of pix_clk_div.
320 */
321 min_sys_div = lim->vt_bk.min_sys_clk_div;
322 dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
324 min_sys_div = max(min_sys_div,
325 DIV_ROUND_UP(min_vt_div,
326 lim->vt_bk.max_pix_clk_div));
323 min_sys_div = max_t(uint16_t, min_sys_div,
324 DIV_ROUND_UP(min_vt_div,
325 lim->vt_bk.max_pix_clk_div));
327 dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
326 dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
328 min_sys_div = max(min_sys_div,
329 pll_fr->pll_op_clk_freq_hz
330 / lim->vt_bk.max_sys_clk_freq_hz);
327 min_sys_div = max_t(uint16_t, min_sys_div,
328 pll_fr->pll_op_clk_freq_hz
329 / lim->vt_bk.max_sys_clk_freq_hz);
331 dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
332 min_sys_div = clk_div_even_up(min_sys_div);
333 dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
334
335 max_sys_div = lim->vt_bk.max_sys_clk_div;
336 dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
330 dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
331 min_sys_div = clk_div_even_up(min_sys_div);
332 dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
333
334 max_sys_div = lim->vt_bk.max_sys_clk_div;
335 dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
337 max_sys_div = min(max_sys_div,
338 DIV_ROUND_UP(max_vt_div,
339 lim->vt_bk.min_pix_clk_div));
336 max_sys_div = min_t(uint16_t, max_sys_div,
337 DIV_ROUND_UP(max_vt_div,
338 lim->vt_bk.min_pix_clk_div));
340 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
339 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
341 max_sys_div = min(max_sys_div,
342 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
343 lim->vt_bk.min_pix_clk_freq_hz));
340 max_sys_div = min_t(uint16_t, max_sys_div,
341 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
342 lim->vt_bk.min_pix_clk_freq_hz));
344 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
345
346 /*
347 * Find pix_div such that a legal pix_div * sys_div results
348 * into a value which is not smaller than div, the desired
349 * divisor.
350 */
351 for (vt_div = min_vt_div; vt_div <= max_vt_div;

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371 /* Check if this one is better. */
372 if (pix_div * sys_div <= rounded_div)
373 best_pix_div = pix_div;
374
375 /* Bail out if we've already found the best value. */
376 if (vt_div == rounded_div)
377 break;
378 }
343 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
344
345 /*
346 * Find pix_div such that a legal pix_div * sys_div results
347 * into a value which is not smaller than div, the desired
348 * divisor.
349 */
350 for (vt_div = min_vt_div; vt_div <= max_vt_div;

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370 /* Check if this one is better. */
371 if (pix_div * sys_div <= rounded_div)
372 best_pix_div = pix_div;
373
374 /* Bail out if we've already found the best value. */
375 if (vt_div == rounded_div)
376 break;
377 }
379 if (best_pix_div < INT_MAX >> 1)
378 if (best_pix_div < SHRT_MAX >> 1)
380 break;
381 }
382
383 pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
384 pll->vt_bk.pix_clk_div = best_pix_div;
385
386 pll->vt_bk.sys_clk_freq_hz =
387 pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;

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380 }
381
382 pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
383 pll->vt_bk.pix_clk_div = best_pix_div;
384
385 pll->vt_bk.sys_clk_freq_hz =
386 pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;

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