1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/media/i2c/ccs-pll.c 4 * 5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator 6 * 7 * Copyright (C) 2020 Intel Corporation 8 * Copyright (C) 2011--2012 Nokia Corporation 9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com> 10 */ 11 12 #include <linux/device.h> 13 #include <linux/gcd.h> 14 #include <linux/lcm.h> 15 #include <linux/module.h> 16 17 #include "ccs-pll.h" 18 19 /* Return an even number or one. */ 20 static inline uint32_t clk_div_even(uint32_t a) 21 { 22 return max_t(uint32_t, 1, a & ~1); 23 } 24 25 /* Return an even number or one. */ 26 static inline uint32_t clk_div_even_up(uint32_t a) 27 { 28 if (a == 1) 29 return 1; 30 return (a + 1) & ~1; 31 } 32 33 static inline uint32_t is_one_or_even(uint32_t a) 34 { 35 if (a == 1) 36 return 1; 37 if (a & 1) 38 return 0; 39 40 return 1; 41 } 42 43 static inline uint32_t one_or_more(uint32_t a) 44 { 45 return a ?: 1; 46 } 47 48 static int bounds_check(struct device *dev, uint32_t val, 49 uint32_t min, uint32_t max, const char *prefix, 50 char *str) 51 { 52 if (val >= min && val <= max) 53 return 0; 54 55 dev_dbg(dev, "%s_%s out of bounds: %d (%d--%d)\n", prefix, 56 str, val, min, max); 57 58 return -EINVAL; 59 } 60 61 #define PLL_OP 1 62 #define PLL_VT 2 63 64 static const char *pll_string(unsigned int which) 65 { 66 switch (which) { 67 case PLL_OP: 68 return "op"; 69 case PLL_VT: 70 return "vt"; 71 } 72 73 return NULL; 74 } 75 76 #define PLL_FL(f) CCS_PLL_FLAG_##f 77 78 static void print_pll(struct device *dev, struct ccs_pll *pll) 79 { 80 const struct { 81 struct ccs_pll_branch_fr *fr; 82 struct ccs_pll_branch_bk *bk; 83 unsigned int which; 84 } branches[] = { 85 { &pll->vt_fr, &pll->vt_bk, PLL_VT }, 86 { &pll->op_fr, &pll->op_bk, PLL_OP } 87 }, *br; 88 unsigned int i; 89 90 dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz); 91 92 for (i = 0, br = branches; i < ARRAY_SIZE(branches); i++, br++) { 93 const char *s = pll_string(br->which); 94 95 if (br->which == PLL_VT) { 96 dev_dbg(dev, "%s_pre_pll_clk_div\t\t%u\n", s, 97 br->fr->pre_pll_clk_div); 98 dev_dbg(dev, "%s_pll_multiplier\t\t%u\n", s, 99 br->fr->pll_multiplier); 100 101 dev_dbg(dev, "%s_pll_ip_clk_freq_hz\t%u\n", s, 102 br->fr->pll_ip_clk_freq_hz); 103 dev_dbg(dev, "%s_pll_op_clk_freq_hz\t%u\n", s, 104 br->fr->pll_op_clk_freq_hz); 105 } 106 107 if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) || 108 br->which == PLL_VT) { 109 dev_dbg(dev, "%s_sys_clk_div\t\t%u\n", s, 110 br->bk->sys_clk_div); 111 dev_dbg(dev, "%s_pix_clk_div\t\t%u\n", s, 112 br->bk->pix_clk_div); 113 114 dev_dbg(dev, "%s_sys_clk_freq_hz\t%u\n", s, 115 br->bk->sys_clk_freq_hz); 116 dev_dbg(dev, "%s_pix_clk_freq_hz\t%u\n", s, 117 br->bk->pix_clk_freq_hz); 118 } 119 } 120 121 dev_dbg(dev, "flags%s%s%s%s%s%s\n", 122 pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "", 123 pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "", 124 pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ? 125 " ext-ip-pll-divider" : "", 126 pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ? 127 " flexible-op-pix-div" : "", 128 pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "", 129 pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : ""); 130 } 131 132 static int check_fr_bounds(struct device *dev, 133 const struct ccs_pll_limits *lim, 134 struct ccs_pll *pll, unsigned int which) 135 { 136 const struct ccs_pll_branch_limits_fr *lim_fr; 137 struct ccs_pll_branch_fr *pll_fr; 138 const char *s = pll_string(which); 139 int rval; 140 141 if (which == PLL_OP) { 142 lim_fr = &lim->op_fr; 143 pll_fr = &pll->op_fr; 144 } else { 145 lim_fr = &lim->vt_fr; 146 pll_fr = &pll->vt_fr; 147 } 148 149 rval = bounds_check(dev, pll_fr->pre_pll_clk_div, 150 lim_fr->min_pre_pll_clk_div, 151 lim_fr->max_pre_pll_clk_div, s, "pre_pll_clk_div"); 152 153 if (!rval) 154 rval = bounds_check(dev, pll_fr->pll_ip_clk_freq_hz, 155 lim_fr->min_pll_ip_clk_freq_hz, 156 lim_fr->max_pll_ip_clk_freq_hz, 157 s, "pll_ip_clk_freq_hz"); 158 if (!rval) 159 rval = bounds_check(dev, pll_fr->pll_multiplier, 160 lim_fr->min_pll_multiplier, 161 lim_fr->max_pll_multiplier, 162 s, "pll_multiplier"); 163 if (!rval) 164 rval = bounds_check(dev, pll_fr->pll_op_clk_freq_hz, 165 lim_fr->min_pll_op_clk_freq_hz, 166 lim_fr->max_pll_op_clk_freq_hz, 167 s, "pll_op_clk_freq_hz"); 168 169 return rval; 170 } 171 172 static int check_bk_bounds(struct device *dev, 173 const struct ccs_pll_limits *lim, 174 struct ccs_pll *pll, unsigned int which) 175 { 176 const struct ccs_pll_branch_limits_bk *lim_bk; 177 struct ccs_pll_branch_bk *pll_bk; 178 const char *s = pll_string(which); 179 int rval; 180 181 if (which == PLL_OP) { 182 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) 183 return 0; 184 185 lim_bk = &lim->op_bk; 186 pll_bk = &pll->op_bk; 187 } else { 188 lim_bk = &lim->vt_bk; 189 pll_bk = &pll->vt_bk; 190 } 191 192 rval = bounds_check(dev, pll_bk->sys_clk_div, 193 lim_bk->min_sys_clk_div, 194 lim_bk->max_sys_clk_div, s, "op_sys_clk_div"); 195 if (!rval) 196 rval = bounds_check(dev, pll_bk->sys_clk_freq_hz, 197 lim_bk->min_sys_clk_freq_hz, 198 lim_bk->max_sys_clk_freq_hz, 199 s, "sys_clk_freq_hz"); 200 if (!rval) 201 rval = bounds_check(dev, pll_bk->sys_clk_div, 202 lim_bk->min_sys_clk_div, 203 lim_bk->max_sys_clk_div, 204 s, "sys_clk_div"); 205 if (!rval) 206 rval = bounds_check(dev, pll_bk->pix_clk_freq_hz, 207 lim_bk->min_pix_clk_freq_hz, 208 lim_bk->max_pix_clk_freq_hz, 209 s, "pix_clk_freq_hz"); 210 211 return rval; 212 } 213 214 static int check_ext_bounds(struct device *dev, struct ccs_pll *pll) 215 { 216 if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) && 217 pll->pixel_rate_pixel_array > pll->pixel_rate_csi) { 218 dev_dbg(dev, "device does not support derating\n"); 219 return -EINVAL; 220 } 221 222 if (!(pll->flags & CCS_PLL_FLAG_FIFO_OVERRATING) && 223 pll->pixel_rate_pixel_array < pll->pixel_rate_csi) { 224 dev_dbg(dev, "device does not support overrating\n"); 225 return -EINVAL; 226 } 227 228 return 0; 229 } 230 231 #define CPHY_CONST 7 232 #define DPHY_CONST 16 233 #define PHY_CONST_DIV 16 234 235 static void 236 ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, 237 const struct ccs_pll_branch_limits_bk *op_lim_bk, 238 struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr, 239 struct ccs_pll_branch_bk *op_pll_bk, bool cphy, 240 uint32_t phy_const) 241 { 242 uint16_t sys_div; 243 uint16_t best_pix_div = SHRT_MAX >> 1; 244 uint16_t vt_op_binning_div; 245 uint16_t min_vt_div, max_vt_div, vt_div; 246 uint16_t min_sys_div, max_sys_div; 247 248 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) 249 goto out_calc_pixel_rate; 250 251 /* 252 * Find out whether a sensor supports derating. If it does not, VT and 253 * OP domains are required to run at the same pixel rate. 254 */ 255 if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) { 256 min_vt_div = 257 op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div 258 * pll->vt_lanes * phy_const 259 / pll->op_lanes / PHY_CONST_DIV; 260 } else { 261 /* 262 * Some sensors perform analogue binning and some do this 263 * digitally. The ones doing this digitally can be roughly be 264 * found out using this formula. The ones doing this digitally 265 * should run at higher clock rate, so smaller divisor is used 266 * on video timing side. 267 */ 268 if (lim->min_line_length_pck_bin > lim->min_line_length_pck 269 / pll->binning_horizontal) 270 vt_op_binning_div = pll->binning_horizontal; 271 else 272 vt_op_binning_div = 1; 273 dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div); 274 275 /* 276 * Profile 2 supports vt_pix_clk_div E [4, 10] 277 * 278 * Horizontal binning can be used as a base for difference in 279 * divisors. One must make sure that horizontal blanking is 280 * enough to accommodate the CSI-2 sync codes. 281 * 282 * Take scaling factor and number of VT lanes into account as well. 283 * 284 * Find absolute limits for the factor of vt divider. 285 */ 286 dev_dbg(dev, "scale_m: %u\n", pll->scale_m); 287 min_vt_div = 288 DIV_ROUND_UP(pll->bits_per_pixel 289 * op_pll_bk->sys_clk_div * pll->scale_n 290 * pll->vt_lanes * phy_const, 291 (pll->flags & 292 CCS_PLL_FLAG_LANE_SPEED_MODEL ? 293 pll->csi2.lanes : 1) 294 * vt_op_binning_div * pll->scale_m 295 * PHY_CONST_DIV); 296 } 297 298 /* Find smallest and biggest allowed vt divisor. */ 299 dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); 300 min_vt_div = max_t(uint16_t, min_vt_div, 301 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, 302 lim->vt_bk.max_pix_clk_freq_hz)); 303 dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n", 304 min_vt_div); 305 min_vt_div = max_t(uint16_t, min_vt_div, lim->vt_bk.min_pix_clk_div 306 * lim->vt_bk.min_sys_clk_div); 307 dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div); 308 309 max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div; 310 dev_dbg(dev, "max_vt_div: %u\n", max_vt_div); 311 max_vt_div = min_t(uint16_t, max_vt_div, 312 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, 313 lim->vt_bk.min_pix_clk_freq_hz)); 314 dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", 315 max_vt_div); 316 317 /* 318 * Find limitsits for sys_clk_div. Not all values are possible 319 * with all values of pix_clk_div. 320 */ 321 min_sys_div = lim->vt_bk.min_sys_clk_div; 322 dev_dbg(dev, "min_sys_div: %u\n", min_sys_div); 323 min_sys_div = max_t(uint16_t, min_sys_div, 324 DIV_ROUND_UP(min_vt_div, 325 lim->vt_bk.max_pix_clk_div)); 326 dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div); 327 min_sys_div = max_t(uint16_t, min_sys_div, 328 pll_fr->pll_op_clk_freq_hz 329 / lim->vt_bk.max_sys_clk_freq_hz); 330 dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div); 331 min_sys_div = clk_div_even_up(min_sys_div); 332 dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div); 333 334 max_sys_div = lim->vt_bk.max_sys_clk_div; 335 dev_dbg(dev, "max_sys_div: %u\n", max_sys_div); 336 max_sys_div = min_t(uint16_t, max_sys_div, 337 DIV_ROUND_UP(max_vt_div, 338 lim->vt_bk.min_pix_clk_div)); 339 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div); 340 max_sys_div = min_t(uint16_t, max_sys_div, 341 DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, 342 lim->vt_bk.min_pix_clk_freq_hz)); 343 dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div); 344 345 /* 346 * Find pix_div such that a legal pix_div * sys_div results 347 * into a value which is not smaller than div, the desired 348 * divisor. 349 */ 350 for (vt_div = min_vt_div; vt_div <= max_vt_div; 351 vt_div += 2 - (vt_div & 1)) { 352 for (sys_div = min_sys_div; 353 sys_div <= max_sys_div; 354 sys_div += 2 - (sys_div & 1)) { 355 uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div); 356 uint16_t rounded_div; 357 358 if (pix_div < lim->vt_bk.min_pix_clk_div 359 || pix_div > lim->vt_bk.max_pix_clk_div) { 360 dev_dbg(dev, 361 "pix_div %u too small or too big (%u--%u)\n", 362 pix_div, 363 lim->vt_bk.min_pix_clk_div, 364 lim->vt_bk.max_pix_clk_div); 365 continue; 366 } 367 368 rounded_div = roundup(vt_div, best_pix_div); 369 370 /* Check if this one is better. */ 371 if (pix_div * sys_div <= rounded_div) 372 best_pix_div = pix_div; 373 374 /* Bail out if we've already found the best value. */ 375 if (vt_div == rounded_div) 376 break; 377 } 378 if (best_pix_div < SHRT_MAX >> 1) 379 break; 380 } 381 382 pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div); 383 pll->vt_bk.pix_clk_div = best_pix_div; 384 385 pll->vt_bk.sys_clk_freq_hz = 386 pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div; 387 pll->vt_bk.pix_clk_freq_hz = 388 pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div; 389 390 out_calc_pixel_rate: 391 pll->pixel_rate_pixel_array = 392 pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes; 393 } 394 395 /* 396 * Heuristically guess the PLL tree for a given common multiplier and 397 * divisor. Begin with the operational timing and continue to video 398 * timing once operational timing has been verified. 399 * 400 * @mul is the PLL multiplier and @div is the common divisor 401 * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL 402 * multiplier will be a multiple of @mul. 403 * 404 * @return Zero on success, error code on error. 405 */ 406 static int 407 ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim, 408 const struct ccs_pll_branch_limits_fr *op_lim_fr, 409 const struct ccs_pll_branch_limits_bk *op_lim_bk, 410 struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, 411 struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, 412 uint32_t div, uint32_t l, bool cphy, uint32_t phy_const) 413 { 414 /* 415 * Higher multipliers (and divisors) are often required than 416 * necessitated by the external clock and the output clocks. 417 * There are limits for all values in the clock tree. These 418 * are the minimum and maximum multiplier for mul. 419 */ 420 uint32_t more_mul_min, more_mul_max; 421 uint32_t more_mul_factor; 422 uint32_t i; 423 424 /* 425 * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be 426 * too high. 427 */ 428 dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div); 429 430 /* Don't go above max pll multiplier. */ 431 more_mul_max = op_lim_fr->max_pll_multiplier / mul; 432 dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n", 433 more_mul_max); 434 /* Don't go above max pll op frequency. */ 435 more_mul_max = 436 min_t(uint32_t, 437 more_mul_max, 438 op_lim_fr->max_pll_op_clk_freq_hz 439 / (pll->ext_clk_freq_hz / 440 op_pll_fr->pre_pll_clk_div * mul)); 441 dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n", 442 more_mul_max); 443 /* Don't go above the division capability of op sys clock divider. */ 444 more_mul_max = min(more_mul_max, 445 op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div 446 / div); 447 dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n", 448 more_mul_max); 449 /* Ensure we won't go above max_pll_multiplier. */ 450 more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul); 451 dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n", 452 more_mul_max); 453 454 /* Ensure we won't go below min_pll_op_clk_freq_hz. */ 455 more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz, 456 pll->ext_clk_freq_hz / 457 op_pll_fr->pre_pll_clk_div * mul); 458 dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n", 459 more_mul_min); 460 /* Ensure we won't go below min_pll_multiplier. */ 461 more_mul_min = max(more_mul_min, 462 DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul)); 463 dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n", 464 more_mul_min); 465 466 if (more_mul_min > more_mul_max) { 467 dev_dbg(dev, 468 "unable to compute more_mul_min and more_mul_max\n"); 469 return -EINVAL; 470 } 471 472 more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div; 473 dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor); 474 more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div); 475 dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n", 476 more_mul_factor); 477 i = roundup(more_mul_min, more_mul_factor); 478 if (!is_one_or_even(i)) 479 i <<= 1; 480 481 dev_dbg(dev, "final more_mul: %u\n", i); 482 if (i > more_mul_max) { 483 dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max); 484 return -EINVAL; 485 } 486 487 op_pll_fr->pll_multiplier = mul * i; 488 op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div; 489 dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div); 490 491 op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz 492 / op_pll_fr->pre_pll_clk_div; 493 494 op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz 495 * op_pll_fr->pll_multiplier; 496 497 if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL) 498 op_pll_bk->pix_clk_div = pll->bits_per_pixel 499 * pll->op_lanes * phy_const 500 / PHY_CONST_DIV / pll->csi2.lanes / l; 501 else 502 op_pll_bk->pix_clk_div = 503 pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l; 504 505 op_pll_bk->pix_clk_freq_hz = 506 op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; 507 508 dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div); 509 510 return 0; 511 } 512 513 int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, 514 struct ccs_pll *pll) 515 { 516 const struct ccs_pll_branch_limits_fr *op_lim_fr = &lim->vt_fr; 517 const struct ccs_pll_branch_limits_bk *op_lim_bk = &lim->op_bk; 518 struct ccs_pll_branch_fr *op_pll_fr = &pll->vt_fr; 519 struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk; 520 bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY; 521 uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST; 522 uint16_t min_op_pre_pll_clk_div; 523 uint16_t max_op_pre_pll_clk_div; 524 uint32_t mul, div; 525 uint32_t l = (!pll->op_bits_per_lane || 526 pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2; 527 uint32_t i; 528 int rval = -EINVAL; 529 530 if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) { 531 pll->op_lanes = 1; 532 pll->vt_lanes = 1; 533 } 534 535 if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel || 536 !pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m || 537 !op_lim_fr->min_pll_ip_clk_freq_hz || 538 !op_lim_fr->max_pll_ip_clk_freq_hz || 539 !op_lim_fr->min_pll_op_clk_freq_hz || 540 !op_lim_fr->max_pll_op_clk_freq_hz || 541 !op_lim_bk->max_sys_clk_div || !op_lim_fr->max_pll_multiplier) 542 return -EINVAL; 543 544 /* 545 * Make sure op_pix_clk_div will be integer --- unless flexible 546 * op_pix_clk_div is supported 547 */ 548 if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) && 549 (pll->bits_per_pixel * pll->op_lanes) % (pll->csi2.lanes * l)) { 550 dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n", 551 pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l); 552 return -EINVAL; 553 } 554 555 dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes); 556 dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes); 557 558 if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) { 559 /* 560 * If there's no OP PLL at all, use the VT values 561 * instead. The OP values are ignored for the rest of 562 * the PLL calculation. 563 */ 564 op_lim_fr = &lim->vt_fr; 565 op_lim_bk = &lim->vt_bk; 566 op_pll_bk = &pll->vt_bk; 567 } 568 569 dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal, 570 pll->binning_vertical); 571 572 switch (pll->bus_type) { 573 case CCS_PLL_BUS_TYPE_CSI2_DPHY: 574 /* CSI transfers 2 bits per clock per lane; thus times 2 */ 575 op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2 576 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 577 1 : pll->csi2.lanes); 578 break; 579 case CCS_PLL_BUS_TYPE_CSI2_CPHY: 580 op_pll_bk->sys_clk_freq_hz = 581 pll->link_freq 582 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 583 1 : pll->csi2.lanes); 584 break; 585 default: 586 return -EINVAL; 587 } 588 589 pll->pixel_rate_csi = 590 div_u64((uint64_t)op_pll_bk->sys_clk_freq_hz 591 * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 592 pll->csi2.lanes : 1) * PHY_CONST_DIV, 593 phy_const * pll->bits_per_pixel * l); 594 595 /* Figure out limits for OP pre-pll divider based on extclk */ 596 dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", 597 op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div); 598 max_op_pre_pll_clk_div = 599 min_t(uint16_t, op_lim_fr->max_pre_pll_clk_div, 600 clk_div_even(pll->ext_clk_freq_hz / 601 op_lim_fr->min_pll_ip_clk_freq_hz)); 602 min_op_pre_pll_clk_div = 603 max_t(uint16_t, op_lim_fr->min_pre_pll_clk_div, 604 clk_div_even_up( 605 DIV_ROUND_UP(pll->ext_clk_freq_hz, 606 op_lim_fr->max_pll_ip_clk_freq_hz))); 607 dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n", 608 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); 609 610 i = gcd(op_pll_bk->sys_clk_freq_hz, pll->ext_clk_freq_hz); 611 mul = op_pll_bk->sys_clk_freq_hz / i; 612 div = pll->ext_clk_freq_hz / i; 613 dev_dbg(dev, "mul %u / div %u\n", mul, div); 614 615 min_op_pre_pll_clk_div = 616 max_t(uint16_t, min_op_pre_pll_clk_div, 617 clk_div_even_up( 618 mul / 619 one_or_more( 620 DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz, 621 pll->ext_clk_freq_hz)))); 622 dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n", 623 min_op_pre_pll_clk_div, max_op_pre_pll_clk_div); 624 625 for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div; 626 op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div; 627 op_pll_fr->pre_pll_clk_div += 628 (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : 629 2 - (op_pll_fr->pre_pll_clk_div & 1)) { 630 rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll, 631 op_pll_fr, op_pll_bk, mul, div, l, 632 cphy, phy_const); 633 if (rval) 634 continue; 635 636 rval = check_fr_bounds(dev, lim, pll, PLL_VT); 637 if (rval) 638 continue; 639 640 rval = check_bk_bounds(dev, lim, pll, PLL_OP); 641 if (rval) 642 continue; 643 644 ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr, 645 op_pll_bk, cphy, phy_const); 646 647 rval = check_bk_bounds(dev, lim, pll, PLL_VT); 648 if (rval) 649 continue; 650 rval = check_ext_bounds(dev, pll); 651 if (rval) 652 continue; 653 654 print_pll(dev, pll); 655 656 return 0; 657 } 658 659 dev_dbg(dev, "unable to compute pre_pll divisor\n"); 660 661 return rval; 662 } 663 EXPORT_SYMBOL_GPL(ccs_pll_calculate); 664 665 MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>"); 666 MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator"); 667 MODULE_LICENSE("GPL v2"); 668