init.c (ccacd94fdacabe77f5a887c3b75334982b1ce9ca) init.c (1ab5a15334529d3980a85abb2e06498c8e5ac8cc)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#define pr_fmt(fmt) "AMD-Vi: " fmt

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233static int __initdata early_acpihid_map_size;
234
235static bool __initdata cmdline_maps;
236
237static enum iommu_init_state init_state = IOMMU_START_STATE;
238
239static int amd_iommu_enable_interrupts(void);
240static int __init iommu_go_to_state(enum iommu_init_state state);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#define pr_fmt(fmt) "AMD-Vi: " fmt

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233static int __initdata early_acpihid_map_size;
234
235static bool __initdata cmdline_maps;
236
237static enum iommu_init_state init_state = IOMMU_START_STATE;
238
239static int amd_iommu_enable_interrupts(void);
240static int __init iommu_go_to_state(enum iommu_init_state state);
241static void init_device_table_dma(void);
241static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg);
242
243static bool amd_iommu_pre_enabled = true;
244
245static u32 amd_iommu_ivinfo __initdata;
246
247bool translation_pre_enabled(struct amd_iommu *iommu)
248{
249 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);

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2114 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
2115 pr_info("X2APIC enabled\n");
2116 }
2117}
2118
2119static int __init amd_iommu_init_pci(void)
2120{
2121 struct amd_iommu *iommu;
242
243static bool amd_iommu_pre_enabled = true;
244
245static u32 amd_iommu_ivinfo __initdata;
246
247bool translation_pre_enabled(struct amd_iommu *iommu)
248{
249 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);

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2114 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
2115 pr_info("X2APIC enabled\n");
2116 }
2117}
2118
2119static int __init amd_iommu_init_pci(void)
2120{
2121 struct amd_iommu *iommu;
2122 struct amd_iommu_pci_seg *pci_seg;
2122 int ret;
2123
2124 for_each_iommu(iommu) {
2125 ret = iommu_init_pci(iommu);
2126 if (ret) {
2127 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n",
2128 iommu->index, ret);
2129 goto out;

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2144 */
2145 ret = amd_iommu_init_api();
2146 if (ret) {
2147 pr_err("IOMMU: Failed to initialize IOMMU-API interface (error=%d)!\n",
2148 ret);
2149 goto out;
2150 }
2151
2123 int ret;
2124
2125 for_each_iommu(iommu) {
2126 ret = iommu_init_pci(iommu);
2127 if (ret) {
2128 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n",
2129 iommu->index, ret);
2130 goto out;

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2145 */
2146 ret = amd_iommu_init_api();
2147 if (ret) {
2148 pr_err("IOMMU: Failed to initialize IOMMU-API interface (error=%d)!\n",
2149 ret);
2150 goto out;
2151 }
2152
2152 init_device_table_dma();
2153 for_each_pci_segment(pci_seg)
2154 init_device_table_dma(pci_seg);
2153
2154 for_each_iommu(iommu)
2155 iommu_flush_all_caches(iommu);
2156
2157 print_iommu_info();
2158
2159out:
2160 return ret;

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2506 }
2507
2508 return 0;
2509}
2510
2511/*
2512 * Init the device table to not allow DMA access for devices
2513 */
2155
2156 for_each_iommu(iommu)
2157 iommu_flush_all_caches(iommu);
2158
2159 print_iommu_info();
2160
2161out:
2162 return ret;

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2508 }
2509
2510 return 0;
2511}
2512
2513/*
2514 * Init the device table to not allow DMA access for devices
2515 */
2514static void init_device_table_dma(void)
2516static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg)
2515{
2516 u32 devid;
2517{
2518 u32 devid;
2519 struct dev_table_entry *dev_table = pci_seg->dev_table;
2517
2520
2521 if (dev_table == NULL)
2522 return;
2523
2518 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2519 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
2520 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
2521 }
2522}
2523
2524 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2525 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
2526 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
2527 }
2528}
2529
2524static void __init uninit_device_table_dma(void)
2530static void __init uninit_device_table_dma(struct amd_iommu_pci_seg *pci_seg)
2525{
2526 u32 devid;
2531{
2532 u32 devid;
2533 struct dev_table_entry *dev_table = pci_seg->dev_table;
2527
2534
2535 if (dev_table == NULL)
2536 return;
2537
2528 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2538 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2529 amd_iommu_dev_table[devid].data[0] = 0ULL;
2530 amd_iommu_dev_table[devid].data[1] = 0ULL;
2539 dev_table[devid].data[0] = 0ULL;
2540 dev_table[devid].data[1] = 0ULL;
2531 }
2532}
2533
2534static void init_device_table(void)
2535{
2536 u32 devid;
2537
2538 if (!amd_iommu_irq_remap)

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3115
3116 if (ret) {
3117 free_dma_resources();
3118 if (!irq_remapping_enabled) {
3119 disable_iommus();
3120 free_iommu_resources();
3121 } else {
3122 struct amd_iommu *iommu;
2541 }
2542}
2543
2544static void init_device_table(void)
2545{
2546 u32 devid;
2547
2548 if (!amd_iommu_irq_remap)

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3125
3126 if (ret) {
3127 free_dma_resources();
3128 if (!irq_remapping_enabled) {
3129 disable_iommus();
3130 free_iommu_resources();
3131 } else {
3132 struct amd_iommu *iommu;
3133 struct amd_iommu_pci_seg *pci_seg;
3123
3134
3124 uninit_device_table_dma();
3135 for_each_pci_segment(pci_seg)
3136 uninit_device_table_dma(pci_seg);
3137
3125 for_each_iommu(iommu)
3126 iommu_flush_all_caches(iommu);
3127 }
3128 }
3129 return ret;
3130}
3131
3132static int __init iommu_go_to_state(enum iommu_init_state state)

--- 386 unchanged lines hidden --- 		3138 for_each_iommu(iommu)
3139 iommu_flush_all_caches(iommu);
3140 }
3141 }
3142 return ret;
3143}
3144
3145static int __init iommu_go_to_state(enum iommu_init_state state)

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