1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #define pr_fmt(fmt) "AMD-Vi: " fmt 9 #define dev_fmt(fmt) pr_fmt(fmt) 10 11 #include <linux/pci.h> 12 #include <linux/acpi.h> 13 #include <linux/list.h> 14 #include <linux/bitmap.h> 15 #include <linux/slab.h> 16 #include <linux/syscore_ops.h> 17 #include <linux/interrupt.h> 18 #include <linux/msi.h> 19 #include <linux/irq.h> 20 #include <linux/amd-iommu.h> 21 #include <linux/export.h> 22 #include <linux/kmemleak.h> 23 #include <linux/cc_platform.h> 24 #include <linux/iopoll.h> 25 #include <asm/pci-direct.h> 26 #include <asm/iommu.h> 27 #include <asm/apic.h> 28 #include <asm/gart.h> 29 #include <asm/x86_init.h> 30 #include <asm/io_apic.h> 31 #include <asm/irq_remapping.h> 32 #include <asm/set_memory.h> 33 34 #include <linux/crash_dump.h> 35 36 #include "amd_iommu.h" 37 #include "../irq_remapping.h" 38 39 /* 40 * definitions for the ACPI scanning code 41 */ 42 #define IVRS_HEADER_LENGTH 48 43 44 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40 45 #define ACPI_IVMD_TYPE_ALL 0x20 46 #define ACPI_IVMD_TYPE 0x21 47 #define ACPI_IVMD_TYPE_RANGE 0x22 48 49 #define IVHD_DEV_ALL 0x01 50 #define IVHD_DEV_SELECT 0x02 51 #define IVHD_DEV_SELECT_RANGE_START 0x03 52 #define IVHD_DEV_RANGE_END 0x04 53 #define IVHD_DEV_ALIAS 0x42 54 #define IVHD_DEV_ALIAS_RANGE 0x43 55 #define IVHD_DEV_EXT_SELECT 0x46 56 #define IVHD_DEV_EXT_SELECT_RANGE 0x47 57 #define IVHD_DEV_SPECIAL 0x48 58 #define IVHD_DEV_ACPI_HID 0xf0 59 60 #define UID_NOT_PRESENT 0 61 #define UID_IS_INTEGER 1 62 #define UID_IS_CHARACTER 2 63 64 #define IVHD_SPECIAL_IOAPIC 1 65 #define IVHD_SPECIAL_HPET 2 66 67 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 68 #define IVHD_FLAG_PASSPW_EN_MASK 0x02 69 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 70 #define IVHD_FLAG_ISOC_EN_MASK 0x08 71 72 #define IVMD_FLAG_EXCL_RANGE 0x08 73 #define IVMD_FLAG_IW 0x04 74 #define IVMD_FLAG_IR 0x02 75 #define IVMD_FLAG_UNITY_MAP 0x01 76 77 #define ACPI_DEVFLAG_INITPASS 0x01 78 #define ACPI_DEVFLAG_EXTINT 0x02 79 #define ACPI_DEVFLAG_NMI 0x04 80 #define ACPI_DEVFLAG_SYSMGT1 0x10 81 #define ACPI_DEVFLAG_SYSMGT2 0x20 82 #define ACPI_DEVFLAG_LINT0 0x40 83 #define ACPI_DEVFLAG_LINT1 0x80 84 #define ACPI_DEVFLAG_ATSDIS 0x10000000 85 86 #define LOOP_TIMEOUT 2000000 87 /* 88 * ACPI table definitions 89 * 90 * These data structures are laid over the table to parse the important values 91 * out of it. 92 */ 93 94 extern const struct iommu_ops amd_iommu_ops; 95 96 /* 97 * structure describing one IOMMU in the ACPI table. Typically followed by one 98 * or more ivhd_entrys. 99 */ 100 struct ivhd_header { 101 u8 type; 102 u8 flags; 103 u16 length; 104 u16 devid; 105 u16 cap_ptr; 106 u64 mmio_phys; 107 u16 pci_seg; 108 u16 info; 109 u32 efr_attr; 110 111 /* Following only valid on IVHD type 11h and 40h */ 112 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */ 113 u64 res; 114 } __attribute__((packed)); 115 116 /* 117 * A device entry describing which devices a specific IOMMU translates and 118 * which requestor ids they use. 119 */ 120 struct ivhd_entry { 121 u8 type; 122 u16 devid; 123 u8 flags; 124 struct_group(ext_hid, 125 u32 ext; 126 u32 hidh; 127 ); 128 u64 cid; 129 u8 uidf; 130 u8 uidl; 131 u8 uid; 132 } __attribute__((packed)); 133 134 /* 135 * An AMD IOMMU memory definition structure. It defines things like exclusion 136 * ranges for devices and regions that should be unity mapped. 137 */ 138 struct ivmd_header { 139 u8 type; 140 u8 flags; 141 u16 length; 142 u16 devid; 143 u16 aux; 144 u16 pci_seg; 145 u8 resv[6]; 146 u64 range_start; 147 u64 range_length; 148 } __attribute__((packed)); 149 150 bool amd_iommu_dump; 151 bool amd_iommu_irq_remap __read_mostly; 152 153 enum io_pgtable_fmt amd_iommu_pgtable = AMD_IOMMU_V1; 154 155 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 156 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; 157 158 static bool amd_iommu_detected; 159 static bool amd_iommu_disabled __initdata; 160 static bool amd_iommu_force_enable __initdata; 161 static int amd_iommu_target_ivhd_type; 162 163 u16 amd_iommu_last_bdf; /* largest PCI device id we have 164 to handle */ 165 166 LIST_HEAD(amd_iommu_pci_seg_list); /* list of all PCI segments */ 167 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the 168 system */ 169 170 /* Array to assign indices to IOMMUs*/ 171 struct amd_iommu *amd_iommus[MAX_IOMMUS]; 172 173 /* Number of IOMMUs present in the system */ 174 static int amd_iommus_present; 175 176 /* IOMMUs have a non-present cache? */ 177 bool amd_iommu_np_cache __read_mostly; 178 bool amd_iommu_iotlb_sup __read_mostly = true; 179 180 u32 amd_iommu_max_pasid __read_mostly = ~0; 181 182 bool amd_iommu_v2_present __read_mostly; 183 static bool amd_iommu_pc_present __read_mostly; 184 bool amdr_ivrs_remap_support __read_mostly; 185 186 bool amd_iommu_force_isolation __read_mostly; 187 188 /* 189 * Pointer to the device table which is shared by all AMD IOMMUs 190 * it is indexed by the PCI device id or the HT unit id and contains 191 * information about the domain the device belongs to as well as the 192 * page table root pointer. 193 */ 194 struct dev_table_entry *amd_iommu_dev_table; 195 196 /* 197 * The alias table is a driver specific data structure which contains the 198 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 199 * More than one device can share the same requestor id. 200 */ 201 u16 *amd_iommu_alias_table; 202 203 /* 204 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap 205 * to know which ones are already in use. 206 */ 207 unsigned long *amd_iommu_pd_alloc_bitmap; 208 209 static u32 dev_table_size; /* size of the device table */ 210 static u32 alias_table_size; /* size of the alias table */ 211 212 enum iommu_init_state { 213 IOMMU_START_STATE, 214 IOMMU_IVRS_DETECTED, 215 IOMMU_ACPI_FINISHED, 216 IOMMU_ENABLED, 217 IOMMU_PCI_INIT, 218 IOMMU_INTERRUPTS_EN, 219 IOMMU_INITIALIZED, 220 IOMMU_NOT_FOUND, 221 IOMMU_INIT_ERROR, 222 IOMMU_CMDLINE_DISABLED, 223 }; 224 225 /* Early ioapic and hpet maps from kernel command line */ 226 #define EARLY_MAP_SIZE 4 227 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; 228 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; 229 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE]; 230 231 static int __initdata early_ioapic_map_size; 232 static int __initdata early_hpet_map_size; 233 static int __initdata early_acpihid_map_size; 234 235 static bool __initdata cmdline_maps; 236 237 static enum iommu_init_state init_state = IOMMU_START_STATE; 238 239 static int amd_iommu_enable_interrupts(void); 240 static int __init iommu_go_to_state(enum iommu_init_state state); 241 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg); 242 243 static bool amd_iommu_pre_enabled = true; 244 245 static u32 amd_iommu_ivinfo __initdata; 246 247 bool translation_pre_enabled(struct amd_iommu *iommu) 248 { 249 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); 250 } 251 252 static void clear_translation_pre_enabled(struct amd_iommu *iommu) 253 { 254 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 255 } 256 257 static void init_translation_status(struct amd_iommu *iommu) 258 { 259 u64 ctrl; 260 261 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 262 if (ctrl & (1<<CONTROL_IOMMU_EN)) 263 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; 264 } 265 266 static inline void update_last_devid(u16 devid) 267 { 268 if (devid > amd_iommu_last_bdf) 269 amd_iommu_last_bdf = devid; 270 } 271 272 static inline unsigned long tbl_size(int entry_size) 273 { 274 unsigned shift = PAGE_SHIFT + 275 get_order(((int)amd_iommu_last_bdf + 1) * entry_size); 276 277 return 1UL << shift; 278 } 279 280 int amd_iommu_get_num_iommus(void) 281 { 282 return amd_iommus_present; 283 } 284 285 #ifdef CONFIG_IRQ_REMAP 286 static bool check_feature_on_all_iommus(u64 mask) 287 { 288 bool ret = false; 289 struct amd_iommu *iommu; 290 291 for_each_iommu(iommu) { 292 ret = iommu_feature(iommu, mask); 293 if (!ret) 294 return false; 295 } 296 297 return true; 298 } 299 #endif 300 301 /* 302 * For IVHD type 0x11/0x40, EFR is also available via IVHD. 303 * Default to IVHD EFR since it is available sooner 304 * (i.e. before PCI init). 305 */ 306 static void __init early_iommu_features_init(struct amd_iommu *iommu, 307 struct ivhd_header *h) 308 { 309 if (amd_iommu_ivinfo & IOMMU_IVINFO_EFRSUP) 310 iommu->features = h->efr_reg; 311 if (amd_iommu_ivinfo & IOMMU_IVINFO_DMA_REMAP) 312 amdr_ivrs_remap_support = true; 313 } 314 315 /* Access to l1 and l2 indexed register spaces */ 316 317 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) 318 { 319 u32 val; 320 321 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 322 pci_read_config_dword(iommu->dev, 0xfc, &val); 323 return val; 324 } 325 326 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) 327 { 328 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); 329 pci_write_config_dword(iommu->dev, 0xfc, val); 330 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); 331 } 332 333 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) 334 { 335 u32 val; 336 337 pci_write_config_dword(iommu->dev, 0xf0, address); 338 pci_read_config_dword(iommu->dev, 0xf4, &val); 339 return val; 340 } 341 342 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) 343 { 344 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); 345 pci_write_config_dword(iommu->dev, 0xf4, val); 346 } 347 348 /**************************************************************************** 349 * 350 * AMD IOMMU MMIO register space handling functions 351 * 352 * These functions are used to program the IOMMU device registers in 353 * MMIO space required for that driver. 354 * 355 ****************************************************************************/ 356 357 /* 358 * This function set the exclusion range in the IOMMU. DMA accesses to the 359 * exclusion range are passed through untranslated 360 */ 361 static void iommu_set_exclusion_range(struct amd_iommu *iommu) 362 { 363 u64 start = iommu->exclusion_start & PAGE_MASK; 364 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; 365 u64 entry; 366 367 if (!iommu->exclusion_start) 368 return; 369 370 entry = start | MMIO_EXCL_ENABLE_MASK; 371 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 372 &entry, sizeof(entry)); 373 374 entry = limit; 375 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 376 &entry, sizeof(entry)); 377 } 378 379 static void iommu_set_cwwb_range(struct amd_iommu *iommu) 380 { 381 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); 382 u64 entry = start & PM_ADDR_MASK; 383 384 if (!iommu_feature(iommu, FEATURE_SNP)) 385 return; 386 387 /* Note: 388 * Re-purpose Exclusion base/limit registers for Completion wait 389 * write-back base/limit. 390 */ 391 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, 392 &entry, sizeof(entry)); 393 394 /* Note: 395 * Default to 4 Kbytes, which can be specified by setting base 396 * address equal to the limit address. 397 */ 398 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, 399 &entry, sizeof(entry)); 400 } 401 402 /* Programs the physical address of the device table into the IOMMU hardware */ 403 static void iommu_set_device_table(struct amd_iommu *iommu) 404 { 405 u64 entry; 406 u32 dev_table_size = iommu->pci_seg->dev_table_size; 407 408 BUG_ON(iommu->mmio_base == NULL); 409 410 entry = iommu_virt_to_phys(amd_iommu_dev_table); 411 entry |= (dev_table_size >> 12) - 1; 412 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, 413 &entry, sizeof(entry)); 414 } 415 416 /* Generic functions to enable/disable certain features of the IOMMU. */ 417 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) 418 { 419 u64 ctrl; 420 421 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 422 ctrl |= (1ULL << bit); 423 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 424 } 425 426 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) 427 { 428 u64 ctrl; 429 430 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 431 ctrl &= ~(1ULL << bit); 432 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 433 } 434 435 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) 436 { 437 u64 ctrl; 438 439 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); 440 ctrl &= ~CTRL_INV_TO_MASK; 441 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK; 442 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); 443 } 444 445 /* Function to enable the hardware */ 446 static void iommu_enable(struct amd_iommu *iommu) 447 { 448 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); 449 } 450 451 static void iommu_disable(struct amd_iommu *iommu) 452 { 453 if (!iommu->mmio_base) 454 return; 455 456 /* Disable command buffer */ 457 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 458 459 /* Disable event logging and event interrupts */ 460 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); 461 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 462 463 /* Disable IOMMU GA_LOG */ 464 iommu_feature_disable(iommu, CONTROL_GALOG_EN); 465 iommu_feature_disable(iommu, CONTROL_GAINT_EN); 466 467 /* Disable IOMMU hardware itself */ 468 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); 469 } 470 471 /* 472 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in 473 * the system has one. 474 */ 475 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) 476 { 477 if (!request_mem_region(address, end, "amd_iommu")) { 478 pr_err("Can not reserve memory region %llx-%llx for mmio\n", 479 address, end); 480 pr_err("This is a BIOS bug. Please contact your hardware vendor\n"); 481 return NULL; 482 } 483 484 return (u8 __iomem *)ioremap(address, end); 485 } 486 487 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) 488 { 489 if (iommu->mmio_base) 490 iounmap(iommu->mmio_base); 491 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); 492 } 493 494 static inline u32 get_ivhd_header_size(struct ivhd_header *h) 495 { 496 u32 size = 0; 497 498 switch (h->type) { 499 case 0x10: 500 size = 24; 501 break; 502 case 0x11: 503 case 0x40: 504 size = 40; 505 break; 506 } 507 return size; 508 } 509 510 /**************************************************************************** 511 * 512 * The functions below belong to the first pass of AMD IOMMU ACPI table 513 * parsing. In this pass we try to find out the highest device id this 514 * code has to handle. Upon this information the size of the shared data 515 * structures is determined later. 516 * 517 ****************************************************************************/ 518 519 /* 520 * This function calculates the length of a given IVHD entry 521 */ 522 static inline int ivhd_entry_length(u8 *ivhd) 523 { 524 u32 type = ((struct ivhd_entry *)ivhd)->type; 525 526 if (type < 0x80) { 527 return 0x04 << (*ivhd >> 6); 528 } else if (type == IVHD_DEV_ACPI_HID) { 529 /* For ACPI_HID, offset 21 is uid len */ 530 return *((u8 *)ivhd + 21) + 22; 531 } 532 return 0; 533 } 534 535 /* 536 * After reading the highest device id from the IOMMU PCI capability header 537 * this function looks if there is a higher device id defined in the ACPI table 538 */ 539 static int __init find_last_devid_from_ivhd(struct ivhd_header *h) 540 { 541 u8 *p = (void *)h, *end = (void *)h; 542 struct ivhd_entry *dev; 543 int last_devid = -EINVAL; 544 545 u32 ivhd_size = get_ivhd_header_size(h); 546 547 if (!ivhd_size) { 548 pr_err("Unsupported IVHD type %#x\n", h->type); 549 return -EINVAL; 550 } 551 552 p += ivhd_size; 553 end += h->length; 554 555 while (p < end) { 556 dev = (struct ivhd_entry *)p; 557 switch (dev->type) { 558 case IVHD_DEV_ALL: 559 /* Use maximum BDF value for DEV_ALL */ 560 update_last_devid(0xffff); 561 return 0xffff; 562 case IVHD_DEV_SELECT: 563 case IVHD_DEV_RANGE_END: 564 case IVHD_DEV_ALIAS: 565 case IVHD_DEV_EXT_SELECT: 566 /* all the above subfield types refer to device ids */ 567 update_last_devid(dev->devid); 568 if (dev->devid > last_devid) 569 last_devid = dev->devid; 570 break; 571 default: 572 break; 573 } 574 p += ivhd_entry_length(p); 575 } 576 577 WARN_ON(p != end); 578 579 return last_devid; 580 } 581 582 static int __init check_ivrs_checksum(struct acpi_table_header *table) 583 { 584 int i; 585 u8 checksum = 0, *p = (u8 *)table; 586 587 for (i = 0; i < table->length; ++i) 588 checksum += p[i]; 589 if (checksum != 0) { 590 /* ACPI table corrupt */ 591 pr_err(FW_BUG "IVRS invalid checksum\n"); 592 return -ENODEV; 593 } 594 595 return 0; 596 } 597 598 /* 599 * Iterate over all IVHD entries in the ACPI table and find the highest device 600 * id which we need to handle. This is the first of three functions which parse 601 * the ACPI table. So we check the checksum here. 602 */ 603 static int __init find_last_devid_acpi(struct acpi_table_header *table, u16 pci_seg) 604 { 605 u8 *p = (u8 *)table, *end = (u8 *)table; 606 struct ivhd_header *h; 607 int last_devid, last_bdf = 0; 608 609 p += IVRS_HEADER_LENGTH; 610 611 end += table->length; 612 while (p < end) { 613 h = (struct ivhd_header *)p; 614 if (h->pci_seg == pci_seg && 615 h->type == amd_iommu_target_ivhd_type) { 616 last_devid = find_last_devid_from_ivhd(h); 617 618 if (last_devid < 0) 619 return -EINVAL; 620 if (last_devid > last_bdf) 621 last_bdf = last_devid; 622 } 623 p += h->length; 624 } 625 WARN_ON(p != end); 626 627 return last_bdf; 628 } 629 630 /**************************************************************************** 631 * 632 * The following functions belong to the code path which parses the ACPI table 633 * the second time. In this ACPI parsing iteration we allocate IOMMU specific 634 * data structures, initialize the per PCI segment device/alias/rlookup table 635 * and also basically initialize the hardware. 636 * 637 ****************************************************************************/ 638 639 /* Allocate per PCI segment device table */ 640 static inline int __init alloc_dev_table(struct amd_iommu_pci_seg *pci_seg) 641 { 642 pci_seg->dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO | GFP_DMA32, 643 get_order(pci_seg->dev_table_size)); 644 if (!pci_seg->dev_table) 645 return -ENOMEM; 646 647 return 0; 648 } 649 650 static inline void free_dev_table(struct amd_iommu_pci_seg *pci_seg) 651 { 652 free_pages((unsigned long)pci_seg->dev_table, 653 get_order(pci_seg->dev_table_size)); 654 pci_seg->dev_table = NULL; 655 } 656 657 /* Allocate per PCI segment IOMMU rlookup table. */ 658 static inline int __init alloc_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 659 { 660 pci_seg->rlookup_table = (void *)__get_free_pages( 661 GFP_KERNEL | __GFP_ZERO, 662 get_order(pci_seg->rlookup_table_size)); 663 if (pci_seg->rlookup_table == NULL) 664 return -ENOMEM; 665 666 return 0; 667 } 668 669 static inline void free_rlookup_table(struct amd_iommu_pci_seg *pci_seg) 670 { 671 free_pages((unsigned long)pci_seg->rlookup_table, 672 get_order(pci_seg->rlookup_table_size)); 673 pci_seg->rlookup_table = NULL; 674 } 675 676 static inline int __init alloc_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 677 { 678 pci_seg->irq_lookup_table = (void *)__get_free_pages( 679 GFP_KERNEL | __GFP_ZERO, 680 get_order(pci_seg->rlookup_table_size)); 681 kmemleak_alloc(pci_seg->irq_lookup_table, 682 pci_seg->rlookup_table_size, 1, GFP_KERNEL); 683 if (pci_seg->irq_lookup_table == NULL) 684 return -ENOMEM; 685 686 return 0; 687 } 688 689 static inline void free_irq_lookup_table(struct amd_iommu_pci_seg *pci_seg) 690 { 691 kmemleak_free(pci_seg->irq_lookup_table); 692 free_pages((unsigned long)pci_seg->irq_lookup_table, 693 get_order(pci_seg->rlookup_table_size)); 694 pci_seg->irq_lookup_table = NULL; 695 } 696 697 static int __init alloc_alias_table(struct amd_iommu_pci_seg *pci_seg) 698 { 699 int i; 700 701 pci_seg->alias_table = (void *)__get_free_pages(GFP_KERNEL, 702 get_order(pci_seg->alias_table_size)); 703 if (!pci_seg->alias_table) 704 return -ENOMEM; 705 706 /* 707 * let all alias entries point to itself 708 */ 709 for (i = 0; i <= amd_iommu_last_bdf; ++i) 710 pci_seg->alias_table[i] = i; 711 712 return 0; 713 } 714 715 static void __init free_alias_table(struct amd_iommu_pci_seg *pci_seg) 716 { 717 free_pages((unsigned long)pci_seg->alias_table, 718 get_order(pci_seg->alias_table_size)); 719 pci_seg->alias_table = NULL; 720 } 721 722 /* 723 * Allocates the command buffer. This buffer is per AMD IOMMU. We can 724 * write commands to that buffer later and the IOMMU will execute them 725 * asynchronously 726 */ 727 static int __init alloc_command_buffer(struct amd_iommu *iommu) 728 { 729 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 730 get_order(CMD_BUFFER_SIZE)); 731 732 return iommu->cmd_buf ? 0 : -ENOMEM; 733 } 734 735 /* 736 * This function restarts event logging in case the IOMMU experienced 737 * an event log buffer overflow. 738 */ 739 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) 740 { 741 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 742 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 743 } 744 745 /* 746 * This function resets the command buffer if the IOMMU stopped fetching 747 * commands from it. 748 */ 749 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) 750 { 751 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 752 753 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); 754 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); 755 iommu->cmd_buf_head = 0; 756 iommu->cmd_buf_tail = 0; 757 758 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); 759 } 760 761 /* 762 * This function writes the command buffer address to the hardware and 763 * enables it. 764 */ 765 static void iommu_enable_command_buffer(struct amd_iommu *iommu) 766 { 767 u64 entry; 768 769 BUG_ON(iommu->cmd_buf == NULL); 770 771 entry = iommu_virt_to_phys(iommu->cmd_buf); 772 entry |= MMIO_CMD_SIZE_512; 773 774 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, 775 &entry, sizeof(entry)); 776 777 amd_iommu_reset_cmd_buffer(iommu); 778 } 779 780 /* 781 * This function disables the command buffer 782 */ 783 static void iommu_disable_command_buffer(struct amd_iommu *iommu) 784 { 785 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); 786 } 787 788 static void __init free_command_buffer(struct amd_iommu *iommu) 789 { 790 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); 791 } 792 793 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, 794 gfp_t gfp, size_t size) 795 { 796 int order = get_order(size); 797 void *buf = (void *)__get_free_pages(gfp, order); 798 799 if (buf && 800 iommu_feature(iommu, FEATURE_SNP) && 801 set_memory_4k((unsigned long)buf, (1 << order))) { 802 free_pages((unsigned long)buf, order); 803 buf = NULL; 804 } 805 806 return buf; 807 } 808 809 /* allocates the memory where the IOMMU will log its events to */ 810 static int __init alloc_event_buffer(struct amd_iommu *iommu) 811 { 812 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 813 EVT_BUFFER_SIZE); 814 815 return iommu->evt_buf ? 0 : -ENOMEM; 816 } 817 818 static void iommu_enable_event_buffer(struct amd_iommu *iommu) 819 { 820 u64 entry; 821 822 BUG_ON(iommu->evt_buf == NULL); 823 824 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; 825 826 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, 827 &entry, sizeof(entry)); 828 829 /* set head and tail to zero manually */ 830 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); 831 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); 832 833 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); 834 } 835 836 /* 837 * This function disables the event log buffer 838 */ 839 static void iommu_disable_event_buffer(struct amd_iommu *iommu) 840 { 841 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); 842 } 843 844 static void __init free_event_buffer(struct amd_iommu *iommu) 845 { 846 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); 847 } 848 849 /* allocates the memory where the IOMMU will log its events to */ 850 static int __init alloc_ppr_log(struct amd_iommu *iommu) 851 { 852 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 853 PPR_LOG_SIZE); 854 855 return iommu->ppr_log ? 0 : -ENOMEM; 856 } 857 858 static void iommu_enable_ppr_log(struct amd_iommu *iommu) 859 { 860 u64 entry; 861 862 if (iommu->ppr_log == NULL) 863 return; 864 865 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; 866 867 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, 868 &entry, sizeof(entry)); 869 870 /* set head and tail to zero manually */ 871 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); 872 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); 873 874 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); 875 iommu_feature_enable(iommu, CONTROL_PPR_EN); 876 } 877 878 static void __init free_ppr_log(struct amd_iommu *iommu) 879 { 880 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); 881 } 882 883 static void free_ga_log(struct amd_iommu *iommu) 884 { 885 #ifdef CONFIG_IRQ_REMAP 886 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); 887 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); 888 #endif 889 } 890 891 static int iommu_ga_log_enable(struct amd_iommu *iommu) 892 { 893 #ifdef CONFIG_IRQ_REMAP 894 u32 status, i; 895 u64 entry; 896 897 if (!iommu->ga_log) 898 return -EINVAL; 899 900 /* Check if already running */ 901 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 902 if (WARN_ON(status & (MMIO_STATUS_GALOG_RUN_MASK))) 903 return 0; 904 905 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; 906 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, 907 &entry, sizeof(entry)); 908 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & 909 (BIT_ULL(52)-1)) & ~7ULL; 910 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, 911 &entry, sizeof(entry)); 912 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); 913 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); 914 915 916 iommu_feature_enable(iommu, CONTROL_GAINT_EN); 917 iommu_feature_enable(iommu, CONTROL_GALOG_EN); 918 919 for (i = 0; i < LOOP_TIMEOUT; ++i) { 920 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); 921 if (status & (MMIO_STATUS_GALOG_RUN_MASK)) 922 break; 923 udelay(10); 924 } 925 926 if (WARN_ON(i >= LOOP_TIMEOUT)) 927 return -EINVAL; 928 #endif /* CONFIG_IRQ_REMAP */ 929 return 0; 930 } 931 932 static int iommu_init_ga_log(struct amd_iommu *iommu) 933 { 934 #ifdef CONFIG_IRQ_REMAP 935 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 936 return 0; 937 938 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 939 get_order(GA_LOG_SIZE)); 940 if (!iommu->ga_log) 941 goto err_out; 942 943 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 944 get_order(8)); 945 if (!iommu->ga_log_tail) 946 goto err_out; 947 948 return 0; 949 err_out: 950 free_ga_log(iommu); 951 return -EINVAL; 952 #else 953 return 0; 954 #endif /* CONFIG_IRQ_REMAP */ 955 } 956 957 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) 958 { 959 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); 960 961 return iommu->cmd_sem ? 0 : -ENOMEM; 962 } 963 964 static void __init free_cwwb_sem(struct amd_iommu *iommu) 965 { 966 if (iommu->cmd_sem) 967 free_page((unsigned long)iommu->cmd_sem); 968 } 969 970 static void iommu_enable_xt(struct amd_iommu *iommu) 971 { 972 #ifdef CONFIG_IRQ_REMAP 973 /* 974 * XT mode (32-bit APIC destination ID) requires 975 * GA mode (128-bit IRTE support) as a prerequisite. 976 */ 977 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) && 978 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 979 iommu_feature_enable(iommu, CONTROL_XT_EN); 980 #endif /* CONFIG_IRQ_REMAP */ 981 } 982 983 static void iommu_enable_gt(struct amd_iommu *iommu) 984 { 985 if (!iommu_feature(iommu, FEATURE_GT)) 986 return; 987 988 iommu_feature_enable(iommu, CONTROL_GT_EN); 989 } 990 991 /* sets a specific bit in the device table entry. */ 992 static void set_dev_entry_bit(u16 devid, u8 bit) 993 { 994 int i = (bit >> 6) & 0x03; 995 int _bit = bit & 0x3f; 996 997 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); 998 } 999 1000 static int get_dev_entry_bit(u16 devid, u8 bit) 1001 { 1002 int i = (bit >> 6) & 0x03; 1003 int _bit = bit & 0x3f; 1004 1005 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; 1006 } 1007 1008 1009 static bool __copy_device_table(struct amd_iommu *iommu) 1010 { 1011 u64 int_ctl, int_tab_len, entry = 0; 1012 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1013 struct dev_table_entry *old_devtb = NULL; 1014 u32 lo, hi, devid, old_devtb_size; 1015 phys_addr_t old_devtb_phys; 1016 u16 dom_id, dte_v, irq_v; 1017 gfp_t gfp_flag; 1018 u64 tmp; 1019 1020 /* Each IOMMU use separate device table with the same size */ 1021 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); 1022 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); 1023 entry = (((u64) hi) << 32) + lo; 1024 1025 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12; 1026 if (old_devtb_size != pci_seg->dev_table_size) { 1027 pr_err("The device table size of IOMMU:%d is not expected!\n", 1028 iommu->index); 1029 return false; 1030 } 1031 1032 /* 1033 * When SME is enabled in the first kernel, the entry includes the 1034 * memory encryption mask(sme_me_mask), we must remove the memory 1035 * encryption mask to obtain the true physical address in kdump kernel. 1036 */ 1037 old_devtb_phys = __sme_clr(entry) & PAGE_MASK; 1038 1039 if (old_devtb_phys >= 0x100000000ULL) { 1040 pr_err("The address of old device table is above 4G, not trustworthy!\n"); 1041 return false; 1042 } 1043 old_devtb = (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) && is_kdump_kernel()) 1044 ? (__force void *)ioremap_encrypted(old_devtb_phys, 1045 pci_seg->dev_table_size) 1046 : memremap(old_devtb_phys, pci_seg->dev_table_size, MEMREMAP_WB); 1047 1048 if (!old_devtb) 1049 return false; 1050 1051 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32; 1052 pci_seg->old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag, 1053 get_order(pci_seg->dev_table_size)); 1054 if (pci_seg->old_dev_tbl_cpy == NULL) { 1055 pr_err("Failed to allocate memory for copying old device table!\n"); 1056 memunmap(old_devtb); 1057 return false; 1058 } 1059 1060 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 1061 pci_seg->old_dev_tbl_cpy[devid] = old_devtb[devid]; 1062 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK; 1063 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V; 1064 1065 if (dte_v && dom_id) { 1066 pci_seg->old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0]; 1067 pci_seg->old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1]; 1068 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap); 1069 /* If gcr3 table existed, mask it out */ 1070 if (old_devtb[devid].data[0] & DTE_FLAG_GV) { 1071 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; 1072 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; 1073 pci_seg->old_dev_tbl_cpy[devid].data[1] &= ~tmp; 1074 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A; 1075 tmp |= DTE_FLAG_GV; 1076 pci_seg->old_dev_tbl_cpy[devid].data[0] &= ~tmp; 1077 } 1078 } 1079 1080 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; 1081 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; 1082 int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK; 1083 if (irq_v && (int_ctl || int_tab_len)) { 1084 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) || 1085 (int_tab_len != DTE_INTTABLEN)) { 1086 pr_err("Wrong old irq remapping flag: %#x\n", devid); 1087 memunmap(old_devtb); 1088 return false; 1089 } 1090 1091 pci_seg->old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2]; 1092 } 1093 } 1094 memunmap(old_devtb); 1095 1096 return true; 1097 } 1098 1099 static bool copy_device_table(void) 1100 { 1101 struct amd_iommu *iommu; 1102 struct amd_iommu_pci_seg *pci_seg; 1103 1104 if (!amd_iommu_pre_enabled) 1105 return false; 1106 1107 pr_warn("Translation is already enabled - trying to copy translation structures\n"); 1108 1109 /* 1110 * All IOMMUs within PCI segment shares common device table. 1111 * Hence copy device table only once per PCI segment. 1112 */ 1113 for_each_pci_segment(pci_seg) { 1114 for_each_iommu(iommu) { 1115 if (pci_seg->id != iommu->pci_seg->id) 1116 continue; 1117 if (!__copy_device_table(iommu)) 1118 return false; 1119 break; 1120 } 1121 } 1122 1123 return true; 1124 } 1125 1126 void amd_iommu_apply_erratum_63(u16 devid) 1127 { 1128 int sysmgt; 1129 1130 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | 1131 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); 1132 1133 if (sysmgt == 0x01) 1134 set_dev_entry_bit(devid, DEV_ENTRY_IW); 1135 } 1136 1137 /* Writes the specific IOMMU for a device into the rlookup table */ 1138 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) 1139 { 1140 iommu->pci_seg->rlookup_table[devid] = iommu; 1141 } 1142 1143 /* 1144 * This function takes the device specific flags read from the ACPI 1145 * table and sets up the device table entry with that information 1146 */ 1147 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, 1148 u16 devid, u32 flags, u32 ext_flags) 1149 { 1150 if (flags & ACPI_DEVFLAG_INITPASS) 1151 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); 1152 if (flags & ACPI_DEVFLAG_EXTINT) 1153 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); 1154 if (flags & ACPI_DEVFLAG_NMI) 1155 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); 1156 if (flags & ACPI_DEVFLAG_SYSMGT1) 1157 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); 1158 if (flags & ACPI_DEVFLAG_SYSMGT2) 1159 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); 1160 if (flags & ACPI_DEVFLAG_LINT0) 1161 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); 1162 if (flags & ACPI_DEVFLAG_LINT1) 1163 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); 1164 1165 amd_iommu_apply_erratum_63(devid); 1166 1167 set_iommu_for_device(iommu, devid); 1168 } 1169 1170 int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line) 1171 { 1172 struct devid_map *entry; 1173 struct list_head *list; 1174 1175 if (type == IVHD_SPECIAL_IOAPIC) 1176 list = &ioapic_map; 1177 else if (type == IVHD_SPECIAL_HPET) 1178 list = &hpet_map; 1179 else 1180 return -EINVAL; 1181 1182 list_for_each_entry(entry, list, list) { 1183 if (!(entry->id == id && entry->cmd_line)) 1184 continue; 1185 1186 pr_info("Command-line override present for %s id %d - ignoring\n", 1187 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id); 1188 1189 *devid = entry->devid; 1190 1191 return 0; 1192 } 1193 1194 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1195 if (!entry) 1196 return -ENOMEM; 1197 1198 entry->id = id; 1199 entry->devid = *devid; 1200 entry->cmd_line = cmd_line; 1201 1202 list_add_tail(&entry->list, list); 1203 1204 return 0; 1205 } 1206 1207 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid, 1208 bool cmd_line) 1209 { 1210 struct acpihid_map_entry *entry; 1211 struct list_head *list = &acpihid_map; 1212 1213 list_for_each_entry(entry, list, list) { 1214 if (strcmp(entry->hid, hid) || 1215 (*uid && *entry->uid && strcmp(entry->uid, uid)) || 1216 !entry->cmd_line) 1217 continue; 1218 1219 pr_info("Command-line override for hid:%s uid:%s\n", 1220 hid, uid); 1221 *devid = entry->devid; 1222 return 0; 1223 } 1224 1225 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 1226 if (!entry) 1227 return -ENOMEM; 1228 1229 memcpy(entry->uid, uid, strlen(uid)); 1230 memcpy(entry->hid, hid, strlen(hid)); 1231 entry->devid = *devid; 1232 entry->cmd_line = cmd_line; 1233 entry->root_devid = (entry->devid & (~0x7)); 1234 1235 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n", 1236 entry->cmd_line ? "cmd" : "ivrs", 1237 entry->hid, entry->uid, entry->root_devid); 1238 1239 list_add_tail(&entry->list, list); 1240 return 0; 1241 } 1242 1243 static int __init add_early_maps(void) 1244 { 1245 int i, ret; 1246 1247 for (i = 0; i < early_ioapic_map_size; ++i) { 1248 ret = add_special_device(IVHD_SPECIAL_IOAPIC, 1249 early_ioapic_map[i].id, 1250 &early_ioapic_map[i].devid, 1251 early_ioapic_map[i].cmd_line); 1252 if (ret) 1253 return ret; 1254 } 1255 1256 for (i = 0; i < early_hpet_map_size; ++i) { 1257 ret = add_special_device(IVHD_SPECIAL_HPET, 1258 early_hpet_map[i].id, 1259 &early_hpet_map[i].devid, 1260 early_hpet_map[i].cmd_line); 1261 if (ret) 1262 return ret; 1263 } 1264 1265 for (i = 0; i < early_acpihid_map_size; ++i) { 1266 ret = add_acpi_hid_device(early_acpihid_map[i].hid, 1267 early_acpihid_map[i].uid, 1268 &early_acpihid_map[i].devid, 1269 early_acpihid_map[i].cmd_line); 1270 if (ret) 1271 return ret; 1272 } 1273 1274 return 0; 1275 } 1276 1277 /* 1278 * Takes a pointer to an AMD IOMMU entry in the ACPI table and 1279 * initializes the hardware and our data structures with it. 1280 */ 1281 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, 1282 struct ivhd_header *h) 1283 { 1284 u8 *p = (u8 *)h; 1285 u8 *end = p, flags = 0; 1286 u16 devid = 0, devid_start = 0, devid_to = 0; 1287 u32 dev_i, ext_flags = 0; 1288 bool alias = false; 1289 struct ivhd_entry *e; 1290 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; 1291 u32 ivhd_size; 1292 int ret; 1293 1294 1295 ret = add_early_maps(); 1296 if (ret) 1297 return ret; 1298 1299 amd_iommu_apply_ivrs_quirks(); 1300 1301 /* 1302 * First save the recommended feature enable bits from ACPI 1303 */ 1304 iommu->acpi_flags = h->flags; 1305 1306 /* 1307 * Done. Now parse the device entries 1308 */ 1309 ivhd_size = get_ivhd_header_size(h); 1310 if (!ivhd_size) { 1311 pr_err("Unsupported IVHD type %#x\n", h->type); 1312 return -EINVAL; 1313 } 1314 1315 p += ivhd_size; 1316 1317 end += h->length; 1318 1319 1320 while (p < end) { 1321 e = (struct ivhd_entry *)p; 1322 switch (e->type) { 1323 case IVHD_DEV_ALL: 1324 1325 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags); 1326 1327 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i) 1328 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); 1329 break; 1330 case IVHD_DEV_SELECT: 1331 1332 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " 1333 "flags: %02x\n", 1334 PCI_BUS_NUM(e->devid), 1335 PCI_SLOT(e->devid), 1336 PCI_FUNC(e->devid), 1337 e->flags); 1338 1339 devid = e->devid; 1340 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1341 break; 1342 case IVHD_DEV_SELECT_RANGE_START: 1343 1344 DUMP_printk(" DEV_SELECT_RANGE_START\t " 1345 "devid: %02x:%02x.%x flags: %02x\n", 1346 PCI_BUS_NUM(e->devid), 1347 PCI_SLOT(e->devid), 1348 PCI_FUNC(e->devid), 1349 e->flags); 1350 1351 devid_start = e->devid; 1352 flags = e->flags; 1353 ext_flags = 0; 1354 alias = false; 1355 break; 1356 case IVHD_DEV_ALIAS: 1357 1358 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " 1359 "flags: %02x devid_to: %02x:%02x.%x\n", 1360 PCI_BUS_NUM(e->devid), 1361 PCI_SLOT(e->devid), 1362 PCI_FUNC(e->devid), 1363 e->flags, 1364 PCI_BUS_NUM(e->ext >> 8), 1365 PCI_SLOT(e->ext >> 8), 1366 PCI_FUNC(e->ext >> 8)); 1367 1368 devid = e->devid; 1369 devid_to = e->ext >> 8; 1370 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); 1371 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); 1372 pci_seg->alias_table[devid] = devid_to; 1373 break; 1374 case IVHD_DEV_ALIAS_RANGE: 1375 1376 DUMP_printk(" DEV_ALIAS_RANGE\t\t " 1377 "devid: %02x:%02x.%x flags: %02x " 1378 "devid_to: %02x:%02x.%x\n", 1379 PCI_BUS_NUM(e->devid), 1380 PCI_SLOT(e->devid), 1381 PCI_FUNC(e->devid), 1382 e->flags, 1383 PCI_BUS_NUM(e->ext >> 8), 1384 PCI_SLOT(e->ext >> 8), 1385 PCI_FUNC(e->ext >> 8)); 1386 1387 devid_start = e->devid; 1388 flags = e->flags; 1389 devid_to = e->ext >> 8; 1390 ext_flags = 0; 1391 alias = true; 1392 break; 1393 case IVHD_DEV_EXT_SELECT: 1394 1395 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " 1396 "flags: %02x ext: %08x\n", 1397 PCI_BUS_NUM(e->devid), 1398 PCI_SLOT(e->devid), 1399 PCI_FUNC(e->devid), 1400 e->flags, e->ext); 1401 1402 devid = e->devid; 1403 set_dev_entry_from_acpi(iommu, devid, e->flags, 1404 e->ext); 1405 break; 1406 case IVHD_DEV_EXT_SELECT_RANGE: 1407 1408 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " 1409 "%02x:%02x.%x flags: %02x ext: %08x\n", 1410 PCI_BUS_NUM(e->devid), 1411 PCI_SLOT(e->devid), 1412 PCI_FUNC(e->devid), 1413 e->flags, e->ext); 1414 1415 devid_start = e->devid; 1416 flags = e->flags; 1417 ext_flags = e->ext; 1418 alias = false; 1419 break; 1420 case IVHD_DEV_RANGE_END: 1421 1422 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", 1423 PCI_BUS_NUM(e->devid), 1424 PCI_SLOT(e->devid), 1425 PCI_FUNC(e->devid)); 1426 1427 devid = e->devid; 1428 for (dev_i = devid_start; dev_i <= devid; ++dev_i) { 1429 if (alias) { 1430 pci_seg->alias_table[dev_i] = devid_to; 1431 set_dev_entry_from_acpi(iommu, 1432 devid_to, flags, ext_flags); 1433 } 1434 set_dev_entry_from_acpi(iommu, dev_i, 1435 flags, ext_flags); 1436 } 1437 break; 1438 case IVHD_DEV_SPECIAL: { 1439 u8 handle, type; 1440 const char *var; 1441 u16 devid; 1442 int ret; 1443 1444 handle = e->ext & 0xff; 1445 devid = (e->ext >> 8) & 0xffff; 1446 type = (e->ext >> 24) & 0xff; 1447 1448 if (type == IVHD_SPECIAL_IOAPIC) 1449 var = "IOAPIC"; 1450 else if (type == IVHD_SPECIAL_HPET) 1451 var = "HPET"; 1452 else 1453 var = "UNKNOWN"; 1454 1455 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n", 1456 var, (int)handle, 1457 PCI_BUS_NUM(devid), 1458 PCI_SLOT(devid), 1459 PCI_FUNC(devid)); 1460 1461 ret = add_special_device(type, handle, &devid, false); 1462 if (ret) 1463 return ret; 1464 1465 /* 1466 * add_special_device might update the devid in case a 1467 * command-line override is present. So call 1468 * set_dev_entry_from_acpi after add_special_device. 1469 */ 1470 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1471 1472 break; 1473 } 1474 case IVHD_DEV_ACPI_HID: { 1475 u16 devid; 1476 u8 hid[ACPIHID_HID_LEN]; 1477 u8 uid[ACPIHID_UID_LEN]; 1478 int ret; 1479 1480 if (h->type != 0x40) { 1481 pr_err(FW_BUG "Invalid IVHD device type %#x\n", 1482 e->type); 1483 break; 1484 } 1485 1486 BUILD_BUG_ON(sizeof(e->ext_hid) != ACPIHID_HID_LEN - 1); 1487 memcpy(hid, &e->ext_hid, ACPIHID_HID_LEN - 1); 1488 hid[ACPIHID_HID_LEN - 1] = '\0'; 1489 1490 if (!(*hid)) { 1491 pr_err(FW_BUG "Invalid HID.\n"); 1492 break; 1493 } 1494 1495 uid[0] = '\0'; 1496 switch (e->uidf) { 1497 case UID_NOT_PRESENT: 1498 1499 if (e->uidl != 0) 1500 pr_warn(FW_BUG "Invalid UID length.\n"); 1501 1502 break; 1503 case UID_IS_INTEGER: 1504 1505 sprintf(uid, "%d", e->uid); 1506 1507 break; 1508 case UID_IS_CHARACTER: 1509 1510 memcpy(uid, &e->uid, e->uidl); 1511 uid[e->uidl] = '\0'; 1512 1513 break; 1514 default: 1515 break; 1516 } 1517 1518 devid = e->devid; 1519 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n", 1520 hid, uid, 1521 PCI_BUS_NUM(devid), 1522 PCI_SLOT(devid), 1523 PCI_FUNC(devid)); 1524 1525 flags = e->flags; 1526 1527 ret = add_acpi_hid_device(hid, uid, &devid, false); 1528 if (ret) 1529 return ret; 1530 1531 /* 1532 * add_special_device might update the devid in case a 1533 * command-line override is present. So call 1534 * set_dev_entry_from_acpi after add_special_device. 1535 */ 1536 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); 1537 1538 break; 1539 } 1540 default: 1541 break; 1542 } 1543 1544 p += ivhd_entry_length(p); 1545 } 1546 1547 return 0; 1548 } 1549 1550 /* Allocate PCI segment data structure */ 1551 static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id, 1552 struct acpi_table_header *ivrs_base) 1553 { 1554 struct amd_iommu_pci_seg *pci_seg; 1555 int last_bdf; 1556 1557 /* 1558 * First parse ACPI tables to find the largest Bus/Dev/Func we need to 1559 * handle in this PCI segment. Upon this information the shared data 1560 * structures for the PCI segments in the system will be allocated. 1561 */ 1562 last_bdf = find_last_devid_acpi(ivrs_base, id); 1563 if (last_bdf < 0) 1564 return NULL; 1565 1566 pci_seg = kzalloc(sizeof(struct amd_iommu_pci_seg), GFP_KERNEL); 1567 if (pci_seg == NULL) 1568 return NULL; 1569 1570 pci_seg->last_bdf = last_bdf; 1571 DUMP_printk("PCI segment : 0x%0x, last bdf : 0x%04x\n", id, last_bdf); 1572 pci_seg->dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); 1573 pci_seg->alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); 1574 pci_seg->rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); 1575 1576 pci_seg->id = id; 1577 init_llist_head(&pci_seg->dev_data_list); 1578 INIT_LIST_HEAD(&pci_seg->unity_map); 1579 list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); 1580 1581 if (alloc_dev_table(pci_seg)) 1582 return NULL; 1583 if (alloc_alias_table(pci_seg)) 1584 return NULL; 1585 if (alloc_rlookup_table(pci_seg)) 1586 return NULL; 1587 1588 return pci_seg; 1589 } 1590 1591 static struct amd_iommu_pci_seg *__init get_pci_segment(u16 id, 1592 struct acpi_table_header *ivrs_base) 1593 { 1594 struct amd_iommu_pci_seg *pci_seg; 1595 1596 for_each_pci_segment(pci_seg) { 1597 if (pci_seg->id == id) 1598 return pci_seg; 1599 } 1600 1601 return alloc_pci_segment(id, ivrs_base); 1602 } 1603 1604 static void __init free_pci_segments(void) 1605 { 1606 struct amd_iommu_pci_seg *pci_seg, *next; 1607 1608 for_each_pci_segment_safe(pci_seg, next) { 1609 list_del(&pci_seg->list); 1610 free_irq_lookup_table(pci_seg); 1611 free_rlookup_table(pci_seg); 1612 free_alias_table(pci_seg); 1613 free_dev_table(pci_seg); 1614 kfree(pci_seg); 1615 } 1616 } 1617 1618 static void __init free_iommu_one(struct amd_iommu *iommu) 1619 { 1620 free_cwwb_sem(iommu); 1621 free_command_buffer(iommu); 1622 free_event_buffer(iommu); 1623 free_ppr_log(iommu); 1624 free_ga_log(iommu); 1625 iommu_unmap_mmio_space(iommu); 1626 } 1627 1628 static void __init free_iommu_all(void) 1629 { 1630 struct amd_iommu *iommu, *next; 1631 1632 for_each_iommu_safe(iommu, next) { 1633 list_del(&iommu->list); 1634 free_iommu_one(iommu); 1635 kfree(iommu); 1636 } 1637 } 1638 1639 /* 1640 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations) 1641 * Workaround: 1642 * BIOS should disable L2B micellaneous clock gating by setting 1643 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b 1644 */ 1645 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) 1646 { 1647 u32 value; 1648 1649 if ((boot_cpu_data.x86 != 0x15) || 1650 (boot_cpu_data.x86_model < 0x10) || 1651 (boot_cpu_data.x86_model > 0x1f)) 1652 return; 1653 1654 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1655 pci_read_config_dword(iommu->dev, 0xf4, &value); 1656 1657 if (value & BIT(2)) 1658 return; 1659 1660 /* Select NB indirect register 0x90 and enable writing */ 1661 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); 1662 1663 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); 1664 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); 1665 1666 /* Clear the enable writing bit */ 1667 pci_write_config_dword(iommu->dev, 0xf0, 0x90); 1668 } 1669 1670 /* 1671 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission) 1672 * Workaround: 1673 * BIOS should enable ATS write permission check by setting 1674 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b 1675 */ 1676 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) 1677 { 1678 u32 value; 1679 1680 if ((boot_cpu_data.x86 != 0x15) || 1681 (boot_cpu_data.x86_model < 0x30) || 1682 (boot_cpu_data.x86_model > 0x3f)) 1683 return; 1684 1685 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */ 1686 value = iommu_read_l2(iommu, 0x47); 1687 1688 if (value & BIT(0)) 1689 return; 1690 1691 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */ 1692 iommu_write_l2(iommu, 0x47, value | BIT(0)); 1693 1694 pci_info(iommu->dev, "Applying ATS write check workaround\n"); 1695 } 1696 1697 /* 1698 * This function glues the initialization function for one IOMMU 1699 * together and also allocates the command buffer and programs the 1700 * hardware. It does NOT enable the IOMMU. This is done afterwards. 1701 */ 1702 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, 1703 struct acpi_table_header *ivrs_base) 1704 { 1705 struct amd_iommu_pci_seg *pci_seg; 1706 int ret; 1707 1708 pci_seg = get_pci_segment(h->pci_seg, ivrs_base); 1709 if (pci_seg == NULL) 1710 return -ENOMEM; 1711 iommu->pci_seg = pci_seg; 1712 1713 raw_spin_lock_init(&iommu->lock); 1714 iommu->cmd_sem_val = 0; 1715 1716 /* Add IOMMU to internal data structures */ 1717 list_add_tail(&iommu->list, &amd_iommu_list); 1718 iommu->index = amd_iommus_present++; 1719 1720 if (unlikely(iommu->index >= MAX_IOMMUS)) { 1721 WARN(1, "System has more IOMMUs than supported by this driver\n"); 1722 return -ENOSYS; 1723 } 1724 1725 /* Index is fine - add IOMMU to the array */ 1726 amd_iommus[iommu->index] = iommu; 1727 1728 /* 1729 * Copy data from ACPI table entry to the iommu struct 1730 */ 1731 iommu->devid = h->devid; 1732 iommu->cap_ptr = h->cap_ptr; 1733 iommu->mmio_phys = h->mmio_phys; 1734 1735 switch (h->type) { 1736 case 0x10: 1737 /* Check if IVHD EFR contains proper max banks/counters */ 1738 if ((h->efr_attr != 0) && 1739 ((h->efr_attr & (0xF << 13)) != 0) && 1740 ((h->efr_attr & (0x3F << 17)) != 0)) 1741 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1742 else 1743 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1744 1745 /* 1746 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1747 * GAM also requires GA mode. Therefore, we need to 1748 * check cmpxchg16b support before enabling it. 1749 */ 1750 if (!boot_cpu_has(X86_FEATURE_CX16) || 1751 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0)) 1752 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1753 break; 1754 case 0x11: 1755 case 0x40: 1756 if (h->efr_reg & (1 << 9)) 1757 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; 1758 else 1759 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; 1760 1761 /* 1762 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports. 1763 * XT, GAM also requires GA mode. Therefore, we need to 1764 * check cmpxchg16b support before enabling them. 1765 */ 1766 if (!boot_cpu_has(X86_FEATURE_CX16) || 1767 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) { 1768 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY; 1769 break; 1770 } 1771 1772 if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) 1773 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE; 1774 1775 early_iommu_features_init(iommu, h); 1776 1777 break; 1778 default: 1779 return -EINVAL; 1780 } 1781 1782 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, 1783 iommu->mmio_phys_end); 1784 if (!iommu->mmio_base) 1785 return -ENOMEM; 1786 1787 if (alloc_cwwb_sem(iommu)) 1788 return -ENOMEM; 1789 1790 if (alloc_command_buffer(iommu)) 1791 return -ENOMEM; 1792 1793 if (alloc_event_buffer(iommu)) 1794 return -ENOMEM; 1795 1796 iommu->int_enabled = false; 1797 1798 init_translation_status(iommu); 1799 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { 1800 iommu_disable(iommu); 1801 clear_translation_pre_enabled(iommu); 1802 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", 1803 iommu->index); 1804 } 1805 if (amd_iommu_pre_enabled) 1806 amd_iommu_pre_enabled = translation_pre_enabled(iommu); 1807 1808 ret = init_iommu_from_acpi(iommu, h); 1809 if (ret) 1810 return ret; 1811 1812 if (amd_iommu_irq_remap) { 1813 ret = amd_iommu_create_irq_domain(iommu); 1814 if (ret) 1815 return ret; 1816 } 1817 1818 /* 1819 * Make sure IOMMU is not considered to translate itself. The IVRS 1820 * table tells us so, but this is a lie! 1821 */ 1822 pci_seg->rlookup_table[iommu->devid] = NULL; 1823 1824 return 0; 1825 } 1826 1827 /** 1828 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type 1829 * @ivrs: Pointer to the IVRS header 1830 * 1831 * This function search through all IVDB of the maximum supported IVHD 1832 */ 1833 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs) 1834 { 1835 u8 *base = (u8 *)ivrs; 1836 struct ivhd_header *ivhd = (struct ivhd_header *) 1837 (base + IVRS_HEADER_LENGTH); 1838 u8 last_type = ivhd->type; 1839 u16 devid = ivhd->devid; 1840 1841 while (((u8 *)ivhd - base < ivrs->length) && 1842 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) { 1843 u8 *p = (u8 *) ivhd; 1844 1845 if (ivhd->devid == devid) 1846 last_type = ivhd->type; 1847 ivhd = (struct ivhd_header *)(p + ivhd->length); 1848 } 1849 1850 return last_type; 1851 } 1852 1853 /* 1854 * Iterates over all IOMMU entries in the ACPI table, allocates the 1855 * IOMMU structure and initializes it with init_iommu_one() 1856 */ 1857 static int __init init_iommu_all(struct acpi_table_header *table) 1858 { 1859 u8 *p = (u8 *)table, *end = (u8 *)table; 1860 struct ivhd_header *h; 1861 struct amd_iommu *iommu; 1862 int ret; 1863 1864 end += table->length; 1865 p += IVRS_HEADER_LENGTH; 1866 1867 while (p < end) { 1868 h = (struct ivhd_header *)p; 1869 if (*p == amd_iommu_target_ivhd_type) { 1870 1871 DUMP_printk("device: %02x:%02x.%01x cap: %04x " 1872 "seg: %d flags: %01x info %04x\n", 1873 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid), 1874 PCI_FUNC(h->devid), h->cap_ptr, 1875 h->pci_seg, h->flags, h->info); 1876 DUMP_printk(" mmio-addr: %016llx\n", 1877 h->mmio_phys); 1878 1879 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); 1880 if (iommu == NULL) 1881 return -ENOMEM; 1882 1883 ret = init_iommu_one(iommu, h, table); 1884 if (ret) 1885 return ret; 1886 } 1887 p += h->length; 1888 1889 } 1890 WARN_ON(p != end); 1891 1892 return 0; 1893 } 1894 1895 static void init_iommu_perf_ctr(struct amd_iommu *iommu) 1896 { 1897 u64 val; 1898 struct pci_dev *pdev = iommu->dev; 1899 1900 if (!iommu_feature(iommu, FEATURE_PC)) 1901 return; 1902 1903 amd_iommu_pc_present = true; 1904 1905 pci_info(pdev, "IOMMU performance counters supported\n"); 1906 1907 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); 1908 iommu->max_banks = (u8) ((val >> 12) & 0x3f); 1909 iommu->max_counters = (u8) ((val >> 7) & 0xf); 1910 1911 return; 1912 } 1913 1914 static ssize_t amd_iommu_show_cap(struct device *dev, 1915 struct device_attribute *attr, 1916 char *buf) 1917 { 1918 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1919 return sprintf(buf, "%x\n", iommu->cap); 1920 } 1921 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL); 1922 1923 static ssize_t amd_iommu_show_features(struct device *dev, 1924 struct device_attribute *attr, 1925 char *buf) 1926 { 1927 struct amd_iommu *iommu = dev_to_amd_iommu(dev); 1928 return sprintf(buf, "%llx\n", iommu->features); 1929 } 1930 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL); 1931 1932 static struct attribute *amd_iommu_attrs[] = { 1933 &dev_attr_cap.attr, 1934 &dev_attr_features.attr, 1935 NULL, 1936 }; 1937 1938 static struct attribute_group amd_iommu_group = { 1939 .name = "amd-iommu", 1940 .attrs = amd_iommu_attrs, 1941 }; 1942 1943 static const struct attribute_group *amd_iommu_groups[] = { 1944 &amd_iommu_group, 1945 NULL, 1946 }; 1947 1948 /* 1949 * Note: IVHD 0x11 and 0x40 also contains exact copy 1950 * of the IOMMU Extended Feature Register [MMIO Offset 0030h]. 1951 * Default to EFR in IVHD since it is available sooner (i.e. before PCI init). 1952 */ 1953 static void __init late_iommu_features_init(struct amd_iommu *iommu) 1954 { 1955 u64 features; 1956 1957 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) 1958 return; 1959 1960 /* read extended feature bits */ 1961 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); 1962 1963 if (!iommu->features) { 1964 iommu->features = features; 1965 return; 1966 } 1967 1968 /* 1969 * Sanity check and warn if EFR values from 1970 * IVHD and MMIO conflict. 1971 */ 1972 if (features != iommu->features) 1973 pr_warn(FW_WARN "EFR mismatch. Use IVHD EFR (%#llx : %#llx).\n", 1974 features, iommu->features); 1975 } 1976 1977 static int __init iommu_init_pci(struct amd_iommu *iommu) 1978 { 1979 int cap_ptr = iommu->cap_ptr; 1980 int ret; 1981 1982 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), 1983 iommu->devid & 0xff); 1984 if (!iommu->dev) 1985 return -ENODEV; 1986 1987 /* Prevent binding other PCI device drivers to IOMMU devices */ 1988 iommu->dev->match_driver = false; 1989 1990 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, 1991 &iommu->cap); 1992 1993 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) 1994 amd_iommu_iotlb_sup = false; 1995 1996 late_iommu_features_init(iommu); 1997 1998 if (iommu_feature(iommu, FEATURE_GT)) { 1999 int glxval; 2000 u32 max_pasid; 2001 u64 pasmax; 2002 2003 pasmax = iommu->features & FEATURE_PASID_MASK; 2004 pasmax >>= FEATURE_PASID_SHIFT; 2005 max_pasid = (1 << (pasmax + 1)) - 1; 2006 2007 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid); 2008 2009 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK); 2010 2011 glxval = iommu->features & FEATURE_GLXVAL_MASK; 2012 glxval >>= FEATURE_GLXVAL_SHIFT; 2013 2014 if (amd_iommu_max_glx_val == -1) 2015 amd_iommu_max_glx_val = glxval; 2016 else 2017 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval); 2018 } 2019 2020 if (iommu_feature(iommu, FEATURE_GT) && 2021 iommu_feature(iommu, FEATURE_PPR)) { 2022 iommu->is_iommu_v2 = true; 2023 amd_iommu_v2_present = true; 2024 } 2025 2026 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) 2027 return -ENOMEM; 2028 2029 ret = iommu_init_ga_log(iommu); 2030 if (ret) 2031 return ret; 2032 2033 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { 2034 pr_info("Using strict mode due to virtualization\n"); 2035 iommu_set_dma_strict(); 2036 amd_iommu_np_cache = true; 2037 } 2038 2039 init_iommu_perf_ctr(iommu); 2040 2041 if (is_rd890_iommu(iommu->dev)) { 2042 int i, j; 2043 2044 iommu->root_pdev = 2045 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, 2046 PCI_DEVFN(0, 0)); 2047 2048 /* 2049 * Some rd890 systems may not be fully reconfigured by the 2050 * BIOS, so it's necessary for us to store this information so 2051 * it can be reprogrammed on resume 2052 */ 2053 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, 2054 &iommu->stored_addr_lo); 2055 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, 2056 &iommu->stored_addr_hi); 2057 2058 /* Low bit locks writes to configuration space */ 2059 iommu->stored_addr_lo &= ~1; 2060 2061 for (i = 0; i < 6; i++) 2062 for (j = 0; j < 0x12; j++) 2063 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); 2064 2065 for (i = 0; i < 0x83; i++) 2066 iommu->stored_l2[i] = iommu_read_l2(iommu, i); 2067 } 2068 2069 amd_iommu_erratum_746_workaround(iommu); 2070 amd_iommu_ats_write_check_workaround(iommu); 2071 2072 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, 2073 amd_iommu_groups, "ivhd%d", iommu->index); 2074 if (ret) 2075 return ret; 2076 2077 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); 2078 2079 return pci_enable_device(iommu->dev); 2080 } 2081 2082 static void print_iommu_info(void) 2083 { 2084 static const char * const feat_str[] = { 2085 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", 2086 "IA", "GA", "HE", "PC" 2087 }; 2088 struct amd_iommu *iommu; 2089 2090 for_each_iommu(iommu) { 2091 struct pci_dev *pdev = iommu->dev; 2092 int i; 2093 2094 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr); 2095 2096 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { 2097 pr_info("Extended features (%#llx):", iommu->features); 2098 2099 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { 2100 if (iommu_feature(iommu, (1ULL << i))) 2101 pr_cont(" %s", feat_str[i]); 2102 } 2103 2104 if (iommu->features & FEATURE_GAM_VAPIC) 2105 pr_cont(" GA_vAPIC"); 2106 2107 pr_cont("\n"); 2108 } 2109 } 2110 if (irq_remapping_enabled) { 2111 pr_info("Interrupt remapping enabled\n"); 2112 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2113 pr_info("Virtual APIC enabled\n"); 2114 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2115 pr_info("X2APIC enabled\n"); 2116 } 2117 } 2118 2119 static int __init amd_iommu_init_pci(void) 2120 { 2121 struct amd_iommu *iommu; 2122 struct amd_iommu_pci_seg *pci_seg; 2123 int ret; 2124 2125 for_each_iommu(iommu) { 2126 ret = iommu_init_pci(iommu); 2127 if (ret) { 2128 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", 2129 iommu->index, ret); 2130 goto out; 2131 } 2132 /* Need to setup range after PCI init */ 2133 iommu_set_cwwb_range(iommu); 2134 } 2135 2136 /* 2137 * Order is important here to make sure any unity map requirements are 2138 * fulfilled. The unity mappings are created and written to the device 2139 * table during the amd_iommu_init_api() call. 2140 * 2141 * After that we call init_device_table_dma() to make sure any 2142 * uninitialized DTE will block DMA, and in the end we flush the caches 2143 * of all IOMMUs to make sure the changes to the device table are 2144 * active. 2145 */ 2146 ret = amd_iommu_init_api(); 2147 if (ret) { 2148 pr_err("IOMMU: Failed to initialize IOMMU-API interface (error=%d)!\n", 2149 ret); 2150 goto out; 2151 } 2152 2153 for_each_pci_segment(pci_seg) 2154 init_device_table_dma(pci_seg); 2155 2156 for_each_iommu(iommu) 2157 iommu_flush_all_caches(iommu); 2158 2159 print_iommu_info(); 2160 2161 out: 2162 return ret; 2163 } 2164 2165 /**************************************************************************** 2166 * 2167 * The following functions initialize the MSI interrupts for all IOMMUs 2168 * in the system. It's a bit challenging because there could be multiple 2169 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per 2170 * pci_dev. 2171 * 2172 ****************************************************************************/ 2173 2174 static int iommu_setup_msi(struct amd_iommu *iommu) 2175 { 2176 int r; 2177 2178 r = pci_enable_msi(iommu->dev); 2179 if (r) 2180 return r; 2181 2182 r = request_threaded_irq(iommu->dev->irq, 2183 amd_iommu_int_handler, 2184 amd_iommu_int_thread, 2185 0, "AMD-Vi", 2186 iommu); 2187 2188 if (r) { 2189 pci_disable_msi(iommu->dev); 2190 return r; 2191 } 2192 2193 return 0; 2194 } 2195 2196 union intcapxt { 2197 u64 capxt; 2198 struct { 2199 u64 reserved_0 : 2, 2200 dest_mode_logical : 1, 2201 reserved_1 : 5, 2202 destid_0_23 : 24, 2203 vector : 8, 2204 reserved_2 : 16, 2205 destid_24_31 : 8; 2206 }; 2207 } __attribute__ ((packed)); 2208 2209 2210 static struct irq_chip intcapxt_controller; 2211 2212 static int intcapxt_irqdomain_activate(struct irq_domain *domain, 2213 struct irq_data *irqd, bool reserve) 2214 { 2215 return 0; 2216 } 2217 2218 static void intcapxt_irqdomain_deactivate(struct irq_domain *domain, 2219 struct irq_data *irqd) 2220 { 2221 } 2222 2223 2224 static int intcapxt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, 2225 unsigned int nr_irqs, void *arg) 2226 { 2227 struct irq_alloc_info *info = arg; 2228 int i, ret; 2229 2230 if (!info || info->type != X86_IRQ_ALLOC_TYPE_AMDVI) 2231 return -EINVAL; 2232 2233 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 2234 if (ret < 0) 2235 return ret; 2236 2237 for (i = virq; i < virq + nr_irqs; i++) { 2238 struct irq_data *irqd = irq_domain_get_irq_data(domain, i); 2239 2240 irqd->chip = &intcapxt_controller; 2241 irqd->chip_data = info->data; 2242 __irq_set_handler(i, handle_edge_irq, 0, "edge"); 2243 } 2244 2245 return ret; 2246 } 2247 2248 static void intcapxt_irqdomain_free(struct irq_domain *domain, unsigned int virq, 2249 unsigned int nr_irqs) 2250 { 2251 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2252 } 2253 2254 2255 static void intcapxt_unmask_irq(struct irq_data *irqd) 2256 { 2257 struct amd_iommu *iommu = irqd->chip_data; 2258 struct irq_cfg *cfg = irqd_cfg(irqd); 2259 union intcapxt xt; 2260 2261 xt.capxt = 0ULL; 2262 xt.dest_mode_logical = apic->dest_mode_logical; 2263 xt.vector = cfg->vector; 2264 xt.destid_0_23 = cfg->dest_apicid & GENMASK(23, 0); 2265 xt.destid_24_31 = cfg->dest_apicid >> 24; 2266 2267 /** 2268 * Current IOMMU implementation uses the same IRQ for all 2269 * 3 IOMMU interrupts. 2270 */ 2271 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); 2272 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); 2273 writeq(xt.capxt, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); 2274 } 2275 2276 static void intcapxt_mask_irq(struct irq_data *irqd) 2277 { 2278 struct amd_iommu *iommu = irqd->chip_data; 2279 2280 writeq(0, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); 2281 writeq(0, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); 2282 writeq(0, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); 2283 } 2284 2285 2286 static int intcapxt_set_affinity(struct irq_data *irqd, 2287 const struct cpumask *mask, bool force) 2288 { 2289 struct irq_data *parent = irqd->parent_data; 2290 int ret; 2291 2292 ret = parent->chip->irq_set_affinity(parent, mask, force); 2293 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) 2294 return ret; 2295 return 0; 2296 } 2297 2298 static int intcapxt_set_wake(struct irq_data *irqd, unsigned int on) 2299 { 2300 return on ? -EOPNOTSUPP : 0; 2301 } 2302 2303 static struct irq_chip intcapxt_controller = { 2304 .name = "IOMMU-MSI", 2305 .irq_unmask = intcapxt_unmask_irq, 2306 .irq_mask = intcapxt_mask_irq, 2307 .irq_ack = irq_chip_ack_parent, 2308 .irq_retrigger = irq_chip_retrigger_hierarchy, 2309 .irq_set_affinity = intcapxt_set_affinity, 2310 .irq_set_wake = intcapxt_set_wake, 2311 .flags = IRQCHIP_MASK_ON_SUSPEND, 2312 }; 2313 2314 static const struct irq_domain_ops intcapxt_domain_ops = { 2315 .alloc = intcapxt_irqdomain_alloc, 2316 .free = intcapxt_irqdomain_free, 2317 .activate = intcapxt_irqdomain_activate, 2318 .deactivate = intcapxt_irqdomain_deactivate, 2319 }; 2320 2321 2322 static struct irq_domain *iommu_irqdomain; 2323 2324 static struct irq_domain *iommu_get_irqdomain(void) 2325 { 2326 struct fwnode_handle *fn; 2327 2328 /* No need for locking here (yet) as the init is single-threaded */ 2329 if (iommu_irqdomain) 2330 return iommu_irqdomain; 2331 2332 fn = irq_domain_alloc_named_fwnode("AMD-Vi-MSI"); 2333 if (!fn) 2334 return NULL; 2335 2336 iommu_irqdomain = irq_domain_create_hierarchy(x86_vector_domain, 0, 0, 2337 fn, &intcapxt_domain_ops, 2338 NULL); 2339 if (!iommu_irqdomain) 2340 irq_domain_free_fwnode(fn); 2341 2342 return iommu_irqdomain; 2343 } 2344 2345 static int iommu_setup_intcapxt(struct amd_iommu *iommu) 2346 { 2347 struct irq_domain *domain; 2348 struct irq_alloc_info info; 2349 int irq, ret; 2350 2351 domain = iommu_get_irqdomain(); 2352 if (!domain) 2353 return -ENXIO; 2354 2355 init_irq_alloc_info(&info, NULL); 2356 info.type = X86_IRQ_ALLOC_TYPE_AMDVI; 2357 info.data = iommu; 2358 2359 irq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); 2360 if (irq < 0) { 2361 irq_domain_remove(domain); 2362 return irq; 2363 } 2364 2365 ret = request_threaded_irq(irq, amd_iommu_int_handler, 2366 amd_iommu_int_thread, 0, "AMD-Vi", iommu); 2367 if (ret) { 2368 irq_domain_free_irqs(irq, 1); 2369 irq_domain_remove(domain); 2370 return ret; 2371 } 2372 2373 return 0; 2374 } 2375 2376 static int iommu_init_irq(struct amd_iommu *iommu) 2377 { 2378 int ret; 2379 2380 if (iommu->int_enabled) 2381 goto enable_faults; 2382 2383 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2384 ret = iommu_setup_intcapxt(iommu); 2385 else if (iommu->dev->msi_cap) 2386 ret = iommu_setup_msi(iommu); 2387 else 2388 ret = -ENODEV; 2389 2390 if (ret) 2391 return ret; 2392 2393 iommu->int_enabled = true; 2394 enable_faults: 2395 2396 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE) 2397 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); 2398 2399 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); 2400 2401 if (iommu->ppr_log != NULL) 2402 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); 2403 2404 iommu_ga_log_enable(iommu); 2405 2406 return 0; 2407 } 2408 2409 /**************************************************************************** 2410 * 2411 * The next functions belong to the third pass of parsing the ACPI 2412 * table. In this last pass the memory mapping requirements are 2413 * gathered (like exclusion and unity mapping ranges). 2414 * 2415 ****************************************************************************/ 2416 2417 static void __init free_unity_maps(void) 2418 { 2419 struct unity_map_entry *entry, *next; 2420 struct amd_iommu_pci_seg *p, *pci_seg; 2421 2422 for_each_pci_segment_safe(pci_seg, p) { 2423 list_for_each_entry_safe(entry, next, &pci_seg->unity_map, list) { 2424 list_del(&entry->list); 2425 kfree(entry); 2426 } 2427 } 2428 } 2429 2430 /* called for unity map ACPI definition */ 2431 static int __init init_unity_map_range(struct ivmd_header *m, 2432 struct acpi_table_header *ivrs_base) 2433 { 2434 struct unity_map_entry *e = NULL; 2435 struct amd_iommu_pci_seg *pci_seg; 2436 char *s; 2437 2438 pci_seg = get_pci_segment(m->pci_seg, ivrs_base); 2439 if (pci_seg == NULL) 2440 return -ENOMEM; 2441 2442 e = kzalloc(sizeof(*e), GFP_KERNEL); 2443 if (e == NULL) 2444 return -ENOMEM; 2445 2446 switch (m->type) { 2447 default: 2448 kfree(e); 2449 return 0; 2450 case ACPI_IVMD_TYPE: 2451 s = "IVMD_TYPEi\t\t\t"; 2452 e->devid_start = e->devid_end = m->devid; 2453 break; 2454 case ACPI_IVMD_TYPE_ALL: 2455 s = "IVMD_TYPE_ALL\t\t"; 2456 e->devid_start = 0; 2457 e->devid_end = amd_iommu_last_bdf; 2458 break; 2459 case ACPI_IVMD_TYPE_RANGE: 2460 s = "IVMD_TYPE_RANGE\t\t"; 2461 e->devid_start = m->devid; 2462 e->devid_end = m->aux; 2463 break; 2464 } 2465 e->address_start = PAGE_ALIGN(m->range_start); 2466 e->address_end = e->address_start + PAGE_ALIGN(m->range_length); 2467 e->prot = m->flags >> 1; 2468 2469 /* 2470 * Treat per-device exclusion ranges as r/w unity-mapped regions 2471 * since some buggy BIOSes might lead to the overwritten exclusion 2472 * range (exclusion_start and exclusion_length members). This 2473 * happens when there are multiple exclusion ranges (IVMD entries) 2474 * defined in ACPI table. 2475 */ 2476 if (m->flags & IVMD_FLAG_EXCL_RANGE) 2477 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; 2478 2479 DUMP_printk("%s devid_start: %04x:%02x:%02x.%x devid_end: " 2480 "%04x:%02x:%02x.%x range_start: %016llx range_end: %016llx" 2481 " flags: %x\n", s, m->pci_seg, 2482 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start), 2483 PCI_FUNC(e->devid_start), m->pci_seg, 2484 PCI_BUS_NUM(e->devid_end), 2485 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), 2486 e->address_start, e->address_end, m->flags); 2487 2488 list_add_tail(&e->list, &pci_seg->unity_map); 2489 2490 return 0; 2491 } 2492 2493 /* iterates over all memory definitions we find in the ACPI table */ 2494 static int __init init_memory_definitions(struct acpi_table_header *table) 2495 { 2496 u8 *p = (u8 *)table, *end = (u8 *)table; 2497 struct ivmd_header *m; 2498 2499 end += table->length; 2500 p += IVRS_HEADER_LENGTH; 2501 2502 while (p < end) { 2503 m = (struct ivmd_header *)p; 2504 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) 2505 init_unity_map_range(m, table); 2506 2507 p += m->length; 2508 } 2509 2510 return 0; 2511 } 2512 2513 /* 2514 * Init the device table to not allow DMA access for devices 2515 */ 2516 static void init_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2517 { 2518 u32 devid; 2519 struct dev_table_entry *dev_table = pci_seg->dev_table; 2520 2521 if (dev_table == NULL) 2522 return; 2523 2524 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2525 set_dev_entry_bit(devid, DEV_ENTRY_VALID); 2526 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); 2527 } 2528 } 2529 2530 static void __init uninit_device_table_dma(struct amd_iommu_pci_seg *pci_seg) 2531 { 2532 u32 devid; 2533 struct dev_table_entry *dev_table = pci_seg->dev_table; 2534 2535 if (dev_table == NULL) 2536 return; 2537 2538 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { 2539 dev_table[devid].data[0] = 0ULL; 2540 dev_table[devid].data[1] = 0ULL; 2541 } 2542 } 2543 2544 static void init_device_table(void) 2545 { 2546 u32 devid; 2547 2548 if (!amd_iommu_irq_remap) 2549 return; 2550 2551 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) 2552 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN); 2553 } 2554 2555 static void iommu_init_flags(struct amd_iommu *iommu) 2556 { 2557 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? 2558 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : 2559 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); 2560 2561 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? 2562 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : 2563 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); 2564 2565 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? 2566 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : 2567 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); 2568 2569 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? 2570 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : 2571 iommu_feature_disable(iommu, CONTROL_ISOC_EN); 2572 2573 /* 2574 * make IOMMU memory accesses cache coherent 2575 */ 2576 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); 2577 2578 /* Set IOTLB invalidation timeout to 1s */ 2579 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); 2580 } 2581 2582 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) 2583 { 2584 int i, j; 2585 u32 ioc_feature_control; 2586 struct pci_dev *pdev = iommu->root_pdev; 2587 2588 /* RD890 BIOSes may not have completely reconfigured the iommu */ 2589 if (!is_rd890_iommu(iommu->dev) || !pdev) 2590 return; 2591 2592 /* 2593 * First, we need to ensure that the iommu is enabled. This is 2594 * controlled by a register in the northbridge 2595 */ 2596 2597 /* Select Northbridge indirect register 0x75 and enable writing */ 2598 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); 2599 pci_read_config_dword(pdev, 0x64, &ioc_feature_control); 2600 2601 /* Enable the iommu */ 2602 if (!(ioc_feature_control & 0x1)) 2603 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); 2604 2605 /* Restore the iommu BAR */ 2606 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2607 iommu->stored_addr_lo); 2608 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, 2609 iommu->stored_addr_hi); 2610 2611 /* Restore the l1 indirect regs for each of the 6 l1s */ 2612 for (i = 0; i < 6; i++) 2613 for (j = 0; j < 0x12; j++) 2614 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); 2615 2616 /* Restore the l2 indirect regs */ 2617 for (i = 0; i < 0x83; i++) 2618 iommu_write_l2(iommu, i, iommu->stored_l2[i]); 2619 2620 /* Lock PCI setup registers */ 2621 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, 2622 iommu->stored_addr_lo | 1); 2623 } 2624 2625 static void iommu_enable_ga(struct amd_iommu *iommu) 2626 { 2627 #ifdef CONFIG_IRQ_REMAP 2628 switch (amd_iommu_guest_ir) { 2629 case AMD_IOMMU_GUEST_IR_VAPIC: 2630 iommu_feature_enable(iommu, CONTROL_GAM_EN); 2631 fallthrough; 2632 case AMD_IOMMU_GUEST_IR_LEGACY_GA: 2633 iommu_feature_enable(iommu, CONTROL_GA_EN); 2634 iommu->irte_ops = &irte_128_ops; 2635 break; 2636 default: 2637 iommu->irte_ops = &irte_32_ops; 2638 break; 2639 } 2640 #endif 2641 } 2642 2643 static void early_enable_iommu(struct amd_iommu *iommu) 2644 { 2645 iommu_disable(iommu); 2646 iommu_init_flags(iommu); 2647 iommu_set_device_table(iommu); 2648 iommu_enable_command_buffer(iommu); 2649 iommu_enable_event_buffer(iommu); 2650 iommu_set_exclusion_range(iommu); 2651 iommu_enable_ga(iommu); 2652 iommu_enable_xt(iommu); 2653 iommu_enable(iommu); 2654 iommu_flush_all_caches(iommu); 2655 } 2656 2657 /* 2658 * This function finally enables all IOMMUs found in the system after 2659 * they have been initialized. 2660 * 2661 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy 2662 * the old content of device table entries. Not this case or copy failed, 2663 * just continue as normal kernel does. 2664 */ 2665 static void early_enable_iommus(void) 2666 { 2667 struct amd_iommu *iommu; 2668 struct amd_iommu_pci_seg *pci_seg; 2669 2670 if (!copy_device_table()) { 2671 /* 2672 * If come here because of failure in copying device table from old 2673 * kernel with all IOMMUs enabled, print error message and try to 2674 * free allocated old_dev_tbl_cpy. 2675 */ 2676 if (amd_iommu_pre_enabled) 2677 pr_err("Failed to copy DEV table from previous kernel.\n"); 2678 2679 for_each_pci_segment(pci_seg) { 2680 if (pci_seg->old_dev_tbl_cpy != NULL) { 2681 free_pages((unsigned long)pci_seg->old_dev_tbl_cpy, 2682 get_order(pci_seg->dev_table_size)); 2683 pci_seg->old_dev_tbl_cpy = NULL; 2684 } 2685 } 2686 2687 for_each_iommu(iommu) { 2688 clear_translation_pre_enabled(iommu); 2689 early_enable_iommu(iommu); 2690 } 2691 } else { 2692 pr_info("Copied DEV table from previous kernel.\n"); 2693 2694 for_each_pci_segment(pci_seg) { 2695 free_pages((unsigned long)pci_seg->dev_table, 2696 get_order(pci_seg->dev_table_size)); 2697 pci_seg->dev_table = pci_seg->old_dev_tbl_cpy; 2698 } 2699 2700 for_each_iommu(iommu) { 2701 iommu_disable_command_buffer(iommu); 2702 iommu_disable_event_buffer(iommu); 2703 iommu_enable_command_buffer(iommu); 2704 iommu_enable_event_buffer(iommu); 2705 iommu_enable_ga(iommu); 2706 iommu_enable_xt(iommu); 2707 iommu_set_device_table(iommu); 2708 iommu_flush_all_caches(iommu); 2709 } 2710 } 2711 2712 #ifdef CONFIG_IRQ_REMAP 2713 /* 2714 * Note: We have already checked GASup from IVRS table. 2715 * Now, we need to make sure that GAMSup is set. 2716 */ 2717 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && 2718 !check_feature_on_all_iommus(FEATURE_GAM_VAPIC)) 2719 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 2720 2721 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2722 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); 2723 #endif 2724 } 2725 2726 static void enable_iommus_v2(void) 2727 { 2728 struct amd_iommu *iommu; 2729 2730 for_each_iommu(iommu) { 2731 iommu_enable_ppr_log(iommu); 2732 iommu_enable_gt(iommu); 2733 } 2734 } 2735 2736 static void enable_iommus(void) 2737 { 2738 early_enable_iommus(); 2739 2740 enable_iommus_v2(); 2741 } 2742 2743 static void disable_iommus(void) 2744 { 2745 struct amd_iommu *iommu; 2746 2747 for_each_iommu(iommu) 2748 iommu_disable(iommu); 2749 2750 #ifdef CONFIG_IRQ_REMAP 2751 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) 2752 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); 2753 #endif 2754 } 2755 2756 /* 2757 * Suspend/Resume support 2758 * disable suspend until real resume implemented 2759 */ 2760 2761 static void amd_iommu_resume(void) 2762 { 2763 struct amd_iommu *iommu; 2764 2765 for_each_iommu(iommu) 2766 iommu_apply_resume_quirks(iommu); 2767 2768 /* re-load the hardware */ 2769 enable_iommus(); 2770 2771 amd_iommu_enable_interrupts(); 2772 } 2773 2774 static int amd_iommu_suspend(void) 2775 { 2776 /* disable IOMMUs to go out of the way for BIOS */ 2777 disable_iommus(); 2778 2779 return 0; 2780 } 2781 2782 static struct syscore_ops amd_iommu_syscore_ops = { 2783 .suspend = amd_iommu_suspend, 2784 .resume = amd_iommu_resume, 2785 }; 2786 2787 static void __init free_iommu_resources(void) 2788 { 2789 kmem_cache_destroy(amd_iommu_irq_cache); 2790 amd_iommu_irq_cache = NULL; 2791 2792 free_pages((unsigned long)amd_iommu_alias_table, 2793 get_order(alias_table_size)); 2794 amd_iommu_alias_table = NULL; 2795 2796 free_pages((unsigned long)amd_iommu_dev_table, 2797 get_order(dev_table_size)); 2798 amd_iommu_dev_table = NULL; 2799 2800 free_iommu_all(); 2801 free_pci_segments(); 2802 } 2803 2804 /* SB IOAPIC is always on this device in AMD systems */ 2805 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0)) 2806 2807 static bool __init check_ioapic_information(void) 2808 { 2809 const char *fw_bug = FW_BUG; 2810 bool ret, has_sb_ioapic; 2811 int idx; 2812 2813 has_sb_ioapic = false; 2814 ret = false; 2815 2816 /* 2817 * If we have map overrides on the kernel command line the 2818 * messages in this function might not describe firmware bugs 2819 * anymore - so be careful 2820 */ 2821 if (cmdline_maps) 2822 fw_bug = ""; 2823 2824 for (idx = 0; idx < nr_ioapics; idx++) { 2825 int devid, id = mpc_ioapic_id(idx); 2826 2827 devid = get_ioapic_devid(id); 2828 if (devid < 0) { 2829 pr_err("%s: IOAPIC[%d] not in IVRS table\n", 2830 fw_bug, id); 2831 ret = false; 2832 } else if (devid == IOAPIC_SB_DEVID) { 2833 has_sb_ioapic = true; 2834 ret = true; 2835 } 2836 } 2837 2838 if (!has_sb_ioapic) { 2839 /* 2840 * We expect the SB IOAPIC to be listed in the IVRS 2841 * table. The system timer is connected to the SB IOAPIC 2842 * and if we don't have it in the list the system will 2843 * panic at boot time. This situation usually happens 2844 * when the BIOS is buggy and provides us the wrong 2845 * device id for the IOAPIC in the system. 2846 */ 2847 pr_err("%s: No southbridge IOAPIC found\n", fw_bug); 2848 } 2849 2850 if (!ret) 2851 pr_err("Disabling interrupt remapping\n"); 2852 2853 return ret; 2854 } 2855 2856 static void __init free_dma_resources(void) 2857 { 2858 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 2859 get_order(MAX_DOMAIN_ID/8)); 2860 amd_iommu_pd_alloc_bitmap = NULL; 2861 2862 free_unity_maps(); 2863 } 2864 2865 static void __init ivinfo_init(void *ivrs) 2866 { 2867 amd_iommu_ivinfo = *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); 2868 } 2869 2870 /* 2871 * This is the hardware init function for AMD IOMMU in the system. 2872 * This function is called either from amd_iommu_init or from the interrupt 2873 * remapping setup code. 2874 * 2875 * This function basically parses the ACPI table for AMD IOMMU (IVRS) 2876 * four times: 2877 * 2878 * 1 pass) Discover the most comprehensive IVHD type to use. 2879 * 2880 * 2 pass) Find the highest PCI device id the driver has to handle. 2881 * Upon this information the size of the data structures is 2882 * determined that needs to be allocated. 2883 * 2884 * 3 pass) Initialize the data structures just allocated with the 2885 * information in the ACPI table about available AMD IOMMUs 2886 * in the system. It also maps the PCI devices in the 2887 * system to specific IOMMUs 2888 * 2889 * 4 pass) After the basic data structures are allocated and 2890 * initialized we update them with information about memory 2891 * remapping requirements parsed out of the ACPI table in 2892 * this last pass. 2893 * 2894 * After everything is set up the IOMMUs are enabled and the necessary 2895 * hotplug and suspend notifiers are registered. 2896 */ 2897 static int __init early_amd_iommu_init(void) 2898 { 2899 struct acpi_table_header *ivrs_base; 2900 int remap_cache_sz, ret; 2901 acpi_status status; 2902 2903 if (!amd_iommu_detected) 2904 return -ENODEV; 2905 2906 status = acpi_get_table("IVRS", 0, &ivrs_base); 2907 if (status == AE_NOT_FOUND) 2908 return -ENODEV; 2909 else if (ACPI_FAILURE(status)) { 2910 const char *err = acpi_format_exception(status); 2911 pr_err("IVRS table error: %s\n", err); 2912 return -EINVAL; 2913 } 2914 2915 /* 2916 * Validate checksum here so we don't need to do it when 2917 * we actually parse the table 2918 */ 2919 ret = check_ivrs_checksum(ivrs_base); 2920 if (ret) 2921 goto out; 2922 2923 ivinfo_init(ivrs_base); 2924 2925 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base); 2926 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); 2927 2928 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); 2929 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); 2930 2931 /* Device table - directly used by all IOMMUs */ 2932 ret = -ENOMEM; 2933 amd_iommu_dev_table = (void *)__get_free_pages( 2934 GFP_KERNEL | __GFP_ZERO | GFP_DMA32, 2935 get_order(dev_table_size)); 2936 if (amd_iommu_dev_table == NULL) 2937 goto out; 2938 2939 /* 2940 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the 2941 * IOMMU see for that device 2942 */ 2943 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, 2944 get_order(alias_table_size)); 2945 if (amd_iommu_alias_table == NULL) 2946 goto out; 2947 2948 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( 2949 GFP_KERNEL | __GFP_ZERO, 2950 get_order(MAX_DOMAIN_ID/8)); 2951 if (amd_iommu_pd_alloc_bitmap == NULL) 2952 goto out; 2953 2954 /* 2955 * never allocate domain 0 because its used as the non-allocated and 2956 * error value placeholder 2957 */ 2958 __set_bit(0, amd_iommu_pd_alloc_bitmap); 2959 2960 /* 2961 * now the data structures are allocated and basically initialized 2962 * start the real acpi table scan 2963 */ 2964 ret = init_iommu_all(ivrs_base); 2965 if (ret) 2966 goto out; 2967 2968 /* Disable any previously enabled IOMMUs */ 2969 if (!is_kdump_kernel() || amd_iommu_disabled) 2970 disable_iommus(); 2971 2972 if (amd_iommu_irq_remap) 2973 amd_iommu_irq_remap = check_ioapic_information(); 2974 2975 if (amd_iommu_irq_remap) { 2976 struct amd_iommu_pci_seg *pci_seg; 2977 /* 2978 * Interrupt remapping enabled, create kmem_cache for the 2979 * remapping tables. 2980 */ 2981 ret = -ENOMEM; 2982 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) 2983 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32); 2984 else 2985 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2); 2986 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache", 2987 remap_cache_sz, 2988 DTE_INTTAB_ALIGNMENT, 2989 0, NULL); 2990 if (!amd_iommu_irq_cache) 2991 goto out; 2992 2993 for_each_pci_segment(pci_seg) { 2994 if (alloc_irq_lookup_table(pci_seg)) 2995 goto out; 2996 } 2997 } 2998 2999 ret = init_memory_definitions(ivrs_base); 3000 if (ret) 3001 goto out; 3002 3003 /* init the device table */ 3004 init_device_table(); 3005 3006 out: 3007 /* Don't leak any ACPI memory */ 3008 acpi_put_table(ivrs_base); 3009 3010 return ret; 3011 } 3012 3013 static int amd_iommu_enable_interrupts(void) 3014 { 3015 struct amd_iommu *iommu; 3016 int ret = 0; 3017 3018 for_each_iommu(iommu) { 3019 ret = iommu_init_irq(iommu); 3020 if (ret) 3021 goto out; 3022 } 3023 3024 out: 3025 return ret; 3026 } 3027 3028 static bool __init detect_ivrs(void) 3029 { 3030 struct acpi_table_header *ivrs_base; 3031 acpi_status status; 3032 int i; 3033 3034 status = acpi_get_table("IVRS", 0, &ivrs_base); 3035 if (status == AE_NOT_FOUND) 3036 return false; 3037 else if (ACPI_FAILURE(status)) { 3038 const char *err = acpi_format_exception(status); 3039 pr_err("IVRS table error: %s\n", err); 3040 return false; 3041 } 3042 3043 acpi_put_table(ivrs_base); 3044 3045 if (amd_iommu_force_enable) 3046 goto out; 3047 3048 /* Don't use IOMMU if there is Stoney Ridge graphics */ 3049 for (i = 0; i < 32; i++) { 3050 u32 pci_id; 3051 3052 pci_id = read_pci_config(0, i, 0, 0); 3053 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) { 3054 pr_info("Disable IOMMU on Stoney Ridge\n"); 3055 return false; 3056 } 3057 } 3058 3059 out: 3060 /* Make sure ACS will be enabled during PCI probe */ 3061 pci_request_acs(); 3062 3063 return true; 3064 } 3065 3066 /**************************************************************************** 3067 * 3068 * AMD IOMMU Initialization State Machine 3069 * 3070 ****************************************************************************/ 3071 3072 static int __init state_next(void) 3073 { 3074 int ret = 0; 3075 3076 switch (init_state) { 3077 case IOMMU_START_STATE: 3078 if (!detect_ivrs()) { 3079 init_state = IOMMU_NOT_FOUND; 3080 ret = -ENODEV; 3081 } else { 3082 init_state = IOMMU_IVRS_DETECTED; 3083 } 3084 break; 3085 case IOMMU_IVRS_DETECTED: 3086 if (amd_iommu_disabled) { 3087 init_state = IOMMU_CMDLINE_DISABLED; 3088 ret = -EINVAL; 3089 } else { 3090 ret = early_amd_iommu_init(); 3091 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED; 3092 } 3093 break; 3094 case IOMMU_ACPI_FINISHED: 3095 early_enable_iommus(); 3096 x86_platform.iommu_shutdown = disable_iommus; 3097 init_state = IOMMU_ENABLED; 3098 break; 3099 case IOMMU_ENABLED: 3100 register_syscore_ops(&amd_iommu_syscore_ops); 3101 ret = amd_iommu_init_pci(); 3102 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; 3103 enable_iommus_v2(); 3104 break; 3105 case IOMMU_PCI_INIT: 3106 ret = amd_iommu_enable_interrupts(); 3107 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN; 3108 break; 3109 case IOMMU_INTERRUPTS_EN: 3110 init_state = IOMMU_INITIALIZED; 3111 break; 3112 case IOMMU_INITIALIZED: 3113 /* Nothing to do */ 3114 break; 3115 case IOMMU_NOT_FOUND: 3116 case IOMMU_INIT_ERROR: 3117 case IOMMU_CMDLINE_DISABLED: 3118 /* Error states => do nothing */ 3119 ret = -EINVAL; 3120 break; 3121 default: 3122 /* Unknown state */ 3123 BUG(); 3124 } 3125 3126 if (ret) { 3127 free_dma_resources(); 3128 if (!irq_remapping_enabled) { 3129 disable_iommus(); 3130 free_iommu_resources(); 3131 } else { 3132 struct amd_iommu *iommu; 3133 struct amd_iommu_pci_seg *pci_seg; 3134 3135 for_each_pci_segment(pci_seg) 3136 uninit_device_table_dma(pci_seg); 3137 3138 for_each_iommu(iommu) 3139 iommu_flush_all_caches(iommu); 3140 } 3141 } 3142 return ret; 3143 } 3144 3145 static int __init iommu_go_to_state(enum iommu_init_state state) 3146 { 3147 int ret = -EINVAL; 3148 3149 while (init_state != state) { 3150 if (init_state == IOMMU_NOT_FOUND || 3151 init_state == IOMMU_INIT_ERROR || 3152 init_state == IOMMU_CMDLINE_DISABLED) 3153 break; 3154 ret = state_next(); 3155 } 3156 3157 return ret; 3158 } 3159 3160 #ifdef CONFIG_IRQ_REMAP 3161 int __init amd_iommu_prepare(void) 3162 { 3163 int ret; 3164 3165 amd_iommu_irq_remap = true; 3166 3167 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED); 3168 if (ret) { 3169 amd_iommu_irq_remap = false; 3170 return ret; 3171 } 3172 3173 return amd_iommu_irq_remap ? 0 : -ENODEV; 3174 } 3175 3176 int __init amd_iommu_enable(void) 3177 { 3178 int ret; 3179 3180 ret = iommu_go_to_state(IOMMU_ENABLED); 3181 if (ret) 3182 return ret; 3183 3184 irq_remapping_enabled = 1; 3185 return amd_iommu_xt_mode; 3186 } 3187 3188 void amd_iommu_disable(void) 3189 { 3190 amd_iommu_suspend(); 3191 } 3192 3193 int amd_iommu_reenable(int mode) 3194 { 3195 amd_iommu_resume(); 3196 3197 return 0; 3198 } 3199 3200 int __init amd_iommu_enable_faulting(void) 3201 { 3202 /* We enable MSI later when PCI is initialized */ 3203 return 0; 3204 } 3205 #endif 3206 3207 /* 3208 * This is the core init function for AMD IOMMU hardware in the system. 3209 * This function is called from the generic x86 DMA layer initialization 3210 * code. 3211 */ 3212 static int __init amd_iommu_init(void) 3213 { 3214 struct amd_iommu *iommu; 3215 int ret; 3216 3217 ret = iommu_go_to_state(IOMMU_INITIALIZED); 3218 #ifdef CONFIG_GART_IOMMU 3219 if (ret && list_empty(&amd_iommu_list)) { 3220 /* 3221 * We failed to initialize the AMD IOMMU - try fallback 3222 * to GART if possible. 3223 */ 3224 gart_iommu_init(); 3225 } 3226 #endif 3227 3228 for_each_iommu(iommu) 3229 amd_iommu_debugfs_setup(iommu); 3230 3231 return ret; 3232 } 3233 3234 static bool amd_iommu_sme_check(void) 3235 { 3236 if (!cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) || 3237 (boot_cpu_data.x86 != 0x17)) 3238 return true; 3239 3240 /* For Fam17h, a specific level of support is required */ 3241 if (boot_cpu_data.microcode >= 0x08001205) 3242 return true; 3243 3244 if ((boot_cpu_data.microcode >= 0x08001126) && 3245 (boot_cpu_data.microcode <= 0x080011ff)) 3246 return true; 3247 3248 pr_notice("IOMMU not currently supported when SME is active\n"); 3249 3250 return false; 3251 } 3252 3253 /**************************************************************************** 3254 * 3255 * Early detect code. This code runs at IOMMU detection time in the DMA 3256 * layer. It just looks if there is an IVRS ACPI table to detect AMD 3257 * IOMMUs 3258 * 3259 ****************************************************************************/ 3260 int __init amd_iommu_detect(void) 3261 { 3262 int ret; 3263 3264 if (no_iommu || (iommu_detected && !gart_iommu_aperture)) 3265 return -ENODEV; 3266 3267 if (!amd_iommu_sme_check()) 3268 return -ENODEV; 3269 3270 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED); 3271 if (ret) 3272 return ret; 3273 3274 amd_iommu_detected = true; 3275 iommu_detected = 1; 3276 x86_init.iommu.iommu_init = amd_iommu_init; 3277 3278 return 1; 3279 } 3280 3281 /**************************************************************************** 3282 * 3283 * Parsing functions for the AMD IOMMU specific kernel command line 3284 * options. 3285 * 3286 ****************************************************************************/ 3287 3288 static int __init parse_amd_iommu_dump(char *str) 3289 { 3290 amd_iommu_dump = true; 3291 3292 return 1; 3293 } 3294 3295 static int __init parse_amd_iommu_intr(char *str) 3296 { 3297 for (; *str; ++str) { 3298 if (strncmp(str, "legacy", 6) == 0) { 3299 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; 3300 break; 3301 } 3302 if (strncmp(str, "vapic", 5) == 0) { 3303 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; 3304 break; 3305 } 3306 } 3307 return 1; 3308 } 3309 3310 static int __init parse_amd_iommu_options(char *str) 3311 { 3312 for (; *str; ++str) { 3313 if (strncmp(str, "fullflush", 9) == 0) { 3314 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); 3315 iommu_set_dma_strict(); 3316 } 3317 if (strncmp(str, "force_enable", 12) == 0) 3318 amd_iommu_force_enable = true; 3319 if (strncmp(str, "off", 3) == 0) 3320 amd_iommu_disabled = true; 3321 if (strncmp(str, "force_isolation", 15) == 0) 3322 amd_iommu_force_isolation = true; 3323 } 3324 3325 return 1; 3326 } 3327 3328 static int __init parse_ivrs_ioapic(char *str) 3329 { 3330 unsigned int bus, dev, fn; 3331 int ret, id, i; 3332 u16 devid; 3333 3334 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3335 3336 if (ret != 4) { 3337 pr_err("Invalid command line: ivrs_ioapic%s\n", str); 3338 return 1; 3339 } 3340 3341 if (early_ioapic_map_size == EARLY_MAP_SIZE) { 3342 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", 3343 str); 3344 return 1; 3345 } 3346 3347 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3348 3349 cmdline_maps = true; 3350 i = early_ioapic_map_size++; 3351 early_ioapic_map[i].id = id; 3352 early_ioapic_map[i].devid = devid; 3353 early_ioapic_map[i].cmd_line = true; 3354 3355 return 1; 3356 } 3357 3358 static int __init parse_ivrs_hpet(char *str) 3359 { 3360 unsigned int bus, dev, fn; 3361 int ret, id, i; 3362 u16 devid; 3363 3364 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); 3365 3366 if (ret != 4) { 3367 pr_err("Invalid command line: ivrs_hpet%s\n", str); 3368 return 1; 3369 } 3370 3371 if (early_hpet_map_size == EARLY_MAP_SIZE) { 3372 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", 3373 str); 3374 return 1; 3375 } 3376 3377 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3378 3379 cmdline_maps = true; 3380 i = early_hpet_map_size++; 3381 early_hpet_map[i].id = id; 3382 early_hpet_map[i].devid = devid; 3383 early_hpet_map[i].cmd_line = true; 3384 3385 return 1; 3386 } 3387 3388 static int __init parse_ivrs_acpihid(char *str) 3389 { 3390 u32 bus, dev, fn; 3391 char *hid, *uid, *p; 3392 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0}; 3393 int ret, i; 3394 3395 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid); 3396 if (ret != 4) { 3397 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str); 3398 return 1; 3399 } 3400 3401 p = acpiid; 3402 hid = strsep(&p, ":"); 3403 uid = p; 3404 3405 if (!hid || !(*hid) || !uid) { 3406 pr_err("Invalid command line: hid or uid\n"); 3407 return 1; 3408 } 3409 3410 i = early_acpihid_map_size++; 3411 memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); 3412 memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); 3413 early_acpihid_map[i].devid = 3414 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); 3415 early_acpihid_map[i].cmd_line = true; 3416 3417 return 1; 3418 } 3419 3420 __setup("amd_iommu_dump", parse_amd_iommu_dump); 3421 __setup("amd_iommu=", parse_amd_iommu_options); 3422 __setup("amd_iommu_intr=", parse_amd_iommu_intr); 3423 __setup("ivrs_ioapic", parse_ivrs_ioapic); 3424 __setup("ivrs_hpet", parse_ivrs_hpet); 3425 __setup("ivrs_acpihid", parse_ivrs_acpihid); 3426 3427 bool amd_iommu_v2_supported(void) 3428 { 3429 return amd_iommu_v2_present; 3430 } 3431 EXPORT_SYMBOL(amd_iommu_v2_supported); 3432 3433 struct amd_iommu *get_amd_iommu(unsigned int idx) 3434 { 3435 unsigned int i = 0; 3436 struct amd_iommu *iommu; 3437 3438 for_each_iommu(iommu) 3439 if (i++ == idx) 3440 return iommu; 3441 return NULL; 3442 } 3443 3444 /**************************************************************************** 3445 * 3446 * IOMMU EFR Performance Counter support functionality. This code allows 3447 * access to the IOMMU PC functionality. 3448 * 3449 ****************************************************************************/ 3450 3451 u8 amd_iommu_pc_get_max_banks(unsigned int idx) 3452 { 3453 struct amd_iommu *iommu = get_amd_iommu(idx); 3454 3455 if (iommu) 3456 return iommu->max_banks; 3457 3458 return 0; 3459 } 3460 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks); 3461 3462 bool amd_iommu_pc_supported(void) 3463 { 3464 return amd_iommu_pc_present; 3465 } 3466 EXPORT_SYMBOL(amd_iommu_pc_supported); 3467 3468 u8 amd_iommu_pc_get_max_counters(unsigned int idx) 3469 { 3470 struct amd_iommu *iommu = get_amd_iommu(idx); 3471 3472 if (iommu) 3473 return iommu->max_counters; 3474 3475 return 0; 3476 } 3477 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters); 3478 3479 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, 3480 u8 fxn, u64 *value, bool is_write) 3481 { 3482 u32 offset; 3483 u32 max_offset_lim; 3484 3485 /* Make sure the IOMMU PC resource is available */ 3486 if (!amd_iommu_pc_present) 3487 return -ENODEV; 3488 3489 /* Check for valid iommu and pc register indexing */ 3490 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) 3491 return -ENODEV; 3492 3493 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn); 3494 3495 /* Limit the offset to the hw defined mmio region aperture */ 3496 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | 3497 (iommu->max_counters << 8) | 0x28); 3498 if ((offset < MMIO_CNTR_REG_OFFSET) || 3499 (offset > max_offset_lim)) 3500 return -EINVAL; 3501 3502 if (is_write) { 3503 u64 val = *value & GENMASK_ULL(47, 0); 3504 3505 writel((u32)val, iommu->mmio_base + offset); 3506 writel((val >> 32), iommu->mmio_base + offset + 4); 3507 } else { 3508 *value = readl(iommu->mmio_base + offset + 4); 3509 *value <<= 32; 3510 *value |= readl(iommu->mmio_base + offset); 3511 *value &= GENMASK_ULL(47, 0); 3512 } 3513 3514 return 0; 3515 } 3516 3517 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3518 { 3519 if (!iommu) 3520 return -EINVAL; 3521 3522 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); 3523 } 3524 3525 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) 3526 { 3527 if (!iommu) 3528 return -EINVAL; 3529 3530 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); 3531 } 3532