sor.c (27ba465ce3397c4705f87c1f73e6d67c1b48ef0f) sor.c (c176393728c9fcd8f7ef842cb3e4cedda3f418a2)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/debugfs.h>

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378
379 const struct tegra_sor_regs *regs;
380 bool has_nvdisplay;
381
382 const struct tegra_sor_hdmi_settings *settings;
383 unsigned int num_settings;
384
385 const u8 *xbar_cfg;
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/debugfs.h>

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378
379 const struct tegra_sor_regs *regs;
380 bool has_nvdisplay;
381
382 const struct tegra_sor_hdmi_settings *settings;
383 unsigned int num_settings;
384
385 const u8 *xbar_cfg;
386 const u8 *lane_map;
387
388 const u8 (*voltage_swing)[4][4];
389 const u8 (*pre_emphasis)[4][4];
390 const u8 (*post_cursor)[4][4];
391 const u8 (*tx_pu)[4][4];
386};
387
388struct tegra_sor;
389
390struct tegra_sor_ops {
391 const char *name;
392 int (*probe)(struct tegra_sor *sor);
393 int (*remove)(struct tegra_sor *sor);

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408 struct clk *clk_safe;
409 struct clk *clk_out;
410 struct clk *clk_pad;
411 struct clk *clk_dp;
412 struct clk *clk;
413
414 u8 xbar_cfg[5];
415
392};
393
394struct tegra_sor;
395
396struct tegra_sor_ops {
397 const char *name;
398 int (*probe)(struct tegra_sor *sor);
399 int (*remove)(struct tegra_sor *sor);

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414 struct clk *clk_safe;
415 struct clk *clk_out;
416 struct clk *clk_pad;
417 struct clk *clk_dp;
418 struct clk *clk;
419
420 u8 xbar_cfg[5];
421
422 struct drm_dp_link link;
416 struct drm_dp_aux *aux;
417
418 struct drm_info_list *debugfs_files;
419
420 const struct tegra_sor_ops *ops;
421 enum tegra_io_pad pad;
422
423 /* for HDMI 2.0 */

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593
594 pad->hw.init = &init;
595
596 clk = devm_clk_register(sor->dev, &pad->hw);
597
598 return clk;
599}
600
423 struct drm_dp_aux *aux;
424
425 struct drm_info_list *debugfs_files;
426
427 const struct tegra_sor_ops *ops;
428 enum tegra_io_pad pad;
429
430 /* for HDMI 2.0 */

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600
601 pad->hw.init = &init;
602
603 clk = devm_clk_register(sor->dev, &pad->hw);
604
605 return clk;
606}
607
601static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
602 struct drm_dp_link *link)
608static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
603{
609{
604 unsigned int i;
605 u8 pattern;
610 unsigned long timeout;
606 u32 value;
611 u32 value;
607 int err;
608
612
609 /* setup lane parameters */
610 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
611 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
612 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
613 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
614 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
613 /*
614 * Clear or set the PD_TXD bit corresponding to each lane, depending
615 * on whether it is used or not.
616 */
617 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
615
618
616 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
617 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
618 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
619 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
620 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
619 if (lanes <= 2)
620 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
621 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
622 else
623 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
624 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
621
625
622 value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
623 SOR_LANE_POSTCURSOR_LANE2(0x00) |
624 SOR_LANE_POSTCURSOR_LANE1(0x00) |
625 SOR_LANE_POSTCURSOR_LANE0(0x00);
626 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
626 if (lanes <= 1)
627 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
628 else
629 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
627
630
628 /* disable LVDS mode */
629 tegra_sor_writel(sor, 0, SOR_LVDS);
631 if (lanes == 0)
632 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
633 else
634 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
630
635
636 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
637
638 /* start lane sequencer */
639 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
640 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
641 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
642
643 timeout = jiffies + msecs_to_jiffies(250);
644
645 while (time_before(jiffies, timeout)) {
646 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
647 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
648 break;
649
650 usleep_range(250, 1000);
651 }
652
653 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
654 return -ETIMEDOUT;
655
656 return 0;
657}
658
659static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
660{
661 unsigned long timeout;
662 u32 value;
663
664 /* power down all lanes */
631 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
665 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
632 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
633 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
634 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
666 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
667 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
635 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
636
668 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
669
670 /* start lane sequencer */
671 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
672 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
673 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
674
675 timeout = jiffies + msecs_to_jiffies(250);
676
677 while (time_before(jiffies, timeout)) {
678 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
679 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
680 break;
681
682 usleep_range(25, 100);
683 }
684
685 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
686 return -ETIMEDOUT;
687
688 return 0;
689}
690
691static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
692{
693 u32 value;
694
695 /* pre-charge all used lanes */
637 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
696 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
638 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
639 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
697
698 if (lanes <= 2)
699 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
700 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
701 else
702 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
703 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
704
705 if (lanes <= 1)
706 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
707 else
708 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
709
710 if (lanes == 0)
711 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
712 else
713 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
714
640 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
641
715 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
716
642 usleep_range(10, 100);
717 usleep_range(15, 100);
643
644 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
645 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
646 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
647 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
718
719 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
720 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
721 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
722 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
723}
648
724
649 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
650 if (err < 0)
651 return err;
725static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
726{
727 u32 mask = 0x08, adj = 0, value;
652
728
653 for (i = 0, value = 0; i < link->lanes; i++) {
654 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
655 SOR_DP_TPG_SCRAMBLER_NONE |
656 SOR_DP_TPG_PATTERN_TRAIN1;
657 value = (value << 8) | lane;
729 /* enable pad calibration logic */
730 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
731 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
732 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
733
734 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
735 value |= SOR_PLL1_TMDS_TERM;
736 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
737
738 while (mask) {
739 adj |= mask;
740
741 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
742 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
743 value |= SOR_PLL1_TMDS_TERMADJ(adj);
744 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
745
746 usleep_range(100, 200);
747
748 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
749 if (value & SOR_PLL1_TERM_COMPOUT)
750 adj &= ~mask;
751
752 mask >>= 1;
658 }
659
753 }
754
660 tegra_sor_writel(sor, value, SOR_DP_TPG);
755 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
756 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
757 value |= SOR_PLL1_TMDS_TERMADJ(adj);
758 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
661
759
662 pattern = DP_TRAINING_PATTERN_1;
760 /* disable pad calibration logic */
761 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
762 value |= SOR_DP_PADCTL_PAD_CAL_PD;
763 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
764}
663
765
664 err = drm_dp_aux_train(sor->aux, link, pattern);
665 if (err < 0)
666 return err;
766static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
767{
768 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
769 u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
770 const struct tegra_sor_soc *soc = sor->soc;
771 u32 pattern = 0, tx_pu = 0, value;
772 unsigned int i;
667
773
668 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
669 value |= SOR_DP_SPARE_SEQ_ENABLE;
670 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
671 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
672 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
774 for (value = 0, i = 0; i < link->lanes; i++) {
775 u8 vs = link->train.request.voltage_swing[i];
776 u8 pe = link->train.request.pre_emphasis[i];
777 u8 pc = link->train.request.post_cursor[i];
778 u8 shift = sor->soc->lane_map[i] << 3;
673
779
674 for (i = 0, value = 0; i < link->lanes; i++) {
675 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
676 SOR_DP_TPG_SCRAMBLER_NONE |
677 SOR_DP_TPG_PATTERN_TRAIN2;
678 value = (value << 8) | lane;
780 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
781 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
782 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
783
784 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
785 tx_pu = sor->soc->tx_pu[pc][vs][pe];
786
787 switch (link->train.pattern) {
788 case DP_TRAINING_PATTERN_DISABLE:
789 value = SOR_DP_TPG_SCRAMBLER_GALIOS |
790 SOR_DP_TPG_PATTERN_NONE;
791 break;
792
793 case DP_TRAINING_PATTERN_1:
794 value = SOR_DP_TPG_SCRAMBLER_NONE |
795 SOR_DP_TPG_PATTERN_TRAIN1;
796 break;
797
798 case DP_TRAINING_PATTERN_2:
799 value = SOR_DP_TPG_SCRAMBLER_NONE |
800 SOR_DP_TPG_PATTERN_TRAIN2;
801 break;
802
803 case DP_TRAINING_PATTERN_3:
804 value = SOR_DP_TPG_SCRAMBLER_NONE |
805 SOR_DP_TPG_PATTERN_TRAIN3;
806 break;
807
808 default:
809 return -EINVAL;
810 }
811
812 if (link->caps.channel_coding)
813 value |= SOR_DP_TPG_CHANNEL_CODING;
814
815 pattern = pattern << 8 | value;
679 }
680
816 }
817
681 tegra_sor_writel(sor, value, SOR_DP_TPG);
818 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
819 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
682
820
683 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
821 if (link->caps.tps3_supported)
822 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
684
823
685 err = drm_dp_aux_train(sor->aux, link, pattern);
686 if (err < 0)
687 return err;
824 tegra_sor_writel(sor, pattern, SOR_DP_TPG);
688
825
689 for (i = 0, value = 0; i < link->lanes; i++) {
690 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
691 SOR_DP_TPG_SCRAMBLER_GALIOS |
692 SOR_DP_TPG_PATTERN_NONE;
693 value = (value << 8) | lane;
826 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
827 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
828 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
829 value |= SOR_DP_PADCTL_TX_PU(tx_pu);
830 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
831
832 usleep_range(20, 100);
833
834 return 0;
835}
836
837static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
838{
839 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
840 unsigned int rate, lanes;
841 u32 value;
842 int err;
843
844 rate = drm_dp_link_rate_to_bw_code(link->rate);
845 lanes = link->lanes;
846
847 /* configure link speed and lane count */
848 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
849 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
850 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
851 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
852
853 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
854 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
855 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
856
857 if (link->caps.enhanced_framing)
858 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
859
860 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
861
862 usleep_range(400, 1000);
863
864 /* configure load pulse position adjustment */
865 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
866 value &= ~SOR_PLL1_LOADADJ_MASK;
867
868 switch (rate) {
869 case DP_LINK_BW_1_62:
870 value |= SOR_PLL1_LOADADJ(0x3);
871 break;
872
873 case DP_LINK_BW_2_7:
874 value |= SOR_PLL1_LOADADJ(0x4);
875 break;
876
877 case DP_LINK_BW_5_4:
878 value |= SOR_PLL1_LOADADJ(0x6);
879 break;
694 }
695
880 }
881
696 tegra_sor_writel(sor, value, SOR_DP_TPG);
882 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
697
883
698 pattern = DP_TRAINING_PATTERN_DISABLE;
884 /* use alternate scrambler reset for eDP */
885 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
699
886
700 err = drm_dp_aux_train(sor->aux, link, pattern);
701 if (err < 0)
887 if (link->edp == 0)
888 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
889 else
890 value |= SOR_DP_SPARE_PANEL_INTERNAL;
891
892 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
893
894 err = tegra_sor_power_down_lanes(sor);
895 if (err < 0) {
896 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
702 return err;
897 return err;
898 }
703
899
900 /* power up and pre-charge lanes */
901 err = tegra_sor_power_up_lanes(sor, lanes);
902 if (err < 0) {
903 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
904 lanes, (lanes != 1) ? "s" : "", err);
905 return err;
906 }
907
908 tegra_sor_dp_precharge(sor, lanes);
909
704 return 0;
705}
706
910 return 0;
911}
912
913static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
914 .apply_training = tegra_sor_dp_link_apply_training,
915 .configure = tegra_sor_dp_link_configure,
916};
917
707static void tegra_sor_super_update(struct tegra_sor *sor)
708{
709 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
710 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
711 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
712}
713
714static void tegra_sor_update(struct tegra_sor *sor)

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1196
1197 /* switch to safe parent clock */
1198 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1199 if (err < 0) {
1200 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1201 return err;
1202 }
1203
918static void tegra_sor_super_update(struct tegra_sor *sor)
919{
920 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
921 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
922 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
923}
924
925static void tegra_sor_update(struct tegra_sor *sor)

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1407
1408 /* switch to safe parent clock */
1409 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1410 if (err < 0) {
1411 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1412 return err;
1413 }
1414
1204 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1205 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1206 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1207 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1208
1209 /* stop lane sequencer */
1210 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1211 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1212 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1213
1214 timeout = jiffies + msecs_to_jiffies(250);
1215
1216 while (time_before(jiffies, timeout)) {
1217 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1218 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1219 break;
1220
1221 usleep_range(25, 100);
1222 }
1223
1224 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1225 return -ETIMEDOUT;
1226
1227 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1228 value |= SOR_PLL2_PORT_POWERDOWN;
1229 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1230
1231 usleep_range(20, 100);
1232
1233 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1234 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;

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1598
1599 err = tegra_sor_detach(sor);
1600 if (err < 0)
1601 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1602
1603 tegra_sor_writel(sor, 0, SOR_STATE1);
1604 tegra_sor_update(sor);
1605
1415 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1416 value |= SOR_PLL2_PORT_POWERDOWN;
1417 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1418
1419 usleep_range(20, 100);
1420
1421 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1422 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;

--- 363 unchanged lines hidden (view full) ---

1786
1787 err = tegra_sor_detach(sor);
1788 if (err < 0)
1789 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1790
1791 tegra_sor_writel(sor, 0, SOR_STATE1);
1792 tegra_sor_update(sor);
1793
1606 /*
1607 * The following accesses registers of the display controller, so make
1608 * sure it's only executed when the output is attached to one.
1609 */
1610 if (dc) {
1611 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1612 value &= ~SOR_ENABLE(0);
1613 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1794 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1795 value &= ~SOR_ENABLE(0);
1796 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1614
1797
1615 tegra_dc_commit(dc);
1616 }
1798 tegra_dc_commit(dc);
1617
1618 err = tegra_sor_power_down(sor);
1619 if (err < 0)
1620 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1621
1622 if (sor->aux) {
1623 err = drm_dp_aux_disable(sor->aux);
1624 if (err < 0)

--- 49 unchanged lines hidden (view full) ---

1674 }
1675
1676 return 0;
1677}
1678#endif
1679
1680static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1681{
1799
1800 err = tegra_sor_power_down(sor);
1801 if (err < 0)
1802 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1803
1804 if (sor->aux) {
1805 err = drm_dp_aux_disable(sor->aux);
1806 if (err < 0)

--- 49 unchanged lines hidden (view full) ---

1856 }
1857
1858 return 0;
1859}
1860#endif
1861
1862static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1863{
1682 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1683 struct tegra_output *output = encoder_to_output(encoder);
1684 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1685 struct tegra_sor *sor = to_sor(output);
1686 struct tegra_sor_config config;
1687 struct tegra_sor_state *state;
1864 struct tegra_output *output = encoder_to_output(encoder);
1865 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1866 struct tegra_sor *sor = to_sor(output);
1867 struct tegra_sor_config config;
1868 struct tegra_sor_state *state;
1688 struct drm_dp_link link;
1689 u8 rate, lanes;
1869 struct drm_display_mode *mode;
1870 struct drm_display_info *info;
1690 unsigned int i;
1871 unsigned int i;
1691 int err = 0;
1692 u32 value;
1872 u32 value;
1873 int err;
1693
1694 state = to_sor_state(output->connector.state);
1874
1875 state = to_sor_state(output->connector.state);
1876 mode = &encoder->crtc->state->adjusted_mode;
1877 info = &output->connector.display_info;
1695
1696 pm_runtime_get_sync(sor->dev);
1697
1698 if (output->panel)
1699 drm_panel_prepare(output->panel);
1700
1701 err = drm_dp_aux_enable(sor->aux);
1702 if (err < 0)
1703 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1704
1878
1879 pm_runtime_get_sync(sor->dev);
1880
1881 if (output->panel)
1882 drm_panel_prepare(output->panel);
1883
1884 err = drm_dp_aux_enable(sor->aux);
1885 if (err < 0)
1886 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1887
1705 err = drm_dp_link_probe(sor->aux, &link);
1888 err = drm_dp_link_probe(sor->aux, &sor->link);
1706 if (err < 0) {
1707 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1708 return;
1709 }
1710
1711 /* switch to safe parent clock */
1712 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1713 if (err < 0)
1714 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1715
1889 if (err < 0) {
1890 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1891 return;
1892 }
1893
1894 /* switch to safe parent clock */
1895 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1896 if (err < 0)
1897 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1898
1716 memset(&config, 0, sizeof(config));
1717 config.bits_per_pixel = state->bpc * 3;
1718
1719 err = tegra_sor_compute_config(sor, mode, &config, &link);
1720 if (err < 0)
1721 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1722
1723 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1724 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1725 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1726 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1727
1728 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1729 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1730 tegra_sor_writel(sor, value, sor->soc->regs->pll2);

--- 92 unchanged lines hidden (view full) ---

1823 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1824 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1825
1826 /* switch to DP parent clock */
1827 err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1828 if (err < 0)
1829 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1830
1899 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1900 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1901 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1902 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1903
1904 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1905 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1906 tegra_sor_writel(sor, value, sor->soc->regs->pll2);

--- 92 unchanged lines hidden (view full) ---

1999 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2000 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2001
2002 /* switch to DP parent clock */
2003 err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
2004 if (err < 0)
2005 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2006
1831 /* power DP lanes */
1832 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2007 /* use DP-A protocol */
2008 value = tegra_sor_readl(sor, SOR_STATE1);
2009 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2010 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2011 tegra_sor_writel(sor, value, SOR_STATE1);
1833
2012
1834 if (link.lanes <= 2)
1835 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1836 else
1837 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1838
1839 if (link.lanes <= 1)
1840 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1841 else
1842 value |= SOR_DP_PADCTL_PD_TXD_1;
1843
1844 if (link.lanes == 0)
1845 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1846 else
1847 value |= SOR_DP_PADCTL_PD_TXD_0;
1848
1849 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1850
2013 /* enable port */
1851 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2014 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1852 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1853 value |= SOR_DP_LINKCTL_LANE_COUNT(link.lanes);
1854 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1855
1856 /* start lane sequencer */
1857 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1858 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1859 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1860
1861 while (true) {
1862 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1863 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1864 break;
1865
1866 usleep_range(250, 1000);
1867 }
1868
1869 /* set link bandwidth */
1870 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1871 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1872 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1873 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1874
1875 tegra_sor_apply_config(sor, &config);
1876
1877 /* enable link */
1878 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1879 value |= SOR_DP_LINKCTL_ENABLE;
2015 value |= SOR_DP_LINKCTL_ENABLE;
1880 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1881 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1882
2016 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2017
1883 for (i = 0, value = 0; i < 4; i++) {
1884 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1885 SOR_DP_TPG_SCRAMBLER_GALIOS |
1886 SOR_DP_TPG_PATTERN_NONE;
1887 value = (value << 8) | lane;
1888 }
2018 /* calibrate termination resistance (XXX do this only on HPD) */
2019 tegra_sor_dp_term_calibrate(sor);
1889
2020
1890 tegra_sor_writel(sor, value, SOR_DP_TPG);
1891
1892 /* enable pad calibration logic */
1893 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1894 value |= SOR_DP_PADCTL_PAD_CAL_PD;
1895 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1896
1897 err = drm_dp_link_probe(sor->aux, &link);
2021 err = drm_dp_link_train(&sor->link);
1898 if (err < 0)
2022 if (err < 0)
1899 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
2023 dev_err(sor->dev, "link training failed: %d\n", err);
2024 else
2025 dev_dbg(sor->dev, "link training succeeded\n");
1900
2026
1901 err = drm_dp_link_power_up(sor->aux, &link);
1902 if (err < 0)
1903 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
2027 err = drm_dp_link_power_up(sor->aux, &sor->link);
2028 if (err < 0) {
2029 dev_err(sor->dev, "failed to power up eDP link: %d\n",
2030 err);
2031 return;
2032 }
1904
2033
1905 err = drm_dp_link_configure(sor->aux, &link);
1906 if (err < 0)
1907 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
2034 /* compute configuration */
2035 memset(&config, 0, sizeof(config));
2036 config.bits_per_pixel = state->bpc * 3;
1908
2037
1909 rate = drm_dp_link_rate_to_bw_code(link.rate);
1910 lanes = link.lanes;
1911
1912 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1913 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1914 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1915 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1916
1917 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1918 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1919 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1920
1921 if (link.caps.enhanced_framing)
1922 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1923
1924 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1925
1926 /* disable training pattern generator */
1927
1928 for (i = 0; i < link.lanes; i++) {
1929 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1930 SOR_DP_TPG_SCRAMBLER_GALIOS |
1931 SOR_DP_TPG_PATTERN_NONE;
1932 value = (value << 8) | lane;
2038 err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2039 if (err < 0) {
2040 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2041 return;
1933 }
1934
2042 }
2043
1935 tegra_sor_writel(sor, value, SOR_DP_TPG);
2044 tegra_sor_apply_config(sor, &config);
1936
2045
1937 err = tegra_sor_dp_train_fast(sor, &link);
1938 if (err < 0)
1939 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1940
1941 dev_dbg(sor->dev, "fast link training succeeded\n");
1942
1943 err = tegra_sor_power_up(sor, 250);
1944 if (err < 0)
1945 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1946
1947 /* CSTM (LVDS, link A/B, upper) */
1948 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1949 SOR_CSTM_UPPER;
1950 tegra_sor_writel(sor, value, SOR_CSTM);

--- 886 unchanged lines hidden (view full) ---

2837 if (sor->soc->supports_edp) {
2838 connector = DRM_MODE_CONNECTOR_eDP;
2839 encoder = DRM_MODE_ENCODER_TMDS;
2840 helpers = &tegra_sor_edp_helpers;
2841 } else if (sor->soc->supports_dp) {
2842 connector = DRM_MODE_CONNECTOR_DisplayPort;
2843 encoder = DRM_MODE_ENCODER_TMDS;
2844 }
2046 err = tegra_sor_power_up(sor, 250);
2047 if (err < 0)
2048 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2049
2050 /* CSTM (LVDS, link A/B, upper) */
2051 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2052 SOR_CSTM_UPPER;
2053 tegra_sor_writel(sor, value, SOR_CSTM);

--- 886 unchanged lines hidden (view full) ---

2940 if (sor->soc->supports_edp) {
2941 connector = DRM_MODE_CONNECTOR_eDP;
2942 encoder = DRM_MODE_ENCODER_TMDS;
2943 helpers = &tegra_sor_edp_helpers;
2944 } else if (sor->soc->supports_dp) {
2945 connector = DRM_MODE_CONNECTOR_DisplayPort;
2946 encoder = DRM_MODE_ENCODER_TMDS;
2947 }
2948
2949 sor->link.ops = &tegra_sor_dp_link_ops;
2950 sor->link.aux = sor->aux;
2845 }
2846
2847 sor->output.dev = sor->dev;
2848
2849 drm_connector_init(drm, &sor->output.connector,
2850 &tegra_sor_connector_funcs,
2851 connector);
2852 drm_connector_helper_add(&sor->output.connector,

--- 184 unchanged lines hidden (view full) ---

3037 .pll0 = 0x17,
3038 .pll1 = 0x18,
3039 .pll2 = 0x19,
3040 .pll3 = 0x1a,
3041 .dp_padctl0 = 0x5c,
3042 .dp_padctl2 = 0x73,
3043};
3044
2951 }
2952
2953 sor->output.dev = sor->dev;
2954
2955 drm_connector_init(drm, &sor->output.connector,
2956 &tegra_sor_connector_funcs,
2957 connector);
2958 drm_connector_helper_add(&sor->output.connector,

--- 184 unchanged lines hidden (view full) ---

3143 .pll0 = 0x17,
3144 .pll1 = 0x18,
3145 .pll2 = 0x19,
3146 .pll3 = 0x1a,
3147 .dp_padctl0 = 0x5c,
3148 .dp_padctl2 = 0x73,
3149};
3150
3151/* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3152static const u8 tegra124_sor_lane_map[4] = {
3153 2, 1, 0, 3,
3154};
3155
3156static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3157 {
3158 { 0x13, 0x19, 0x1e, 0x28 },
3159 { 0x1e, 0x25, 0x2d, },
3160 { 0x28, 0x32, },
3161 { 0x3c, },
3162 }, {
3163 { 0x12, 0x17, 0x1b, 0x25 },
3164 { 0x1c, 0x23, 0x2a, },
3165 { 0x25, 0x2f, },
3166 { 0x39, }
3167 }, {
3168 { 0x12, 0x16, 0x1a, 0x22 },
3169 { 0x1b, 0x20, 0x27, },
3170 { 0x24, 0x2d, },
3171 { 0x36, },
3172 }, {
3173 { 0x11, 0x14, 0x17, 0x1f },
3174 { 0x19, 0x1e, 0x24, },
3175 { 0x22, 0x2a, },
3176 { 0x32, },
3177 },
3178};
3179
3180static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3181 {
3182 { 0x00, 0x09, 0x13, 0x25 },
3183 { 0x00, 0x0f, 0x1e, },
3184 { 0x00, 0x14, },
3185 { 0x00, },
3186 }, {
3187 { 0x00, 0x0a, 0x14, 0x28 },
3188 { 0x00, 0x0f, 0x1e, },
3189 { 0x00, 0x14, },
3190 { 0x00 },
3191 }, {
3192 { 0x00, 0x0a, 0x14, 0x28 },
3193 { 0x00, 0x0f, 0x1e, },
3194 { 0x00, 0x14, },
3195 { 0x00, },
3196 }, {
3197 { 0x00, 0x0a, 0x14, 0x28 },
3198 { 0x00, 0x0f, 0x1e, },
3199 { 0x00, 0x14, },
3200 { 0x00, },
3201 },
3202};
3203
3204static const u8 tegra124_sor_post_cursor[4][4][4] = {
3205 {
3206 { 0x00, 0x00, 0x00, 0x00 },
3207 { 0x00, 0x00, 0x00, },
3208 { 0x00, 0x00, },
3209 { 0x00, },
3210 }, {
3211 { 0x02, 0x02, 0x04, 0x05 },
3212 { 0x02, 0x04, 0x05, },
3213 { 0x04, 0x05, },
3214 { 0x05, },
3215 }, {
3216 { 0x04, 0x05, 0x08, 0x0b },
3217 { 0x05, 0x09, 0x0b, },
3218 { 0x08, 0x0a, },
3219 { 0x0b, },
3220 }, {
3221 { 0x05, 0x09, 0x0b, 0x12 },
3222 { 0x09, 0x0d, 0x12, },
3223 { 0x0b, 0x0f, },
3224 { 0x12, },
3225 },
3226};
3227
3228static const u8 tegra124_sor_tx_pu[4][4][4] = {
3229 {
3230 { 0x20, 0x30, 0x40, 0x60 },
3231 { 0x30, 0x40, 0x60, },
3232 { 0x40, 0x60, },
3233 { 0x60, },
3234 }, {
3235 { 0x20, 0x20, 0x30, 0x50 },
3236 { 0x30, 0x40, 0x50, },
3237 { 0x40, 0x50, },
3238 { 0x60, },
3239 }, {
3240 { 0x20, 0x20, 0x30, 0x40, },
3241 { 0x30, 0x30, 0x40, },
3242 { 0x40, 0x50, },
3243 { 0x60, },
3244 }, {
3245 { 0x20, 0x20, 0x20, 0x40, },
3246 { 0x30, 0x30, 0x40, },
3247 { 0x40, 0x40, },
3248 { 0x60, },
3249 },
3250};
3251
3045static const struct tegra_sor_soc tegra124_sor = {
3046 .supports_edp = true,
3047 .supports_lvds = true,
3048 .supports_hdmi = false,
3049 .supports_dp = false,
3050 .regs = &tegra124_sor_regs,
3051 .has_nvdisplay = false,
3052 .xbar_cfg = tegra124_sor_xbar_cfg,
3252static const struct tegra_sor_soc tegra124_sor = {
3253 .supports_edp = true,
3254 .supports_lvds = true,
3255 .supports_hdmi = false,
3256 .supports_dp = false,
3257 .regs = &tegra124_sor_regs,
3258 .has_nvdisplay = false,
3259 .xbar_cfg = tegra124_sor_xbar_cfg,
3260 .lane_map = tegra124_sor_lane_map,
3261 .voltage_swing = tegra124_sor_voltage_swing,
3262 .pre_emphasis = tegra124_sor_pre_emphasis,
3263 .post_cursor = tegra124_sor_post_cursor,
3264 .tx_pu = tegra124_sor_tx_pu,
3053};
3054
3265};
3266
3267static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3268 {
3269 { 0x00, 0x08, 0x12, 0x24 },
3270 { 0x01, 0x0e, 0x1d, },
3271 { 0x01, 0x13, },
3272 { 0x00, },
3273 }, {
3274 { 0x00, 0x08, 0x12, 0x24 },
3275 { 0x00, 0x0e, 0x1d, },
3276 { 0x00, 0x13, },
3277 { 0x00 },
3278 }, {
3279 { 0x00, 0x08, 0x12, 0x24 },
3280 { 0x00, 0x0e, 0x1d, },
3281 { 0x00, 0x13, },
3282 { 0x00, },
3283 }, {
3284 { 0x00, 0x08, 0x12, 0x24 },
3285 { 0x00, 0x0e, 0x1d, },
3286 { 0x00, 0x13, },
3287 { 0x00, },
3288 },
3289};
3290
3291static const struct tegra_sor_soc tegra132_sor = {
3292 .supports_edp = true,
3293 .supports_lvds = true,
3294 .supports_hdmi = false,
3295 .supports_dp = false,
3296 .regs = &tegra124_sor_regs,
3297 .has_nvdisplay = false,
3298 .xbar_cfg = tegra124_sor_xbar_cfg,
3299 .lane_map = tegra124_sor_lane_map,
3300 .voltage_swing = tegra124_sor_voltage_swing,
3301 .pre_emphasis = tegra132_sor_pre_emphasis,
3302 .post_cursor = tegra124_sor_post_cursor,
3303 .tx_pu = tegra124_sor_tx_pu,
3304};
3305
3055static const struct tegra_sor_regs tegra210_sor_regs = {
3056 .head_state0 = 0x05,
3057 .head_state1 = 0x07,
3058 .head_state2 = 0x09,
3059 .head_state3 = 0x0b,
3060 .head_state4 = 0x0d,
3061 .head_state5 = 0x0f,
3062 .pll0 = 0x17,
3063 .pll1 = 0x18,
3064 .pll2 = 0x19,
3065 .pll3 = 0x1a,
3066 .dp_padctl0 = 0x5c,
3067 .dp_padctl2 = 0x73,
3068};
3069
3306static const struct tegra_sor_regs tegra210_sor_regs = {
3307 .head_state0 = 0x05,
3308 .head_state1 = 0x07,
3309 .head_state2 = 0x09,
3310 .head_state3 = 0x0b,
3311 .head_state4 = 0x0d,
3312 .head_state5 = 0x0f,
3313 .pll0 = 0x17,
3314 .pll1 = 0x18,
3315 .pll2 = 0x19,
3316 .pll3 = 0x1a,
3317 .dp_padctl0 = 0x5c,
3318 .dp_padctl2 = 0x73,
3319};
3320
3321static const u8 tegra210_sor_xbar_cfg[5] = {
3322 2, 1, 0, 3, 4
3323};
3324
3070static const struct tegra_sor_soc tegra210_sor = {
3071 .supports_edp = true,
3072 .supports_lvds = false,
3073 .supports_hdmi = false,
3074 .supports_dp = false,
3325static const struct tegra_sor_soc tegra210_sor = {
3326 .supports_edp = true,
3327 .supports_lvds = false,
3328 .supports_hdmi = false,
3329 .supports_dp = false,
3330
3075 .regs = &tegra210_sor_regs,
3076 .has_nvdisplay = false,
3331 .regs = &tegra210_sor_regs,
3332 .has_nvdisplay = false,
3077 .xbar_cfg = tegra124_sor_xbar_cfg,
3078};
3079
3333
3080static const u8 tegra210_sor_xbar_cfg[5] = {
3081 2, 1, 0, 3, 4
3334 .xbar_cfg = tegra210_sor_xbar_cfg,
3082};
3083
3084static const struct tegra_sor_soc tegra210_sor1 = {
3085 .supports_edp = false,
3086 .supports_lvds = false,
3087 .supports_hdmi = true,
3088 .supports_dp = true,
3089
3090 .regs = &tegra210_sor_regs,
3091 .has_nvdisplay = false,
3092
3093 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3094 .settings = tegra210_sor_hdmi_defaults,
3335};
3336
3337static const struct tegra_sor_soc tegra210_sor1 = {
3338 .supports_edp = false,
3339 .supports_lvds = false,
3340 .supports_hdmi = true,
3341 .supports_dp = true,
3342
3343 .regs = &tegra210_sor_regs,
3344 .has_nvdisplay = false,
3345
3346 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3347 .settings = tegra210_sor_hdmi_defaults,
3095
3096 .xbar_cfg = tegra210_sor_xbar_cfg,
3097};
3098
3099static const struct tegra_sor_regs tegra186_sor_regs = {
3100 .head_state0 = 0x151,
3101 .head_state1 = 0x154,
3102 .head_state2 = 0x157,
3103 .head_state3 = 0x15a,

--- 25 unchanged lines hidden (view full) ---

3129 .supports_hdmi = true,
3130 .supports_dp = true,
3131
3132 .regs = &tegra186_sor_regs,
3133 .has_nvdisplay = true,
3134
3135 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3136 .settings = tegra186_sor_hdmi_defaults,
3348 .xbar_cfg = tegra210_sor_xbar_cfg,
3349};
3350
3351static const struct tegra_sor_regs tegra186_sor_regs = {
3352 .head_state0 = 0x151,
3353 .head_state1 = 0x154,
3354 .head_state2 = 0x157,
3355 .head_state3 = 0x15a,

--- 25 unchanged lines hidden (view full) ---

3381 .supports_hdmi = true,
3382 .supports_dp = true,
3383
3384 .regs = &tegra186_sor_regs,
3385 .has_nvdisplay = true,
3386
3387 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3388 .settings = tegra186_sor_hdmi_defaults,
3137
3138 .xbar_cfg = tegra124_sor_xbar_cfg,
3139};
3140
3141static const struct tegra_sor_regs tegra194_sor_regs = {
3142 .head_state0 = 0x151,
3143 .head_state1 = 0x155,
3144 .head_state2 = 0x159,
3145 .head_state3 = 0x15d,

--- 23 unchanged lines hidden (view full) ---

3169};
3170
3171static const struct of_device_id tegra_sor_of_match[] = {
3172 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3173 { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
3174 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3175 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3176 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3389 .xbar_cfg = tegra124_sor_xbar_cfg,
3390};
3391
3392static const struct tegra_sor_regs tegra194_sor_regs = {
3393 .head_state0 = 0x151,
3394 .head_state1 = 0x155,
3395 .head_state2 = 0x159,
3396 .head_state3 = 0x15d,

--- 23 unchanged lines hidden (view full) ---

3420};
3421
3422static const struct of_device_id tegra_sor_of_match[] = {
3423 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3424 { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
3425 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3426 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3427 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3428 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3177 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3178 { },
3179};
3180MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3181
3182static int tegra_sor_parse_dt(struct tegra_sor *sor)
3183{
3184 struct device_node *np = sor->dev->of_node;

--- 403 unchanged lines hidden --- 		3429 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3430 { },
3431};
3432MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3433
3434static int tegra_sor_parse_dt(struct tegra_sor *sor)
3435{
3436 struct device_node *np = sor->dev->of_node;

--- 403 unchanged lines hidden ---