1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/debugfs.h> 9 #include <linux/gpio.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/reset.h> 17 18 #include <soc/tegra/pmc.h> 19 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_debugfs.h> 22 #include <drm/drm_dp_helper.h> 23 #include <drm/drm_file.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_scdc_helper.h> 26 27 #include "dc.h" 28 #include "dp.h" 29 #include "drm.h" 30 #include "hda.h" 31 #include "sor.h" 32 #include "trace.h" 33 34 #define SOR_REKEY 0x38 35 36 struct tegra_sor_hdmi_settings { 37 unsigned long frequency; 38 39 u8 vcocap; 40 u8 filter; 41 u8 ichpmp; 42 u8 loadadj; 43 u8 tmds_termadj; 44 u8 tx_pu_value; 45 u8 bg_temp_coef; 46 u8 bg_vref_level; 47 u8 avdd10_level; 48 u8 avdd14_level; 49 u8 sparepll; 50 51 u8 drive_current[4]; 52 u8 preemphasis[4]; 53 }; 54 55 #if 1 56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 57 { 58 .frequency = 54000000, 59 .vcocap = 0x0, 60 .filter = 0x0, 61 .ichpmp = 0x1, 62 .loadadj = 0x3, 63 .tmds_termadj = 0x9, 64 .tx_pu_value = 0x10, 65 .bg_temp_coef = 0x3, 66 .bg_vref_level = 0x8, 67 .avdd10_level = 0x4, 68 .avdd14_level = 0x4, 69 .sparepll = 0x0, 70 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 71 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 72 }, { 73 .frequency = 75000000, 74 .vcocap = 0x3, 75 .filter = 0x0, 76 .ichpmp = 0x1, 77 .loadadj = 0x3, 78 .tmds_termadj = 0x9, 79 .tx_pu_value = 0x40, 80 .bg_temp_coef = 0x3, 81 .bg_vref_level = 0x8, 82 .avdd10_level = 0x4, 83 .avdd14_level = 0x4, 84 .sparepll = 0x0, 85 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 86 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 87 }, { 88 .frequency = 150000000, 89 .vcocap = 0x3, 90 .filter = 0x0, 91 .ichpmp = 0x1, 92 .loadadj = 0x3, 93 .tmds_termadj = 0x9, 94 .tx_pu_value = 0x66, 95 .bg_temp_coef = 0x3, 96 .bg_vref_level = 0x8, 97 .avdd10_level = 0x4, 98 .avdd14_level = 0x4, 99 .sparepll = 0x0, 100 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 101 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 102 }, { 103 .frequency = 300000000, 104 .vcocap = 0x3, 105 .filter = 0x0, 106 .ichpmp = 0x1, 107 .loadadj = 0x3, 108 .tmds_termadj = 0x9, 109 .tx_pu_value = 0x66, 110 .bg_temp_coef = 0x3, 111 .bg_vref_level = 0xa, 112 .avdd10_level = 0x4, 113 .avdd14_level = 0x4, 114 .sparepll = 0x0, 115 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 116 .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, 117 }, { 118 .frequency = 600000000, 119 .vcocap = 0x3, 120 .filter = 0x0, 121 .ichpmp = 0x1, 122 .loadadj = 0x3, 123 .tmds_termadj = 0x9, 124 .tx_pu_value = 0x66, 125 .bg_temp_coef = 0x3, 126 .bg_vref_level = 0x8, 127 .avdd10_level = 0x4, 128 .avdd14_level = 0x4, 129 .sparepll = 0x0, 130 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 131 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 132 }, 133 }; 134 #else 135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 136 { 137 .frequency = 75000000, 138 .vcocap = 0x3, 139 .filter = 0x0, 140 .ichpmp = 0x1, 141 .loadadj = 0x3, 142 .tmds_termadj = 0x9, 143 .tx_pu_value = 0x40, 144 .bg_temp_coef = 0x3, 145 .bg_vref_level = 0x8, 146 .avdd10_level = 0x4, 147 .avdd14_level = 0x4, 148 .sparepll = 0x0, 149 .drive_current = { 0x29, 0x29, 0x29, 0x29 }, 150 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 151 }, { 152 .frequency = 150000000, 153 .vcocap = 0x3, 154 .filter = 0x0, 155 .ichpmp = 0x1, 156 .loadadj = 0x3, 157 .tmds_termadj = 0x9, 158 .tx_pu_value = 0x66, 159 .bg_temp_coef = 0x3, 160 .bg_vref_level = 0x8, 161 .avdd10_level = 0x4, 162 .avdd14_level = 0x4, 163 .sparepll = 0x0, 164 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 165 .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, 166 }, { 167 .frequency = 300000000, 168 .vcocap = 0x3, 169 .filter = 0x0, 170 .ichpmp = 0x6, 171 .loadadj = 0x3, 172 .tmds_termadj = 0x9, 173 .tx_pu_value = 0x66, 174 .bg_temp_coef = 0x3, 175 .bg_vref_level = 0xf, 176 .avdd10_level = 0x4, 177 .avdd14_level = 0x4, 178 .sparepll = 0x0, 179 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 180 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, 181 }, { 182 .frequency = 600000000, 183 .vcocap = 0x3, 184 .filter = 0x0, 185 .ichpmp = 0xa, 186 .loadadj = 0x3, 187 .tmds_termadj = 0xb, 188 .tx_pu_value = 0x66, 189 .bg_temp_coef = 0x3, 190 .bg_vref_level = 0xe, 191 .avdd10_level = 0x4, 192 .avdd14_level = 0x4, 193 .sparepll = 0x0, 194 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, 195 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, 196 }, 197 }; 198 #endif 199 200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = { 201 { 202 .frequency = 54000000, 203 .vcocap = 0, 204 .filter = 5, 205 .ichpmp = 5, 206 .loadadj = 3, 207 .tmds_termadj = 0xf, 208 .tx_pu_value = 0, 209 .bg_temp_coef = 3, 210 .bg_vref_level = 8, 211 .avdd10_level = 4, 212 .avdd14_level = 4, 213 .sparepll = 0x54, 214 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 215 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 216 }, { 217 .frequency = 75000000, 218 .vcocap = 1, 219 .filter = 5, 220 .ichpmp = 5, 221 .loadadj = 3, 222 .tmds_termadj = 0xf, 223 .tx_pu_value = 0, 224 .bg_temp_coef = 3, 225 .bg_vref_level = 8, 226 .avdd10_level = 4, 227 .avdd14_level = 4, 228 .sparepll = 0x44, 229 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 230 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 231 }, { 232 .frequency = 150000000, 233 .vcocap = 3, 234 .filter = 5, 235 .ichpmp = 5, 236 .loadadj = 3, 237 .tmds_termadj = 15, 238 .tx_pu_value = 0x66 /* 0 */, 239 .bg_temp_coef = 3, 240 .bg_vref_level = 8, 241 .avdd10_level = 4, 242 .avdd14_level = 4, 243 .sparepll = 0x00, /* 0x34 */ 244 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 245 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 246 }, { 247 .frequency = 300000000, 248 .vcocap = 3, 249 .filter = 5, 250 .ichpmp = 5, 251 .loadadj = 3, 252 .tmds_termadj = 15, 253 .tx_pu_value = 64, 254 .bg_temp_coef = 3, 255 .bg_vref_level = 8, 256 .avdd10_level = 4, 257 .avdd14_level = 4, 258 .sparepll = 0x34, 259 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 260 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 261 }, { 262 .frequency = 600000000, 263 .vcocap = 3, 264 .filter = 5, 265 .ichpmp = 5, 266 .loadadj = 3, 267 .tmds_termadj = 12, 268 .tx_pu_value = 96, 269 .bg_temp_coef = 3, 270 .bg_vref_level = 8, 271 .avdd10_level = 4, 272 .avdd14_level = 4, 273 .sparepll = 0x34, 274 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 275 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 276 } 277 }; 278 279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = { 280 { 281 .frequency = 54000000, 282 .vcocap = 0, 283 .filter = 5, 284 .ichpmp = 5, 285 .loadadj = 3, 286 .tmds_termadj = 0xf, 287 .tx_pu_value = 0, 288 .bg_temp_coef = 3, 289 .bg_vref_level = 8, 290 .avdd10_level = 4, 291 .avdd14_level = 4, 292 .sparepll = 0x54, 293 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 294 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 295 }, { 296 .frequency = 75000000, 297 .vcocap = 1, 298 .filter = 5, 299 .ichpmp = 5, 300 .loadadj = 3, 301 .tmds_termadj = 0xf, 302 .tx_pu_value = 0, 303 .bg_temp_coef = 3, 304 .bg_vref_level = 8, 305 .avdd10_level = 4, 306 .avdd14_level = 4, 307 .sparepll = 0x44, 308 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 309 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 310 }, { 311 .frequency = 150000000, 312 .vcocap = 3, 313 .filter = 5, 314 .ichpmp = 5, 315 .loadadj = 3, 316 .tmds_termadj = 15, 317 .tx_pu_value = 0x66 /* 0 */, 318 .bg_temp_coef = 3, 319 .bg_vref_level = 8, 320 .avdd10_level = 4, 321 .avdd14_level = 4, 322 .sparepll = 0x00, /* 0x34 */ 323 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 324 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 325 }, { 326 .frequency = 300000000, 327 .vcocap = 3, 328 .filter = 5, 329 .ichpmp = 5, 330 .loadadj = 3, 331 .tmds_termadj = 15, 332 .tx_pu_value = 64, 333 .bg_temp_coef = 3, 334 .bg_vref_level = 8, 335 .avdd10_level = 4, 336 .avdd14_level = 4, 337 .sparepll = 0x34, 338 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 339 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 340 }, { 341 .frequency = 600000000, 342 .vcocap = 3, 343 .filter = 5, 344 .ichpmp = 5, 345 .loadadj = 3, 346 .tmds_termadj = 12, 347 .tx_pu_value = 96, 348 .bg_temp_coef = 3, 349 .bg_vref_level = 8, 350 .avdd10_level = 4, 351 .avdd14_level = 4, 352 .sparepll = 0x34, 353 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 354 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 355 } 356 }; 357 358 struct tegra_sor_regs { 359 unsigned int head_state0; 360 unsigned int head_state1; 361 unsigned int head_state2; 362 unsigned int head_state3; 363 unsigned int head_state4; 364 unsigned int head_state5; 365 unsigned int pll0; 366 unsigned int pll1; 367 unsigned int pll2; 368 unsigned int pll3; 369 unsigned int dp_padctl0; 370 unsigned int dp_padctl2; 371 }; 372 373 struct tegra_sor_soc { 374 bool supports_edp; 375 bool supports_lvds; 376 bool supports_hdmi; 377 bool supports_dp; 378 379 const struct tegra_sor_regs *regs; 380 bool has_nvdisplay; 381 382 const struct tegra_sor_hdmi_settings *settings; 383 unsigned int num_settings; 384 385 const u8 *xbar_cfg; 386 const u8 *lane_map; 387 388 const u8 (*voltage_swing)[4][4]; 389 const u8 (*pre_emphasis)[4][4]; 390 const u8 (*post_cursor)[4][4]; 391 const u8 (*tx_pu)[4][4]; 392 }; 393 394 struct tegra_sor; 395 396 struct tegra_sor_ops { 397 const char *name; 398 int (*probe)(struct tegra_sor *sor); 399 int (*remove)(struct tegra_sor *sor); 400 }; 401 402 struct tegra_sor { 403 struct host1x_client client; 404 struct tegra_output output; 405 struct device *dev; 406 407 const struct tegra_sor_soc *soc; 408 void __iomem *regs; 409 unsigned int index; 410 unsigned int irq; 411 412 struct reset_control *rst; 413 struct clk *clk_parent; 414 struct clk *clk_safe; 415 struct clk *clk_out; 416 struct clk *clk_pad; 417 struct clk *clk_dp; 418 struct clk *clk; 419 420 u8 xbar_cfg[5]; 421 422 struct drm_dp_link link; 423 struct drm_dp_aux *aux; 424 425 struct drm_info_list *debugfs_files; 426 427 const struct tegra_sor_ops *ops; 428 enum tegra_io_pad pad; 429 430 /* for HDMI 2.0 */ 431 struct tegra_sor_hdmi_settings *settings; 432 unsigned int num_settings; 433 434 struct regulator *avdd_io_supply; 435 struct regulator *vdd_pll_supply; 436 struct regulator *hdmi_supply; 437 438 struct delayed_work scdc; 439 bool scdc_enabled; 440 441 struct tegra_hda_format format; 442 }; 443 444 struct tegra_sor_state { 445 struct drm_connector_state base; 446 447 unsigned int link_speed; 448 unsigned long pclk; 449 unsigned int bpc; 450 }; 451 452 static inline struct tegra_sor_state * 453 to_sor_state(struct drm_connector_state *state) 454 { 455 return container_of(state, struct tegra_sor_state, base); 456 } 457 458 struct tegra_sor_config { 459 u32 bits_per_pixel; 460 461 u32 active_polarity; 462 u32 active_count; 463 u32 tu_size; 464 u32 active_frac; 465 u32 watermark; 466 467 u32 hblank_symbols; 468 u32 vblank_symbols; 469 }; 470 471 static inline struct tegra_sor * 472 host1x_client_to_sor(struct host1x_client *client) 473 { 474 return container_of(client, struct tegra_sor, client); 475 } 476 477 static inline struct tegra_sor *to_sor(struct tegra_output *output) 478 { 479 return container_of(output, struct tegra_sor, output); 480 } 481 482 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) 483 { 484 u32 value = readl(sor->regs + (offset << 2)); 485 486 trace_sor_readl(sor->dev, offset, value); 487 488 return value; 489 } 490 491 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, 492 unsigned int offset) 493 { 494 trace_sor_writel(sor->dev, offset, value); 495 writel(value, sor->regs + (offset << 2)); 496 } 497 498 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) 499 { 500 int err; 501 502 clk_disable_unprepare(sor->clk); 503 504 err = clk_set_parent(sor->clk_out, parent); 505 if (err < 0) 506 return err; 507 508 err = clk_prepare_enable(sor->clk); 509 if (err < 0) 510 return err; 511 512 return 0; 513 } 514 515 struct tegra_clk_sor_pad { 516 struct clk_hw hw; 517 struct tegra_sor *sor; 518 }; 519 520 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw) 521 { 522 return container_of(hw, struct tegra_clk_sor_pad, hw); 523 } 524 525 static const char * const tegra_clk_sor_pad_parents[] = { 526 "pll_d2_out0", "pll_dp" 527 }; 528 529 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) 530 { 531 struct tegra_clk_sor_pad *pad = to_pad(hw); 532 struct tegra_sor *sor = pad->sor; 533 u32 value; 534 535 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 536 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 537 538 switch (index) { 539 case 0: 540 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 541 break; 542 543 case 1: 544 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 545 break; 546 } 547 548 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 549 550 return 0; 551 } 552 553 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw) 554 { 555 struct tegra_clk_sor_pad *pad = to_pad(hw); 556 struct tegra_sor *sor = pad->sor; 557 u8 parent = U8_MAX; 558 u32 value; 559 560 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 561 562 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { 563 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: 564 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK: 565 parent = 0; 566 break; 567 568 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK: 569 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK: 570 parent = 1; 571 break; 572 } 573 574 return parent; 575 } 576 577 static const struct clk_ops tegra_clk_sor_pad_ops = { 578 .set_parent = tegra_clk_sor_pad_set_parent, 579 .get_parent = tegra_clk_sor_pad_get_parent, 580 }; 581 582 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, 583 const char *name) 584 { 585 struct tegra_clk_sor_pad *pad; 586 struct clk_init_data init; 587 struct clk *clk; 588 589 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); 590 if (!pad) 591 return ERR_PTR(-ENOMEM); 592 593 pad->sor = sor; 594 595 init.name = name; 596 init.flags = 0; 597 init.parent_names = tegra_clk_sor_pad_parents; 598 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents); 599 init.ops = &tegra_clk_sor_pad_ops; 600 601 pad->hw.init = &init; 602 603 clk = devm_clk_register(sor->dev, &pad->hw); 604 605 return clk; 606 } 607 608 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) 609 { 610 unsigned long timeout; 611 u32 value; 612 613 /* 614 * Clear or set the PD_TXD bit corresponding to each lane, depending 615 * on whether it is used or not. 616 */ 617 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 618 619 if (lanes <= 2) 620 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | 621 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); 622 else 623 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | 624 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); 625 626 if (lanes <= 1) 627 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); 628 else 629 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); 630 631 if (lanes == 0) 632 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); 633 else 634 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); 635 636 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 637 638 /* start lane sequencer */ 639 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 640 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 641 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 642 643 timeout = jiffies + msecs_to_jiffies(250); 644 645 while (time_before(jiffies, timeout)) { 646 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 647 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 648 break; 649 650 usleep_range(250, 1000); 651 } 652 653 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 654 return -ETIMEDOUT; 655 656 return 0; 657 } 658 659 static int tegra_sor_power_down_lanes(struct tegra_sor *sor) 660 { 661 unsigned long timeout; 662 u32 value; 663 664 /* power down all lanes */ 665 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 666 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 667 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 668 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 669 670 /* start lane sequencer */ 671 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 672 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 673 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 674 675 timeout = jiffies + msecs_to_jiffies(250); 676 677 while (time_before(jiffies, timeout)) { 678 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 679 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 680 break; 681 682 usleep_range(25, 100); 683 } 684 685 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 686 return -ETIMEDOUT; 687 688 return 0; 689 } 690 691 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) 692 { 693 u32 value; 694 695 /* pre-charge all used lanes */ 696 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 697 698 if (lanes <= 2) 699 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | 700 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); 701 else 702 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | 703 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); 704 705 if (lanes <= 1) 706 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); 707 else 708 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); 709 710 if (lanes == 0) 711 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); 712 else 713 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); 714 715 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 716 717 usleep_range(15, 100); 718 719 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 720 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 721 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 722 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 723 } 724 725 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) 726 { 727 u32 mask = 0x08, adj = 0, value; 728 729 /* enable pad calibration logic */ 730 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 731 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 732 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 733 734 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 735 value |= SOR_PLL1_TMDS_TERM; 736 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 737 738 while (mask) { 739 adj |= mask; 740 741 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 742 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 743 value |= SOR_PLL1_TMDS_TERMADJ(adj); 744 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 745 746 usleep_range(100, 200); 747 748 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 749 if (value & SOR_PLL1_TERM_COMPOUT) 750 adj &= ~mask; 751 752 mask >>= 1; 753 } 754 755 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 756 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 757 value |= SOR_PLL1_TMDS_TERMADJ(adj); 758 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 759 760 /* disable pad calibration logic */ 761 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 762 value |= SOR_DP_PADCTL_PAD_CAL_PD; 763 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 764 } 765 766 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link) 767 { 768 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); 769 u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0; 770 const struct tegra_sor_soc *soc = sor->soc; 771 u32 pattern = 0, tx_pu = 0, value; 772 unsigned int i; 773 774 for (value = 0, i = 0; i < link->lanes; i++) { 775 u8 vs = link->train.request.voltage_swing[i]; 776 u8 pe = link->train.request.pre_emphasis[i]; 777 u8 pc = link->train.request.post_cursor[i]; 778 u8 shift = sor->soc->lane_map[i] << 3; 779 780 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift; 781 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift; 782 post_cursor |= soc->post_cursor[pc][vs][pe] << shift; 783 784 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) 785 tx_pu = sor->soc->tx_pu[pc][vs][pe]; 786 787 switch (link->train.pattern) { 788 case DP_TRAINING_PATTERN_DISABLE: 789 value = SOR_DP_TPG_SCRAMBLER_GALIOS | 790 SOR_DP_TPG_PATTERN_NONE; 791 break; 792 793 case DP_TRAINING_PATTERN_1: 794 value = SOR_DP_TPG_SCRAMBLER_NONE | 795 SOR_DP_TPG_PATTERN_TRAIN1; 796 break; 797 798 case DP_TRAINING_PATTERN_2: 799 value = SOR_DP_TPG_SCRAMBLER_NONE | 800 SOR_DP_TPG_PATTERN_TRAIN2; 801 break; 802 803 case DP_TRAINING_PATTERN_3: 804 value = SOR_DP_TPG_SCRAMBLER_NONE | 805 SOR_DP_TPG_PATTERN_TRAIN3; 806 break; 807 808 default: 809 return -EINVAL; 810 } 811 812 if (link->caps.channel_coding) 813 value |= SOR_DP_TPG_CHANNEL_CODING; 814 815 pattern = pattern << 8 | value; 816 } 817 818 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0); 819 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0); 820 821 if (link->caps.tps3_supported) 822 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0); 823 824 tegra_sor_writel(sor, pattern, SOR_DP_TPG); 825 826 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 827 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 828 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 829 value |= SOR_DP_PADCTL_TX_PU(tx_pu); 830 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 831 832 usleep_range(20, 100); 833 834 return 0; 835 } 836 837 static int tegra_sor_dp_link_configure(struct drm_dp_link *link) 838 { 839 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); 840 unsigned int rate, lanes; 841 u32 value; 842 int err; 843 844 rate = drm_dp_link_rate_to_bw_code(link->rate); 845 lanes = link->lanes; 846 847 /* configure link speed and lane count */ 848 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 849 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 850 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 851 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 852 853 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 854 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 855 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 856 857 if (link->caps.enhanced_framing) 858 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 859 860 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 861 862 usleep_range(400, 1000); 863 864 /* configure load pulse position adjustment */ 865 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 866 value &= ~SOR_PLL1_LOADADJ_MASK; 867 868 switch (rate) { 869 case DP_LINK_BW_1_62: 870 value |= SOR_PLL1_LOADADJ(0x3); 871 break; 872 873 case DP_LINK_BW_2_7: 874 value |= SOR_PLL1_LOADADJ(0x4); 875 break; 876 877 case DP_LINK_BW_5_4: 878 value |= SOR_PLL1_LOADADJ(0x6); 879 break; 880 } 881 882 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 883 884 /* use alternate scrambler reset for eDP */ 885 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 886 887 if (link->edp == 0) 888 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 889 else 890 value |= SOR_DP_SPARE_PANEL_INTERNAL; 891 892 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 893 894 err = tegra_sor_power_down_lanes(sor); 895 if (err < 0) { 896 dev_err(sor->dev, "failed to power down lanes: %d\n", err); 897 return err; 898 } 899 900 /* power up and pre-charge lanes */ 901 err = tegra_sor_power_up_lanes(sor, lanes); 902 if (err < 0) { 903 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", 904 lanes, (lanes != 1) ? "s" : "", err); 905 return err; 906 } 907 908 tegra_sor_dp_precharge(sor, lanes); 909 910 return 0; 911 } 912 913 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = { 914 .apply_training = tegra_sor_dp_link_apply_training, 915 .configure = tegra_sor_dp_link_configure, 916 }; 917 918 static void tegra_sor_super_update(struct tegra_sor *sor) 919 { 920 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 921 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); 922 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 923 } 924 925 static void tegra_sor_update(struct tegra_sor *sor) 926 { 927 tegra_sor_writel(sor, 0, SOR_STATE0); 928 tegra_sor_writel(sor, 1, SOR_STATE0); 929 tegra_sor_writel(sor, 0, SOR_STATE0); 930 } 931 932 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 933 { 934 u32 value; 935 936 value = tegra_sor_readl(sor, SOR_PWM_DIV); 937 value &= ~SOR_PWM_DIV_MASK; 938 value |= 0x400; /* period */ 939 tegra_sor_writel(sor, value, SOR_PWM_DIV); 940 941 value = tegra_sor_readl(sor, SOR_PWM_CTL); 942 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 943 value |= 0x400; /* duty cycle */ 944 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 945 value |= SOR_PWM_CTL_TRIGGER; 946 tegra_sor_writel(sor, value, SOR_PWM_CTL); 947 948 timeout = jiffies + msecs_to_jiffies(timeout); 949 950 while (time_before(jiffies, timeout)) { 951 value = tegra_sor_readl(sor, SOR_PWM_CTL); 952 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 953 return 0; 954 955 usleep_range(25, 100); 956 } 957 958 return -ETIMEDOUT; 959 } 960 961 static int tegra_sor_attach(struct tegra_sor *sor) 962 { 963 unsigned long value, timeout; 964 965 /* wake up in normal mode */ 966 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 967 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 968 value |= SOR_SUPER_STATE_MODE_NORMAL; 969 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 970 tegra_sor_super_update(sor); 971 972 /* attach */ 973 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 974 value |= SOR_SUPER_STATE_ATTACHED; 975 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 976 tegra_sor_super_update(sor); 977 978 timeout = jiffies + msecs_to_jiffies(250); 979 980 while (time_before(jiffies, timeout)) { 981 value = tegra_sor_readl(sor, SOR_TEST); 982 if ((value & SOR_TEST_ATTACHED) != 0) 983 return 0; 984 985 usleep_range(25, 100); 986 } 987 988 return -ETIMEDOUT; 989 } 990 991 static int tegra_sor_wakeup(struct tegra_sor *sor) 992 { 993 unsigned long value, timeout; 994 995 timeout = jiffies + msecs_to_jiffies(250); 996 997 /* wait for head to wake up */ 998 while (time_before(jiffies, timeout)) { 999 value = tegra_sor_readl(sor, SOR_TEST); 1000 value &= SOR_TEST_HEAD_MODE_MASK; 1001 1002 if (value == SOR_TEST_HEAD_MODE_AWAKE) 1003 return 0; 1004 1005 usleep_range(25, 100); 1006 } 1007 1008 return -ETIMEDOUT; 1009 } 1010 1011 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 1012 { 1013 u32 value; 1014 1015 value = tegra_sor_readl(sor, SOR_PWR); 1016 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 1017 tegra_sor_writel(sor, value, SOR_PWR); 1018 1019 timeout = jiffies + msecs_to_jiffies(timeout); 1020 1021 while (time_before(jiffies, timeout)) { 1022 value = tegra_sor_readl(sor, SOR_PWR); 1023 if ((value & SOR_PWR_TRIGGER) == 0) 1024 return 0; 1025 1026 usleep_range(25, 100); 1027 } 1028 1029 return -ETIMEDOUT; 1030 } 1031 1032 struct tegra_sor_params { 1033 /* number of link clocks per line */ 1034 unsigned int num_clocks; 1035 /* ratio between input and output */ 1036 u64 ratio; 1037 /* precision factor */ 1038 u64 precision; 1039 1040 unsigned int active_polarity; 1041 unsigned int active_count; 1042 unsigned int active_frac; 1043 unsigned int tu_size; 1044 unsigned int error; 1045 }; 1046 1047 static int tegra_sor_compute_params(struct tegra_sor *sor, 1048 struct tegra_sor_params *params, 1049 unsigned int tu_size) 1050 { 1051 u64 active_sym, active_count, frac, approx; 1052 u32 active_polarity, active_frac = 0; 1053 const u64 f = params->precision; 1054 s64 error; 1055 1056 active_sym = params->ratio * tu_size; 1057 active_count = div_u64(active_sym, f) * f; 1058 frac = active_sym - active_count; 1059 1060 /* fraction < 0.5 */ 1061 if (frac >= (f / 2)) { 1062 active_polarity = 1; 1063 frac = f - frac; 1064 } else { 1065 active_polarity = 0; 1066 } 1067 1068 if (frac != 0) { 1069 frac = div_u64(f * f, frac); /* 1/fraction */ 1070 if (frac <= (15 * f)) { 1071 active_frac = div_u64(frac, f); 1072 1073 /* round up */ 1074 if (active_polarity) 1075 active_frac++; 1076 } else { 1077 active_frac = active_polarity ? 1 : 15; 1078 } 1079 } 1080 1081 if (active_frac == 1) 1082 active_polarity = 0; 1083 1084 if (active_polarity == 1) { 1085 if (active_frac) { 1086 approx = active_count + (active_frac * (f - 1)) * f; 1087 approx = div_u64(approx, active_frac * f); 1088 } else { 1089 approx = active_count + f; 1090 } 1091 } else { 1092 if (active_frac) 1093 approx = active_count + div_u64(f, active_frac); 1094 else 1095 approx = active_count; 1096 } 1097 1098 error = div_s64(active_sym - approx, tu_size); 1099 error *= params->num_clocks; 1100 1101 if (error <= 0 && abs(error) < params->error) { 1102 params->active_count = div_u64(active_count, f); 1103 params->active_polarity = active_polarity; 1104 params->active_frac = active_frac; 1105 params->error = abs(error); 1106 params->tu_size = tu_size; 1107 1108 if (error == 0) 1109 return true; 1110 } 1111 1112 return false; 1113 } 1114 1115 static int tegra_sor_compute_config(struct tegra_sor *sor, 1116 const struct drm_display_mode *mode, 1117 struct tegra_sor_config *config, 1118 struct drm_dp_link *link) 1119 { 1120 const u64 f = 100000, link_rate = link->rate * 1000; 1121 const u64 pclk = mode->clock * 1000; 1122 u64 input, output, watermark, num; 1123 struct tegra_sor_params params; 1124 u32 num_syms_per_line; 1125 unsigned int i; 1126 1127 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel) 1128 return -EINVAL; 1129 1130 input = pclk * config->bits_per_pixel; 1131 output = link_rate * 8 * link->lanes; 1132 1133 if (input >= output) 1134 return -ERANGE; 1135 1136 memset(¶ms, 0, sizeof(params)); 1137 params.ratio = div64_u64(input * f, output); 1138 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 1139 params.precision = f; 1140 params.error = 64 * f; 1141 params.tu_size = 64; 1142 1143 for (i = params.tu_size; i >= 32; i--) 1144 if (tegra_sor_compute_params(sor, ¶ms, i)) 1145 break; 1146 1147 if (params.active_frac == 0) { 1148 config->active_polarity = 0; 1149 config->active_count = params.active_count; 1150 1151 if (!params.active_polarity) 1152 config->active_count--; 1153 1154 config->tu_size = params.tu_size; 1155 config->active_frac = 1; 1156 } else { 1157 config->active_polarity = params.active_polarity; 1158 config->active_count = params.active_count; 1159 config->active_frac = params.active_frac; 1160 config->tu_size = params.tu_size; 1161 } 1162 1163 dev_dbg(sor->dev, 1164 "polarity: %d active count: %d tu size: %d active frac: %d\n", 1165 config->active_polarity, config->active_count, 1166 config->tu_size, config->active_frac); 1167 1168 watermark = params.ratio * config->tu_size * (f - params.ratio); 1169 watermark = div_u64(watermark, f); 1170 1171 watermark = div_u64(watermark + params.error, f); 1172 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 1173 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 1174 (link->lanes * 8); 1175 1176 if (config->watermark > 30) { 1177 config->watermark = 30; 1178 dev_err(sor->dev, 1179 "unable to compute TU size, forcing watermark to %u\n", 1180 config->watermark); 1181 } else if (config->watermark > num_syms_per_line) { 1182 config->watermark = num_syms_per_line; 1183 dev_err(sor->dev, "watermark too high, forcing to %u\n", 1184 config->watermark); 1185 } 1186 1187 /* compute the number of symbols per horizontal blanking interval */ 1188 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 1189 config->hblank_symbols = div_u64(num, pclk); 1190 1191 if (link->caps.enhanced_framing) 1192 config->hblank_symbols -= 3; 1193 1194 config->hblank_symbols -= 12 / link->lanes; 1195 1196 /* compute the number of symbols per vertical blanking interval */ 1197 num = (mode->hdisplay - 25) * link_rate; 1198 config->vblank_symbols = div_u64(num, pclk); 1199 config->vblank_symbols -= 36 / link->lanes + 4; 1200 1201 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 1202 config->vblank_symbols); 1203 1204 return 0; 1205 } 1206 1207 static void tegra_sor_apply_config(struct tegra_sor *sor, 1208 const struct tegra_sor_config *config) 1209 { 1210 u32 value; 1211 1212 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1213 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 1214 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); 1215 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1216 1217 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); 1218 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 1219 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); 1220 1221 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 1222 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); 1223 1224 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 1225 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); 1226 1227 if (config->active_polarity) 1228 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1229 else 1230 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1231 1232 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 1233 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 1234 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); 1235 1236 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1237 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 1238 value |= config->hblank_symbols & 0xffff; 1239 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1240 1241 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1242 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 1243 value |= config->vblank_symbols & 0xffff; 1244 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1245 } 1246 1247 static void tegra_sor_mode_set(struct tegra_sor *sor, 1248 const struct drm_display_mode *mode, 1249 struct tegra_sor_state *state) 1250 { 1251 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 1252 unsigned int vbe, vse, hbe, hse, vbs, hbs; 1253 u32 value; 1254 1255 value = tegra_sor_readl(sor, SOR_STATE1); 1256 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; 1257 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1258 value &= ~SOR_STATE_ASY_OWNER_MASK; 1259 1260 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | 1261 SOR_STATE_ASY_OWNER(dc->pipe + 1); 1262 1263 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1264 value &= ~SOR_STATE_ASY_HSYNCPOL; 1265 1266 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1267 value |= SOR_STATE_ASY_HSYNCPOL; 1268 1269 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1270 value &= ~SOR_STATE_ASY_VSYNCPOL; 1271 1272 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1273 value |= SOR_STATE_ASY_VSYNCPOL; 1274 1275 switch (state->bpc) { 1276 case 16: 1277 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; 1278 break; 1279 1280 case 12: 1281 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; 1282 break; 1283 1284 case 10: 1285 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; 1286 break; 1287 1288 case 8: 1289 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1290 break; 1291 1292 case 6: 1293 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 1294 break; 1295 1296 default: 1297 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1298 break; 1299 } 1300 1301 tegra_sor_writel(sor, value, SOR_STATE1); 1302 1303 /* 1304 * TODO: The video timing programming below doesn't seem to match the 1305 * register definitions. 1306 */ 1307 1308 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 1309 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); 1310 1311 /* sync end = sync width - 1 */ 1312 vse = mode->vsync_end - mode->vsync_start - 1; 1313 hse = mode->hsync_end - mode->hsync_start - 1; 1314 1315 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 1316 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); 1317 1318 /* blank end = sync end + back porch */ 1319 vbe = vse + (mode->vtotal - mode->vsync_end); 1320 hbe = hse + (mode->htotal - mode->hsync_end); 1321 1322 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 1323 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); 1324 1325 /* blank start = blank end + active */ 1326 vbs = vbe + mode->vdisplay; 1327 hbs = hbe + mode->hdisplay; 1328 1329 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 1330 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); 1331 1332 /* XXX interlacing support */ 1333 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); 1334 } 1335 1336 static int tegra_sor_detach(struct tegra_sor *sor) 1337 { 1338 unsigned long value, timeout; 1339 1340 /* switch to safe mode */ 1341 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1342 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 1343 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1344 tegra_sor_super_update(sor); 1345 1346 timeout = jiffies + msecs_to_jiffies(250); 1347 1348 while (time_before(jiffies, timeout)) { 1349 value = tegra_sor_readl(sor, SOR_PWR); 1350 if (value & SOR_PWR_MODE_SAFE) 1351 break; 1352 } 1353 1354 if ((value & SOR_PWR_MODE_SAFE) == 0) 1355 return -ETIMEDOUT; 1356 1357 /* go to sleep */ 1358 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1359 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 1360 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1361 tegra_sor_super_update(sor); 1362 1363 /* detach */ 1364 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1365 value &= ~SOR_SUPER_STATE_ATTACHED; 1366 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1367 tegra_sor_super_update(sor); 1368 1369 timeout = jiffies + msecs_to_jiffies(250); 1370 1371 while (time_before(jiffies, timeout)) { 1372 value = tegra_sor_readl(sor, SOR_TEST); 1373 if ((value & SOR_TEST_ATTACHED) == 0) 1374 break; 1375 1376 usleep_range(25, 100); 1377 } 1378 1379 if ((value & SOR_TEST_ATTACHED) != 0) 1380 return -ETIMEDOUT; 1381 1382 return 0; 1383 } 1384 1385 static int tegra_sor_power_down(struct tegra_sor *sor) 1386 { 1387 unsigned long value, timeout; 1388 int err; 1389 1390 value = tegra_sor_readl(sor, SOR_PWR); 1391 value &= ~SOR_PWR_NORMAL_STATE_PU; 1392 value |= SOR_PWR_TRIGGER; 1393 tegra_sor_writel(sor, value, SOR_PWR); 1394 1395 timeout = jiffies + msecs_to_jiffies(250); 1396 1397 while (time_before(jiffies, timeout)) { 1398 value = tegra_sor_readl(sor, SOR_PWR); 1399 if ((value & SOR_PWR_TRIGGER) == 0) 1400 return 0; 1401 1402 usleep_range(25, 100); 1403 } 1404 1405 if ((value & SOR_PWR_TRIGGER) != 0) 1406 return -ETIMEDOUT; 1407 1408 /* switch to safe parent clock */ 1409 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1410 if (err < 0) { 1411 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1412 return err; 1413 } 1414 1415 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1416 value |= SOR_PLL2_PORT_POWERDOWN; 1417 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1418 1419 usleep_range(20, 100); 1420 1421 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1422 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1423 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1424 1425 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1426 value |= SOR_PLL2_SEQ_PLLCAPPD; 1427 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1428 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1429 1430 usleep_range(20, 100); 1431 1432 return 0; 1433 } 1434 1435 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 1436 { 1437 u32 value; 1438 1439 timeout = jiffies + msecs_to_jiffies(timeout); 1440 1441 while (time_before(jiffies, timeout)) { 1442 value = tegra_sor_readl(sor, SOR_CRCA); 1443 if (value & SOR_CRCA_VALID) 1444 return 0; 1445 1446 usleep_range(100, 200); 1447 } 1448 1449 return -ETIMEDOUT; 1450 } 1451 1452 static int tegra_sor_show_crc(struct seq_file *s, void *data) 1453 { 1454 struct drm_info_node *node = s->private; 1455 struct tegra_sor *sor = node->info_ent->data; 1456 struct drm_crtc *crtc = sor->output.encoder.crtc; 1457 struct drm_device *drm = node->minor->dev; 1458 int err = 0; 1459 u32 value; 1460 1461 drm_modeset_lock_all(drm); 1462 1463 if (!crtc || !crtc->state->active) { 1464 err = -EBUSY; 1465 goto unlock; 1466 } 1467 1468 value = tegra_sor_readl(sor, SOR_STATE1); 1469 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1470 tegra_sor_writel(sor, value, SOR_STATE1); 1471 1472 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 1473 value |= SOR_CRC_CNTRL_ENABLE; 1474 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 1475 1476 value = tegra_sor_readl(sor, SOR_TEST); 1477 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 1478 tegra_sor_writel(sor, value, SOR_TEST); 1479 1480 err = tegra_sor_crc_wait(sor, 100); 1481 if (err < 0) 1482 goto unlock; 1483 1484 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); 1485 value = tegra_sor_readl(sor, SOR_CRCB); 1486 1487 seq_printf(s, "%08x\n", value); 1488 1489 unlock: 1490 drm_modeset_unlock_all(drm); 1491 return err; 1492 } 1493 1494 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1495 1496 static const struct debugfs_reg32 tegra_sor_regs[] = { 1497 DEBUGFS_REG32(SOR_CTXSW), 1498 DEBUGFS_REG32(SOR_SUPER_STATE0), 1499 DEBUGFS_REG32(SOR_SUPER_STATE1), 1500 DEBUGFS_REG32(SOR_STATE0), 1501 DEBUGFS_REG32(SOR_STATE1), 1502 DEBUGFS_REG32(SOR_HEAD_STATE0(0)), 1503 DEBUGFS_REG32(SOR_HEAD_STATE0(1)), 1504 DEBUGFS_REG32(SOR_HEAD_STATE1(0)), 1505 DEBUGFS_REG32(SOR_HEAD_STATE1(1)), 1506 DEBUGFS_REG32(SOR_HEAD_STATE2(0)), 1507 DEBUGFS_REG32(SOR_HEAD_STATE2(1)), 1508 DEBUGFS_REG32(SOR_HEAD_STATE3(0)), 1509 DEBUGFS_REG32(SOR_HEAD_STATE3(1)), 1510 DEBUGFS_REG32(SOR_HEAD_STATE4(0)), 1511 DEBUGFS_REG32(SOR_HEAD_STATE4(1)), 1512 DEBUGFS_REG32(SOR_HEAD_STATE5(0)), 1513 DEBUGFS_REG32(SOR_HEAD_STATE5(1)), 1514 DEBUGFS_REG32(SOR_CRC_CNTRL), 1515 DEBUGFS_REG32(SOR_DP_DEBUG_MVID), 1516 DEBUGFS_REG32(SOR_CLK_CNTRL), 1517 DEBUGFS_REG32(SOR_CAP), 1518 DEBUGFS_REG32(SOR_PWR), 1519 DEBUGFS_REG32(SOR_TEST), 1520 DEBUGFS_REG32(SOR_PLL0), 1521 DEBUGFS_REG32(SOR_PLL1), 1522 DEBUGFS_REG32(SOR_PLL2), 1523 DEBUGFS_REG32(SOR_PLL3), 1524 DEBUGFS_REG32(SOR_CSTM), 1525 DEBUGFS_REG32(SOR_LVDS), 1526 DEBUGFS_REG32(SOR_CRCA), 1527 DEBUGFS_REG32(SOR_CRCB), 1528 DEBUGFS_REG32(SOR_BLANK), 1529 DEBUGFS_REG32(SOR_SEQ_CTL), 1530 DEBUGFS_REG32(SOR_LANE_SEQ_CTL), 1531 DEBUGFS_REG32(SOR_SEQ_INST(0)), 1532 DEBUGFS_REG32(SOR_SEQ_INST(1)), 1533 DEBUGFS_REG32(SOR_SEQ_INST(2)), 1534 DEBUGFS_REG32(SOR_SEQ_INST(3)), 1535 DEBUGFS_REG32(SOR_SEQ_INST(4)), 1536 DEBUGFS_REG32(SOR_SEQ_INST(5)), 1537 DEBUGFS_REG32(SOR_SEQ_INST(6)), 1538 DEBUGFS_REG32(SOR_SEQ_INST(7)), 1539 DEBUGFS_REG32(SOR_SEQ_INST(8)), 1540 DEBUGFS_REG32(SOR_SEQ_INST(9)), 1541 DEBUGFS_REG32(SOR_SEQ_INST(10)), 1542 DEBUGFS_REG32(SOR_SEQ_INST(11)), 1543 DEBUGFS_REG32(SOR_SEQ_INST(12)), 1544 DEBUGFS_REG32(SOR_SEQ_INST(13)), 1545 DEBUGFS_REG32(SOR_SEQ_INST(14)), 1546 DEBUGFS_REG32(SOR_SEQ_INST(15)), 1547 DEBUGFS_REG32(SOR_PWM_DIV), 1548 DEBUGFS_REG32(SOR_PWM_CTL), 1549 DEBUGFS_REG32(SOR_VCRC_A0), 1550 DEBUGFS_REG32(SOR_VCRC_A1), 1551 DEBUGFS_REG32(SOR_VCRC_B0), 1552 DEBUGFS_REG32(SOR_VCRC_B1), 1553 DEBUGFS_REG32(SOR_CCRC_A0), 1554 DEBUGFS_REG32(SOR_CCRC_A1), 1555 DEBUGFS_REG32(SOR_CCRC_B0), 1556 DEBUGFS_REG32(SOR_CCRC_B1), 1557 DEBUGFS_REG32(SOR_EDATA_A0), 1558 DEBUGFS_REG32(SOR_EDATA_A1), 1559 DEBUGFS_REG32(SOR_EDATA_B0), 1560 DEBUGFS_REG32(SOR_EDATA_B1), 1561 DEBUGFS_REG32(SOR_COUNT_A0), 1562 DEBUGFS_REG32(SOR_COUNT_A1), 1563 DEBUGFS_REG32(SOR_COUNT_B0), 1564 DEBUGFS_REG32(SOR_COUNT_B1), 1565 DEBUGFS_REG32(SOR_DEBUG_A0), 1566 DEBUGFS_REG32(SOR_DEBUG_A1), 1567 DEBUGFS_REG32(SOR_DEBUG_B0), 1568 DEBUGFS_REG32(SOR_DEBUG_B1), 1569 DEBUGFS_REG32(SOR_TRIG), 1570 DEBUGFS_REG32(SOR_MSCHECK), 1571 DEBUGFS_REG32(SOR_XBAR_CTRL), 1572 DEBUGFS_REG32(SOR_XBAR_POL), 1573 DEBUGFS_REG32(SOR_DP_LINKCTL0), 1574 DEBUGFS_REG32(SOR_DP_LINKCTL1), 1575 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0), 1576 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1), 1577 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0), 1578 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1), 1579 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0), 1580 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1), 1581 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0), 1582 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1), 1583 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0), 1584 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1), 1585 DEBUGFS_REG32(SOR_DP_CONFIG0), 1586 DEBUGFS_REG32(SOR_DP_CONFIG1), 1587 DEBUGFS_REG32(SOR_DP_MN0), 1588 DEBUGFS_REG32(SOR_DP_MN1), 1589 DEBUGFS_REG32(SOR_DP_PADCTL0), 1590 DEBUGFS_REG32(SOR_DP_PADCTL1), 1591 DEBUGFS_REG32(SOR_DP_PADCTL2), 1592 DEBUGFS_REG32(SOR_DP_DEBUG0), 1593 DEBUGFS_REG32(SOR_DP_DEBUG1), 1594 DEBUGFS_REG32(SOR_DP_SPARE0), 1595 DEBUGFS_REG32(SOR_DP_SPARE1), 1596 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL), 1597 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS), 1598 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS), 1599 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER), 1600 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0), 1601 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1), 1602 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2), 1603 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3), 1604 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4), 1605 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5), 1606 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6), 1607 DEBUGFS_REG32(SOR_DP_TPG), 1608 DEBUGFS_REG32(SOR_DP_TPG_CONFIG), 1609 DEBUGFS_REG32(SOR_DP_LQ_CSTM0), 1610 DEBUGFS_REG32(SOR_DP_LQ_CSTM1), 1611 DEBUGFS_REG32(SOR_DP_LQ_CSTM2), 1612 }; 1613 1614 static int tegra_sor_show_regs(struct seq_file *s, void *data) 1615 { 1616 struct drm_info_node *node = s->private; 1617 struct tegra_sor *sor = node->info_ent->data; 1618 struct drm_crtc *crtc = sor->output.encoder.crtc; 1619 struct drm_device *drm = node->minor->dev; 1620 unsigned int i; 1621 int err = 0; 1622 1623 drm_modeset_lock_all(drm); 1624 1625 if (!crtc || !crtc->state->active) { 1626 err = -EBUSY; 1627 goto unlock; 1628 } 1629 1630 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) { 1631 unsigned int offset = tegra_sor_regs[i].offset; 1632 1633 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, 1634 offset, tegra_sor_readl(sor, offset)); 1635 } 1636 1637 unlock: 1638 drm_modeset_unlock_all(drm); 1639 return err; 1640 } 1641 1642 static const struct drm_info_list debugfs_files[] = { 1643 { "crc", tegra_sor_show_crc, 0, NULL }, 1644 { "regs", tegra_sor_show_regs, 0, NULL }, 1645 }; 1646 1647 static int tegra_sor_late_register(struct drm_connector *connector) 1648 { 1649 struct tegra_output *output = connector_to_output(connector); 1650 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1651 struct drm_minor *minor = connector->dev->primary; 1652 struct dentry *root = connector->debugfs_entry; 1653 struct tegra_sor *sor = to_sor(output); 1654 int err; 1655 1656 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1657 GFP_KERNEL); 1658 if (!sor->debugfs_files) 1659 return -ENOMEM; 1660 1661 for (i = 0; i < count; i++) 1662 sor->debugfs_files[i].data = sor; 1663 1664 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor); 1665 if (err < 0) 1666 goto free; 1667 1668 return 0; 1669 1670 free: 1671 kfree(sor->debugfs_files); 1672 sor->debugfs_files = NULL; 1673 1674 return err; 1675 } 1676 1677 static void tegra_sor_early_unregister(struct drm_connector *connector) 1678 { 1679 struct tegra_output *output = connector_to_output(connector); 1680 unsigned int count = ARRAY_SIZE(debugfs_files); 1681 struct tegra_sor *sor = to_sor(output); 1682 1683 drm_debugfs_remove_files(sor->debugfs_files, count, 1684 connector->dev->primary); 1685 kfree(sor->debugfs_files); 1686 sor->debugfs_files = NULL; 1687 } 1688 1689 static void tegra_sor_connector_reset(struct drm_connector *connector) 1690 { 1691 struct tegra_sor_state *state; 1692 1693 state = kzalloc(sizeof(*state), GFP_KERNEL); 1694 if (!state) 1695 return; 1696 1697 if (connector->state) { 1698 __drm_atomic_helper_connector_destroy_state(connector->state); 1699 kfree(connector->state); 1700 } 1701 1702 __drm_atomic_helper_connector_reset(connector, &state->base); 1703 } 1704 1705 static enum drm_connector_status 1706 tegra_sor_connector_detect(struct drm_connector *connector, bool force) 1707 { 1708 struct tegra_output *output = connector_to_output(connector); 1709 struct tegra_sor *sor = to_sor(output); 1710 1711 if (sor->aux) 1712 return drm_dp_aux_detect(sor->aux); 1713 1714 return tegra_output_connector_detect(connector, force); 1715 } 1716 1717 static struct drm_connector_state * 1718 tegra_sor_connector_duplicate_state(struct drm_connector *connector) 1719 { 1720 struct tegra_sor_state *state = to_sor_state(connector->state); 1721 struct tegra_sor_state *copy; 1722 1723 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 1724 if (!copy) 1725 return NULL; 1726 1727 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); 1728 1729 return ©->base; 1730 } 1731 1732 static const struct drm_connector_funcs tegra_sor_connector_funcs = { 1733 .reset = tegra_sor_connector_reset, 1734 .detect = tegra_sor_connector_detect, 1735 .fill_modes = drm_helper_probe_single_connector_modes, 1736 .destroy = tegra_output_connector_destroy, 1737 .atomic_duplicate_state = tegra_sor_connector_duplicate_state, 1738 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1739 .late_register = tegra_sor_late_register, 1740 .early_unregister = tegra_sor_early_unregister, 1741 }; 1742 1743 static int tegra_sor_connector_get_modes(struct drm_connector *connector) 1744 { 1745 struct tegra_output *output = connector_to_output(connector); 1746 struct tegra_sor *sor = to_sor(output); 1747 int err; 1748 1749 if (sor->aux) 1750 drm_dp_aux_enable(sor->aux); 1751 1752 err = tegra_output_connector_get_modes(connector); 1753 1754 if (sor->aux) 1755 drm_dp_aux_disable(sor->aux); 1756 1757 return err; 1758 } 1759 1760 static enum drm_mode_status 1761 tegra_sor_connector_mode_valid(struct drm_connector *connector, 1762 struct drm_display_mode *mode) 1763 { 1764 return MODE_OK; 1765 } 1766 1767 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { 1768 .get_modes = tegra_sor_connector_get_modes, 1769 .mode_valid = tegra_sor_connector_mode_valid, 1770 }; 1771 1772 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { 1773 .destroy = tegra_output_encoder_destroy, 1774 }; 1775 1776 static void tegra_sor_edp_disable(struct drm_encoder *encoder) 1777 { 1778 struct tegra_output *output = encoder_to_output(encoder); 1779 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1780 struct tegra_sor *sor = to_sor(output); 1781 u32 value; 1782 int err; 1783 1784 if (output->panel) 1785 drm_panel_disable(output->panel); 1786 1787 err = tegra_sor_detach(sor); 1788 if (err < 0) 1789 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1790 1791 tegra_sor_writel(sor, 0, SOR_STATE1); 1792 tegra_sor_update(sor); 1793 1794 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1795 value &= ~SOR_ENABLE(0); 1796 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1797 1798 tegra_dc_commit(dc); 1799 1800 err = tegra_sor_power_down(sor); 1801 if (err < 0) 1802 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1803 1804 if (sor->aux) { 1805 err = drm_dp_aux_disable(sor->aux); 1806 if (err < 0) 1807 dev_err(sor->dev, "failed to disable DP: %d\n", err); 1808 } 1809 1810 err = tegra_io_pad_power_disable(sor->pad); 1811 if (err < 0) 1812 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 1813 1814 if (output->panel) 1815 drm_panel_unprepare(output->panel); 1816 1817 pm_runtime_put(sor->dev); 1818 } 1819 1820 #if 0 1821 static int calc_h_ref_to_sync(const struct drm_display_mode *mode, 1822 unsigned int *value) 1823 { 1824 unsigned int hfp, hsw, hbp, a = 0, b; 1825 1826 hfp = mode->hsync_start - mode->hdisplay; 1827 hsw = mode->hsync_end - mode->hsync_start; 1828 hbp = mode->htotal - mode->hsync_end; 1829 1830 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp); 1831 1832 b = hfp - 1; 1833 1834 pr_info("a: %u, b: %u\n", a, b); 1835 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp); 1836 1837 if (a + hsw + hbp <= 11) { 1838 a = 1 + 11 - hsw - hbp; 1839 pr_info("a: %u\n", a); 1840 } 1841 1842 if (a > b) 1843 return -EINVAL; 1844 1845 if (hsw < 1) 1846 return -EINVAL; 1847 1848 if (mode->hdisplay < 16) 1849 return -EINVAL; 1850 1851 if (value) { 1852 if (b > a && a % 2) 1853 *value = a + 1; 1854 else 1855 *value = a; 1856 } 1857 1858 return 0; 1859 } 1860 #endif 1861 1862 static void tegra_sor_edp_enable(struct drm_encoder *encoder) 1863 { 1864 struct tegra_output *output = encoder_to_output(encoder); 1865 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1866 struct tegra_sor *sor = to_sor(output); 1867 struct tegra_sor_config config; 1868 struct tegra_sor_state *state; 1869 struct drm_display_mode *mode; 1870 struct drm_display_info *info; 1871 unsigned int i; 1872 u32 value; 1873 int err; 1874 1875 state = to_sor_state(output->connector.state); 1876 mode = &encoder->crtc->state->adjusted_mode; 1877 info = &output->connector.display_info; 1878 1879 pm_runtime_get_sync(sor->dev); 1880 1881 if (output->panel) 1882 drm_panel_prepare(output->panel); 1883 1884 err = drm_dp_aux_enable(sor->aux); 1885 if (err < 0) 1886 dev_err(sor->dev, "failed to enable DP: %d\n", err); 1887 1888 err = drm_dp_link_probe(sor->aux, &sor->link); 1889 if (err < 0) { 1890 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 1891 return; 1892 } 1893 1894 /* switch to safe parent clock */ 1895 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1896 if (err < 0) 1897 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1898 1899 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1900 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 1901 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 1902 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1903 1904 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1905 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1906 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1907 usleep_range(20, 100); 1908 1909 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 1910 value |= SOR_PLL3_PLL_VDD_MODE_3V3; 1911 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 1912 1913 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | 1914 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; 1915 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1916 1917 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1918 value |= SOR_PLL2_SEQ_PLLCAPPD; 1919 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1920 value |= SOR_PLL2_LVDS_ENABLE; 1921 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1922 1923 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; 1924 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 1925 1926 while (true) { 1927 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1928 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) 1929 break; 1930 1931 usleep_range(250, 1000); 1932 } 1933 1934 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1935 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 1936 value &= ~SOR_PLL2_PORT_POWERDOWN; 1937 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1938 1939 /* 1940 * power up 1941 */ 1942 1943 /* set safe link bandwidth (1.62 Gbps) */ 1944 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1945 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1946 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; 1947 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1948 1949 /* step 1 */ 1950 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1951 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | 1952 SOR_PLL2_BANDGAP_POWERDOWN; 1953 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1954 1955 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1956 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1957 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1958 1959 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 1960 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 1961 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 1962 1963 /* step 2 */ 1964 err = tegra_io_pad_power_enable(sor->pad); 1965 if (err < 0) 1966 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 1967 1968 usleep_range(5, 100); 1969 1970 /* step 3 */ 1971 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1972 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1973 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1974 1975 usleep_range(20, 100); 1976 1977 /* step 4 */ 1978 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1979 value &= ~SOR_PLL0_VCOPD; 1980 value &= ~SOR_PLL0_PWR; 1981 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1982 1983 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1984 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1985 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1986 1987 usleep_range(200, 1000); 1988 1989 /* step 5 */ 1990 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1991 value &= ~SOR_PLL2_PORT_POWERDOWN; 1992 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1993 1994 /* XXX not in TRM */ 1995 for (value = 0, i = 0; i < 5; i++) 1996 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | 1997 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 1998 1999 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2000 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2001 2002 /* switch to DP parent clock */ 2003 err = tegra_sor_set_parent_clock(sor, sor->clk_dp); 2004 if (err < 0) 2005 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 2006 2007 /* use DP-A protocol */ 2008 value = tegra_sor_readl(sor, SOR_STATE1); 2009 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2010 value |= SOR_STATE_ASY_PROTOCOL_DP_A; 2011 tegra_sor_writel(sor, value, SOR_STATE1); 2012 2013 /* enable port */ 2014 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2015 value |= SOR_DP_LINKCTL_ENABLE; 2016 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2017 2018 /* calibrate termination resistance (XXX do this only on HPD) */ 2019 tegra_sor_dp_term_calibrate(sor); 2020 2021 err = drm_dp_link_train(&sor->link); 2022 if (err < 0) 2023 dev_err(sor->dev, "link training failed: %d\n", err); 2024 else 2025 dev_dbg(sor->dev, "link training succeeded\n"); 2026 2027 err = drm_dp_link_power_up(sor->aux, &sor->link); 2028 if (err < 0) { 2029 dev_err(sor->dev, "failed to power up eDP link: %d\n", 2030 err); 2031 return; 2032 } 2033 2034 /* compute configuration */ 2035 memset(&config, 0, sizeof(config)); 2036 config.bits_per_pixel = state->bpc * 3; 2037 2038 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); 2039 if (err < 0) { 2040 dev_err(sor->dev, "failed to compute configuration: %d\n", err); 2041 return; 2042 } 2043 2044 tegra_sor_apply_config(sor, &config); 2045 2046 err = tegra_sor_power_up(sor, 250); 2047 if (err < 0) 2048 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2049 2050 /* CSTM (LVDS, link A/B, upper) */ 2051 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 2052 SOR_CSTM_UPPER; 2053 tegra_sor_writel(sor, value, SOR_CSTM); 2054 2055 /* use DP-A protocol */ 2056 value = tegra_sor_readl(sor, SOR_STATE1); 2057 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2058 value |= SOR_STATE_ASY_PROTOCOL_DP_A; 2059 tegra_sor_writel(sor, value, SOR_STATE1); 2060 2061 tegra_sor_mode_set(sor, mode, state); 2062 2063 /* PWM setup */ 2064 err = tegra_sor_setup_pwm(sor, 250); 2065 if (err < 0) 2066 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 2067 2068 tegra_sor_update(sor); 2069 2070 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2071 value |= SOR_ENABLE(0); 2072 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2073 2074 tegra_dc_commit(dc); 2075 2076 err = tegra_sor_attach(sor); 2077 if (err < 0) 2078 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2079 2080 err = tegra_sor_wakeup(sor); 2081 if (err < 0) 2082 dev_err(sor->dev, "failed to enable DC: %d\n", err); 2083 2084 if (output->panel) 2085 drm_panel_enable(output->panel); 2086 } 2087 2088 static int 2089 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, 2090 struct drm_crtc_state *crtc_state, 2091 struct drm_connector_state *conn_state) 2092 { 2093 struct tegra_output *output = encoder_to_output(encoder); 2094 struct tegra_sor_state *state = to_sor_state(conn_state); 2095 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 2096 unsigned long pclk = crtc_state->mode.clock * 1000; 2097 struct tegra_sor *sor = to_sor(output); 2098 struct drm_display_info *info; 2099 int err; 2100 2101 info = &output->connector.display_info; 2102 2103 /* 2104 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so 2105 * the pixel clock must be corrected accordingly. 2106 */ 2107 if (pclk >= 340000000) { 2108 state->link_speed = 20; 2109 state->pclk = pclk / 2; 2110 } else { 2111 state->link_speed = 10; 2112 state->pclk = pclk; 2113 } 2114 2115 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, 2116 pclk, 0); 2117 if (err < 0) { 2118 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 2119 return err; 2120 } 2121 2122 switch (info->bpc) { 2123 case 8: 2124 case 6: 2125 state->bpc = info->bpc; 2126 break; 2127 2128 default: 2129 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); 2130 state->bpc = 8; 2131 break; 2132 } 2133 2134 return 0; 2135 } 2136 2137 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = { 2138 .disable = tegra_sor_edp_disable, 2139 .enable = tegra_sor_edp_enable, 2140 .atomic_check = tegra_sor_encoder_atomic_check, 2141 }; 2142 2143 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) 2144 { 2145 u32 value = 0; 2146 size_t i; 2147 2148 for (i = size; i > 0; i--) 2149 value = (value << 8) | ptr[i - 1]; 2150 2151 return value; 2152 } 2153 2154 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, 2155 const void *data, size_t size) 2156 { 2157 const u8 *ptr = data; 2158 unsigned long offset; 2159 size_t i, j; 2160 u32 value; 2161 2162 switch (ptr[0]) { 2163 case HDMI_INFOFRAME_TYPE_AVI: 2164 offset = SOR_HDMI_AVI_INFOFRAME_HEADER; 2165 break; 2166 2167 case HDMI_INFOFRAME_TYPE_AUDIO: 2168 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; 2169 break; 2170 2171 case HDMI_INFOFRAME_TYPE_VENDOR: 2172 offset = SOR_HDMI_VSI_INFOFRAME_HEADER; 2173 break; 2174 2175 default: 2176 dev_err(sor->dev, "unsupported infoframe type: %02x\n", 2177 ptr[0]); 2178 return; 2179 } 2180 2181 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 2182 INFOFRAME_HEADER_VERSION(ptr[1]) | 2183 INFOFRAME_HEADER_LEN(ptr[2]); 2184 tegra_sor_writel(sor, value, offset); 2185 offset++; 2186 2187 /* 2188 * Each subpack contains 7 bytes, divided into: 2189 * - subpack_low: bytes 0 - 3 2190 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 2191 */ 2192 for (i = 3, j = 0; i < size; i += 7, j += 8) { 2193 size_t rem = size - i, num = min_t(size_t, rem, 4); 2194 2195 value = tegra_sor_hdmi_subpack(&ptr[i], num); 2196 tegra_sor_writel(sor, value, offset++); 2197 2198 num = min_t(size_t, rem - num, 3); 2199 2200 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); 2201 tegra_sor_writel(sor, value, offset++); 2202 } 2203 } 2204 2205 static int 2206 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, 2207 const struct drm_display_mode *mode) 2208 { 2209 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 2210 struct hdmi_avi_infoframe frame; 2211 u32 value; 2212 int err; 2213 2214 /* disable AVI infoframe */ 2215 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 2216 value &= ~INFOFRAME_CTRL_SINGLE; 2217 value &= ~INFOFRAME_CTRL_OTHER; 2218 value &= ~INFOFRAME_CTRL_ENABLE; 2219 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 2220 2221 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 2222 &sor->output.connector, mode); 2223 if (err < 0) { 2224 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2225 return err; 2226 } 2227 2228 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 2229 if (err < 0) { 2230 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); 2231 return err; 2232 } 2233 2234 tegra_sor_hdmi_write_infopack(sor, buffer, err); 2235 2236 /* enable AVI infoframe */ 2237 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 2238 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 2239 value |= INFOFRAME_CTRL_ENABLE; 2240 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 2241 2242 return 0; 2243 } 2244 2245 static void tegra_sor_write_eld(struct tegra_sor *sor) 2246 { 2247 size_t length = drm_eld_size(sor->output.connector.eld), i; 2248 2249 for (i = 0; i < length; i++) 2250 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], 2251 SOR_AUDIO_HDA_ELD_BUFWR); 2252 2253 /* 2254 * The HDA codec will always report an ELD buffer size of 96 bytes and 2255 * the HDA codec driver will check that each byte read from the buffer 2256 * is valid. Therefore every byte must be written, even if no 96 bytes 2257 * were parsed from EDID. 2258 */ 2259 for (i = length; i < 96; i++) 2260 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); 2261 } 2262 2263 static void tegra_sor_audio_prepare(struct tegra_sor *sor) 2264 { 2265 u32 value; 2266 2267 /* 2268 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This 2269 * is used for interoperability between the HDA codec driver and the 2270 * HDMI/DP driver. 2271 */ 2272 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; 2273 tegra_sor_writel(sor, value, SOR_INT_ENABLE); 2274 tegra_sor_writel(sor, value, SOR_INT_MASK); 2275 2276 tegra_sor_write_eld(sor); 2277 2278 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; 2279 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); 2280 } 2281 2282 static void tegra_sor_audio_unprepare(struct tegra_sor *sor) 2283 { 2284 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); 2285 tegra_sor_writel(sor, 0, SOR_INT_MASK); 2286 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); 2287 } 2288 2289 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) 2290 { 2291 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; 2292 struct hdmi_audio_infoframe frame; 2293 u32 value; 2294 int err; 2295 2296 err = hdmi_audio_infoframe_init(&frame); 2297 if (err < 0) { 2298 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); 2299 return err; 2300 } 2301 2302 frame.channels = sor->format.channels; 2303 2304 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 2305 if (err < 0) { 2306 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); 2307 return err; 2308 } 2309 2310 tegra_sor_hdmi_write_infopack(sor, buffer, err); 2311 2312 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2313 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 2314 value |= INFOFRAME_CTRL_ENABLE; 2315 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2316 2317 return 0; 2318 } 2319 2320 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) 2321 { 2322 u32 value; 2323 2324 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); 2325 2326 /* select HDA audio input */ 2327 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); 2328 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); 2329 2330 /* inject null samples */ 2331 if (sor->format.channels != 2) 2332 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 2333 else 2334 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 2335 2336 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; 2337 2338 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); 2339 2340 /* enable advertising HBR capability */ 2341 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); 2342 2343 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); 2344 2345 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | 2346 SOR_HDMI_SPARE_CTS_RESET(1) | 2347 SOR_HDMI_SPARE_HW_CTS_ENABLE; 2348 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); 2349 2350 /* enable HW CTS */ 2351 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); 2352 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); 2353 2354 /* allow packet to be sent */ 2355 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; 2356 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); 2357 2358 /* reset N counter and enable lookup */ 2359 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; 2360 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 2361 2362 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); 2363 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); 2364 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); 2365 2366 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); 2367 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); 2368 2369 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); 2370 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); 2371 2372 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); 2373 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); 2374 2375 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); 2376 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); 2377 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); 2378 2379 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); 2380 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); 2381 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); 2382 2383 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); 2384 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); 2385 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); 2386 2387 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); 2388 value &= ~SOR_HDMI_AUDIO_N_RESET; 2389 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 2390 2391 tegra_sor_hdmi_enable_audio_infoframe(sor); 2392 } 2393 2394 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) 2395 { 2396 u32 value; 2397 2398 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2399 value &= ~INFOFRAME_CTRL_ENABLE; 2400 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2401 } 2402 2403 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) 2404 { 2405 tegra_sor_hdmi_disable_audio_infoframe(sor); 2406 } 2407 2408 static struct tegra_sor_hdmi_settings * 2409 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) 2410 { 2411 unsigned int i; 2412 2413 for (i = 0; i < sor->num_settings; i++) 2414 if (frequency <= sor->settings[i].frequency) 2415 return &sor->settings[i]; 2416 2417 return NULL; 2418 } 2419 2420 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) 2421 { 2422 u32 value; 2423 2424 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2425 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2426 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; 2427 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2428 } 2429 2430 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) 2431 { 2432 struct i2c_adapter *ddc = sor->output.ddc; 2433 2434 drm_scdc_set_high_tmds_clock_ratio(ddc, false); 2435 drm_scdc_set_scrambling(ddc, false); 2436 2437 tegra_sor_hdmi_disable_scrambling(sor); 2438 } 2439 2440 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) 2441 { 2442 if (sor->scdc_enabled) { 2443 cancel_delayed_work_sync(&sor->scdc); 2444 tegra_sor_hdmi_scdc_disable(sor); 2445 } 2446 } 2447 2448 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) 2449 { 2450 u32 value; 2451 2452 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2453 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2454 value |= SOR_HDMI2_CTRL_SCRAMBLE; 2455 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2456 } 2457 2458 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) 2459 { 2460 struct i2c_adapter *ddc = sor->output.ddc; 2461 2462 drm_scdc_set_high_tmds_clock_ratio(ddc, true); 2463 drm_scdc_set_scrambling(ddc, true); 2464 2465 tegra_sor_hdmi_enable_scrambling(sor); 2466 } 2467 2468 static void tegra_sor_hdmi_scdc_work(struct work_struct *work) 2469 { 2470 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); 2471 struct i2c_adapter *ddc = sor->output.ddc; 2472 2473 if (!drm_scdc_get_scrambling_status(ddc)) { 2474 DRM_DEBUG_KMS("SCDC not scrambled\n"); 2475 tegra_sor_hdmi_scdc_enable(sor); 2476 } 2477 2478 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2479 } 2480 2481 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) 2482 { 2483 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; 2484 struct drm_display_mode *mode; 2485 2486 mode = &sor->output.encoder.crtc->state->adjusted_mode; 2487 2488 if (mode->clock >= 340000 && scdc->supported) { 2489 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2490 tegra_sor_hdmi_scdc_enable(sor); 2491 sor->scdc_enabled = true; 2492 } 2493 } 2494 2495 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) 2496 { 2497 struct tegra_output *output = encoder_to_output(encoder); 2498 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2499 struct tegra_sor *sor = to_sor(output); 2500 u32 value; 2501 int err; 2502 2503 tegra_sor_audio_unprepare(sor); 2504 tegra_sor_hdmi_scdc_stop(sor); 2505 2506 err = tegra_sor_detach(sor); 2507 if (err < 0) 2508 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2509 2510 tegra_sor_writel(sor, 0, SOR_STATE1); 2511 tegra_sor_update(sor); 2512 2513 /* disable display to SOR clock */ 2514 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2515 2516 if (!sor->soc->has_nvdisplay) 2517 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1)); 2518 else 2519 value &= ~SOR_ENABLE(sor->index); 2520 2521 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2522 2523 tegra_dc_commit(dc); 2524 2525 err = tegra_sor_power_down(sor); 2526 if (err < 0) 2527 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2528 2529 err = tegra_io_pad_power_disable(sor->pad); 2530 if (err < 0) 2531 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 2532 2533 pm_runtime_put(sor->dev); 2534 } 2535 2536 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) 2537 { 2538 struct tegra_output *output = encoder_to_output(encoder); 2539 unsigned int h_ref_to_sync = 1, pulse_start, max_ac; 2540 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2541 struct tegra_sor_hdmi_settings *settings; 2542 struct tegra_sor *sor = to_sor(output); 2543 struct tegra_sor_state *state; 2544 struct drm_display_mode *mode; 2545 unsigned long rate, pclk; 2546 unsigned int div, i; 2547 u32 value; 2548 int err; 2549 2550 state = to_sor_state(output->connector.state); 2551 mode = &encoder->crtc->state->adjusted_mode; 2552 pclk = mode->clock * 1000; 2553 2554 pm_runtime_get_sync(sor->dev); 2555 2556 /* switch to safe parent clock */ 2557 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2558 if (err < 0) { 2559 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2560 return; 2561 } 2562 2563 div = clk_get_rate(sor->clk) / 1000000 * 4; 2564 2565 err = tegra_io_pad_power_enable(sor->pad); 2566 if (err < 0) 2567 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 2568 2569 usleep_range(20, 100); 2570 2571 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2572 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2573 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2574 2575 usleep_range(20, 100); 2576 2577 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2578 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; 2579 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2580 2581 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2582 value &= ~SOR_PLL0_VCOPD; 2583 value &= ~SOR_PLL0_PWR; 2584 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2585 2586 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2587 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2588 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2589 2590 usleep_range(200, 400); 2591 2592 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2593 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2594 value &= ~SOR_PLL2_PORT_POWERDOWN; 2595 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2596 2597 usleep_range(20, 100); 2598 2599 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2600 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 2601 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 2602 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2603 2604 while (true) { 2605 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2606 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) 2607 break; 2608 2609 usleep_range(250, 1000); 2610 } 2611 2612 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 2613 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); 2614 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 2615 2616 while (true) { 2617 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2618 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 2619 break; 2620 2621 usleep_range(250, 1000); 2622 } 2623 2624 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2625 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 2626 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2627 2628 if (mode->clock < 340000) { 2629 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n"); 2630 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 2631 } else { 2632 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n"); 2633 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; 2634 } 2635 2636 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 2637 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2638 2639 /* SOR pad PLL stabilization time */ 2640 usleep_range(250, 1000); 2641 2642 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2643 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 2644 value |= SOR_DP_LINKCTL_LANE_COUNT(4); 2645 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2646 2647 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2648 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2649 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2650 value &= ~SOR_DP_SPARE_SEQ_ENABLE; 2651 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; 2652 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2653 2654 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | 2655 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); 2656 tegra_sor_writel(sor, value, SOR_SEQ_CTL); 2657 2658 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | 2659 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); 2660 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); 2661 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); 2662 2663 if (!sor->soc->has_nvdisplay) { 2664 /* program the reference clock */ 2665 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); 2666 tegra_sor_writel(sor, value, SOR_REFCLK); 2667 } 2668 2669 /* XXX not in TRM */ 2670 for (value = 0, i = 0; i < 5; i++) 2671 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | 2672 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 2673 2674 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2675 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2676 2677 /* switch to parent clock */ 2678 err = clk_set_parent(sor->clk, sor->clk_parent); 2679 if (err < 0) { 2680 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 2681 return; 2682 } 2683 2684 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); 2685 if (err < 0) { 2686 dev_err(sor->dev, "failed to set pad clock: %d\n", err); 2687 return; 2688 } 2689 2690 /* adjust clock rate for HDMI 2.0 modes */ 2691 rate = clk_get_rate(sor->clk_parent); 2692 2693 if (mode->clock >= 340000) 2694 rate /= 2; 2695 2696 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk); 2697 2698 clk_set_rate(sor->clk, rate); 2699 2700 if (!sor->soc->has_nvdisplay) { 2701 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2702 2703 /* XXX is this the proper check? */ 2704 if (mode->clock < 75000) 2705 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; 2706 2707 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); 2708 } 2709 2710 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; 2711 2712 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | 2713 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); 2714 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); 2715 2716 if (!dc->soc->has_nvdisplay) { 2717 /* H_PULSE2 setup */ 2718 pulse_start = h_ref_to_sync + 2719 (mode->hsync_end - mode->hsync_start) + 2720 (mode->htotal - mode->hsync_end) - 10; 2721 2722 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | 2723 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; 2724 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 2725 2726 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); 2727 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 2728 2729 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); 2730 value |= H_PULSE2_ENABLE; 2731 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); 2732 } 2733 2734 /* infoframe setup */ 2735 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); 2736 if (err < 0) 2737 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2738 2739 /* XXX HDMI audio support not implemented yet */ 2740 tegra_sor_hdmi_disable_audio_infoframe(sor); 2741 2742 /* use single TMDS protocol */ 2743 value = tegra_sor_readl(sor, SOR_STATE1); 2744 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2745 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; 2746 tegra_sor_writel(sor, value, SOR_STATE1); 2747 2748 /* power up pad calibration */ 2749 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2750 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 2751 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2752 2753 /* production settings */ 2754 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); 2755 if (!settings) { 2756 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", 2757 mode->clock * 1000); 2758 return; 2759 } 2760 2761 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2762 value &= ~SOR_PLL0_ICHPMP_MASK; 2763 value &= ~SOR_PLL0_FILTER_MASK; 2764 value &= ~SOR_PLL0_VCOCAP_MASK; 2765 value |= SOR_PLL0_ICHPMP(settings->ichpmp); 2766 value |= SOR_PLL0_FILTER(settings->filter); 2767 value |= SOR_PLL0_VCOCAP(settings->vcocap); 2768 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2769 2770 /* XXX not in TRM */ 2771 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 2772 value &= ~SOR_PLL1_LOADADJ_MASK; 2773 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 2774 value |= SOR_PLL1_LOADADJ(settings->loadadj); 2775 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); 2776 value |= SOR_PLL1_TMDS_TERM; 2777 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 2778 2779 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2780 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; 2781 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; 2782 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; 2783 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; 2784 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); 2785 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); 2786 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); 2787 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); 2788 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2789 2790 value = settings->drive_current[3] << 24 | 2791 settings->drive_current[2] << 16 | 2792 settings->drive_current[1] << 8 | 2793 settings->drive_current[0] << 0; 2794 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 2795 2796 value = settings->preemphasis[3] << 24 | 2797 settings->preemphasis[2] << 16 | 2798 settings->preemphasis[1] << 8 | 2799 settings->preemphasis[0] << 0; 2800 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 2801 2802 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2803 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 2804 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 2805 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); 2806 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2807 2808 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); 2809 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; 2810 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); 2811 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); 2812 2813 /* power down pad calibration */ 2814 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2815 value |= SOR_DP_PADCTL_PAD_CAL_PD; 2816 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2817 2818 if (!dc->soc->has_nvdisplay) { 2819 /* miscellaneous display controller settings */ 2820 value = VSYNC_H_POSITION(1); 2821 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); 2822 } 2823 2824 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2825 value &= ~DITHER_CONTROL_MASK; 2826 value &= ~BASE_COLOR_SIZE_MASK; 2827 2828 switch (state->bpc) { 2829 case 6: 2830 value |= BASE_COLOR_SIZE_666; 2831 break; 2832 2833 case 8: 2834 value |= BASE_COLOR_SIZE_888; 2835 break; 2836 2837 case 10: 2838 value |= BASE_COLOR_SIZE_101010; 2839 break; 2840 2841 case 12: 2842 value |= BASE_COLOR_SIZE_121212; 2843 break; 2844 2845 default: 2846 WARN(1, "%u bits-per-color not supported\n", state->bpc); 2847 value |= BASE_COLOR_SIZE_888; 2848 break; 2849 } 2850 2851 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2852 2853 /* XXX set display head owner */ 2854 value = tegra_sor_readl(sor, SOR_STATE1); 2855 value &= ~SOR_STATE_ASY_OWNER_MASK; 2856 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); 2857 tegra_sor_writel(sor, value, SOR_STATE1); 2858 2859 err = tegra_sor_power_up(sor, 250); 2860 if (err < 0) 2861 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2862 2863 /* configure dynamic range of output */ 2864 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2865 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; 2866 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; 2867 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2868 2869 /* configure colorspace */ 2870 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2871 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; 2872 value |= SOR_HEAD_STATE_COLORSPACE_RGB; 2873 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2874 2875 tegra_sor_mode_set(sor, mode, state); 2876 2877 tegra_sor_update(sor); 2878 2879 /* program preamble timing in SOR (XXX) */ 2880 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2881 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2882 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2883 2884 err = tegra_sor_attach(sor); 2885 if (err < 0) 2886 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2887 2888 /* enable display to SOR clock and generate HDMI preamble */ 2889 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2890 2891 if (!sor->soc->has_nvdisplay) 2892 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA; 2893 else 2894 value |= SOR_ENABLE(sor->index); 2895 2896 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2897 2898 if (dc->soc->has_nvdisplay) { 2899 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2900 value &= ~PROTOCOL_MASK; 2901 value |= PROTOCOL_SINGLE_TMDS_A; 2902 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2903 } 2904 2905 tegra_dc_commit(dc); 2906 2907 err = tegra_sor_wakeup(sor); 2908 if (err < 0) 2909 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2910 2911 tegra_sor_hdmi_scdc_start(sor); 2912 tegra_sor_audio_prepare(sor); 2913 } 2914 2915 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { 2916 .disable = tegra_sor_hdmi_disable, 2917 .enable = tegra_sor_hdmi_enable, 2918 .atomic_check = tegra_sor_encoder_atomic_check, 2919 }; 2920 2921 static int tegra_sor_init(struct host1x_client *client) 2922 { 2923 struct drm_device *drm = dev_get_drvdata(client->parent); 2924 const struct drm_encoder_helper_funcs *helpers = NULL; 2925 struct tegra_sor *sor = host1x_client_to_sor(client); 2926 int connector = DRM_MODE_CONNECTOR_Unknown; 2927 int encoder = DRM_MODE_ENCODER_NONE; 2928 int err; 2929 2930 if (!sor->aux) { 2931 if (sor->soc->supports_hdmi) { 2932 connector = DRM_MODE_CONNECTOR_HDMIA; 2933 encoder = DRM_MODE_ENCODER_TMDS; 2934 helpers = &tegra_sor_hdmi_helpers; 2935 } else if (sor->soc->supports_lvds) { 2936 connector = DRM_MODE_CONNECTOR_LVDS; 2937 encoder = DRM_MODE_ENCODER_LVDS; 2938 } 2939 } else { 2940 if (sor->soc->supports_edp) { 2941 connector = DRM_MODE_CONNECTOR_eDP; 2942 encoder = DRM_MODE_ENCODER_TMDS; 2943 helpers = &tegra_sor_edp_helpers; 2944 } else if (sor->soc->supports_dp) { 2945 connector = DRM_MODE_CONNECTOR_DisplayPort; 2946 encoder = DRM_MODE_ENCODER_TMDS; 2947 } 2948 2949 sor->link.ops = &tegra_sor_dp_link_ops; 2950 sor->link.aux = sor->aux; 2951 } 2952 2953 sor->output.dev = sor->dev; 2954 2955 drm_connector_init(drm, &sor->output.connector, 2956 &tegra_sor_connector_funcs, 2957 connector); 2958 drm_connector_helper_add(&sor->output.connector, 2959 &tegra_sor_connector_helper_funcs); 2960 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; 2961 2962 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, 2963 encoder, NULL); 2964 drm_encoder_helper_add(&sor->output.encoder, helpers); 2965 2966 drm_connector_attach_encoder(&sor->output.connector, 2967 &sor->output.encoder); 2968 drm_connector_register(&sor->output.connector); 2969 2970 err = tegra_output_init(drm, &sor->output); 2971 if (err < 0) { 2972 dev_err(client->dev, "failed to initialize output: %d\n", err); 2973 return err; 2974 } 2975 2976 tegra_output_find_possible_crtcs(&sor->output, drm); 2977 2978 if (sor->aux) { 2979 err = drm_dp_aux_attach(sor->aux, &sor->output); 2980 if (err < 0) { 2981 dev_err(sor->dev, "failed to attach DP: %d\n", err); 2982 return err; 2983 } 2984 } 2985 2986 /* 2987 * XXX: Remove this reset once proper hand-over from firmware to 2988 * kernel is possible. 2989 */ 2990 if (sor->rst) { 2991 err = reset_control_acquire(sor->rst); 2992 if (err < 0) { 2993 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", 2994 err); 2995 return err; 2996 } 2997 2998 err = reset_control_assert(sor->rst); 2999 if (err < 0) { 3000 dev_err(sor->dev, "failed to assert SOR reset: %d\n", 3001 err); 3002 return err; 3003 } 3004 } 3005 3006 err = clk_prepare_enable(sor->clk); 3007 if (err < 0) { 3008 dev_err(sor->dev, "failed to enable clock: %d\n", err); 3009 return err; 3010 } 3011 3012 usleep_range(1000, 3000); 3013 3014 if (sor->rst) { 3015 err = reset_control_deassert(sor->rst); 3016 if (err < 0) { 3017 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", 3018 err); 3019 return err; 3020 } 3021 3022 reset_control_release(sor->rst); 3023 } 3024 3025 err = clk_prepare_enable(sor->clk_safe); 3026 if (err < 0) 3027 return err; 3028 3029 err = clk_prepare_enable(sor->clk_dp); 3030 if (err < 0) 3031 return err; 3032 3033 return 0; 3034 } 3035 3036 static int tegra_sor_exit(struct host1x_client *client) 3037 { 3038 struct tegra_sor *sor = host1x_client_to_sor(client); 3039 int err; 3040 3041 tegra_output_exit(&sor->output); 3042 3043 if (sor->aux) { 3044 err = drm_dp_aux_detach(sor->aux); 3045 if (err < 0) { 3046 dev_err(sor->dev, "failed to detach DP: %d\n", err); 3047 return err; 3048 } 3049 } 3050 3051 clk_disable_unprepare(sor->clk_safe); 3052 clk_disable_unprepare(sor->clk_dp); 3053 clk_disable_unprepare(sor->clk); 3054 3055 return 0; 3056 } 3057 3058 static const struct host1x_client_ops sor_client_ops = { 3059 .init = tegra_sor_init, 3060 .exit = tegra_sor_exit, 3061 }; 3062 3063 static const struct tegra_sor_ops tegra_sor_edp_ops = { 3064 .name = "eDP", 3065 }; 3066 3067 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) 3068 { 3069 int err; 3070 3071 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); 3072 if (IS_ERR(sor->avdd_io_supply)) { 3073 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", 3074 PTR_ERR(sor->avdd_io_supply)); 3075 return PTR_ERR(sor->avdd_io_supply); 3076 } 3077 3078 err = regulator_enable(sor->avdd_io_supply); 3079 if (err < 0) { 3080 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", 3081 err); 3082 return err; 3083 } 3084 3085 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); 3086 if (IS_ERR(sor->vdd_pll_supply)) { 3087 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", 3088 PTR_ERR(sor->vdd_pll_supply)); 3089 return PTR_ERR(sor->vdd_pll_supply); 3090 } 3091 3092 err = regulator_enable(sor->vdd_pll_supply); 3093 if (err < 0) { 3094 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", 3095 err); 3096 return err; 3097 } 3098 3099 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); 3100 if (IS_ERR(sor->hdmi_supply)) { 3101 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", 3102 PTR_ERR(sor->hdmi_supply)); 3103 return PTR_ERR(sor->hdmi_supply); 3104 } 3105 3106 err = regulator_enable(sor->hdmi_supply); 3107 if (err < 0) { 3108 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); 3109 return err; 3110 } 3111 3112 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); 3113 3114 return 0; 3115 } 3116 3117 static int tegra_sor_hdmi_remove(struct tegra_sor *sor) 3118 { 3119 regulator_disable(sor->hdmi_supply); 3120 regulator_disable(sor->vdd_pll_supply); 3121 regulator_disable(sor->avdd_io_supply); 3122 3123 return 0; 3124 } 3125 3126 static const struct tegra_sor_ops tegra_sor_hdmi_ops = { 3127 .name = "HDMI", 3128 .probe = tegra_sor_hdmi_probe, 3129 .remove = tegra_sor_hdmi_remove, 3130 }; 3131 3132 static const u8 tegra124_sor_xbar_cfg[5] = { 3133 0, 1, 2, 3, 4 3134 }; 3135 3136 static const struct tegra_sor_regs tegra124_sor_regs = { 3137 .head_state0 = 0x05, 3138 .head_state1 = 0x07, 3139 .head_state2 = 0x09, 3140 .head_state3 = 0x0b, 3141 .head_state4 = 0x0d, 3142 .head_state5 = 0x0f, 3143 .pll0 = 0x17, 3144 .pll1 = 0x18, 3145 .pll2 = 0x19, 3146 .pll3 = 0x1a, 3147 .dp_padctl0 = 0x5c, 3148 .dp_padctl2 = 0x73, 3149 }; 3150 3151 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */ 3152 static const u8 tegra124_sor_lane_map[4] = { 3153 2, 1, 0, 3, 3154 }; 3155 3156 static const u8 tegra124_sor_voltage_swing[4][4][4] = { 3157 { 3158 { 0x13, 0x19, 0x1e, 0x28 }, 3159 { 0x1e, 0x25, 0x2d, }, 3160 { 0x28, 0x32, }, 3161 { 0x3c, }, 3162 }, { 3163 { 0x12, 0x17, 0x1b, 0x25 }, 3164 { 0x1c, 0x23, 0x2a, }, 3165 { 0x25, 0x2f, }, 3166 { 0x39, } 3167 }, { 3168 { 0x12, 0x16, 0x1a, 0x22 }, 3169 { 0x1b, 0x20, 0x27, }, 3170 { 0x24, 0x2d, }, 3171 { 0x36, }, 3172 }, { 3173 { 0x11, 0x14, 0x17, 0x1f }, 3174 { 0x19, 0x1e, 0x24, }, 3175 { 0x22, 0x2a, }, 3176 { 0x32, }, 3177 }, 3178 }; 3179 3180 static const u8 tegra124_sor_pre_emphasis[4][4][4] = { 3181 { 3182 { 0x00, 0x09, 0x13, 0x25 }, 3183 { 0x00, 0x0f, 0x1e, }, 3184 { 0x00, 0x14, }, 3185 { 0x00, }, 3186 }, { 3187 { 0x00, 0x0a, 0x14, 0x28 }, 3188 { 0x00, 0x0f, 0x1e, }, 3189 { 0x00, 0x14, }, 3190 { 0x00 }, 3191 }, { 3192 { 0x00, 0x0a, 0x14, 0x28 }, 3193 { 0x00, 0x0f, 0x1e, }, 3194 { 0x00, 0x14, }, 3195 { 0x00, }, 3196 }, { 3197 { 0x00, 0x0a, 0x14, 0x28 }, 3198 { 0x00, 0x0f, 0x1e, }, 3199 { 0x00, 0x14, }, 3200 { 0x00, }, 3201 }, 3202 }; 3203 3204 static const u8 tegra124_sor_post_cursor[4][4][4] = { 3205 { 3206 { 0x00, 0x00, 0x00, 0x00 }, 3207 { 0x00, 0x00, 0x00, }, 3208 { 0x00, 0x00, }, 3209 { 0x00, }, 3210 }, { 3211 { 0x02, 0x02, 0x04, 0x05 }, 3212 { 0x02, 0x04, 0x05, }, 3213 { 0x04, 0x05, }, 3214 { 0x05, }, 3215 }, { 3216 { 0x04, 0x05, 0x08, 0x0b }, 3217 { 0x05, 0x09, 0x0b, }, 3218 { 0x08, 0x0a, }, 3219 { 0x0b, }, 3220 }, { 3221 { 0x05, 0x09, 0x0b, 0x12 }, 3222 { 0x09, 0x0d, 0x12, }, 3223 { 0x0b, 0x0f, }, 3224 { 0x12, }, 3225 }, 3226 }; 3227 3228 static const u8 tegra124_sor_tx_pu[4][4][4] = { 3229 { 3230 { 0x20, 0x30, 0x40, 0x60 }, 3231 { 0x30, 0x40, 0x60, }, 3232 { 0x40, 0x60, }, 3233 { 0x60, }, 3234 }, { 3235 { 0x20, 0x20, 0x30, 0x50 }, 3236 { 0x30, 0x40, 0x50, }, 3237 { 0x40, 0x50, }, 3238 { 0x60, }, 3239 }, { 3240 { 0x20, 0x20, 0x30, 0x40, }, 3241 { 0x30, 0x30, 0x40, }, 3242 { 0x40, 0x50, }, 3243 { 0x60, }, 3244 }, { 3245 { 0x20, 0x20, 0x20, 0x40, }, 3246 { 0x30, 0x30, 0x40, }, 3247 { 0x40, 0x40, }, 3248 { 0x60, }, 3249 }, 3250 }; 3251 3252 static const struct tegra_sor_soc tegra124_sor = { 3253 .supports_edp = true, 3254 .supports_lvds = true, 3255 .supports_hdmi = false, 3256 .supports_dp = false, 3257 .regs = &tegra124_sor_regs, 3258 .has_nvdisplay = false, 3259 .xbar_cfg = tegra124_sor_xbar_cfg, 3260 .lane_map = tegra124_sor_lane_map, 3261 .voltage_swing = tegra124_sor_voltage_swing, 3262 .pre_emphasis = tegra124_sor_pre_emphasis, 3263 .post_cursor = tegra124_sor_post_cursor, 3264 .tx_pu = tegra124_sor_tx_pu, 3265 }; 3266 3267 static const u8 tegra132_sor_pre_emphasis[4][4][4] = { 3268 { 3269 { 0x00, 0x08, 0x12, 0x24 }, 3270 { 0x01, 0x0e, 0x1d, }, 3271 { 0x01, 0x13, }, 3272 { 0x00, }, 3273 }, { 3274 { 0x00, 0x08, 0x12, 0x24 }, 3275 { 0x00, 0x0e, 0x1d, }, 3276 { 0x00, 0x13, }, 3277 { 0x00 }, 3278 }, { 3279 { 0x00, 0x08, 0x12, 0x24 }, 3280 { 0x00, 0x0e, 0x1d, }, 3281 { 0x00, 0x13, }, 3282 { 0x00, }, 3283 }, { 3284 { 0x00, 0x08, 0x12, 0x24 }, 3285 { 0x00, 0x0e, 0x1d, }, 3286 { 0x00, 0x13, }, 3287 { 0x00, }, 3288 }, 3289 }; 3290 3291 static const struct tegra_sor_soc tegra132_sor = { 3292 .supports_edp = true, 3293 .supports_lvds = true, 3294 .supports_hdmi = false, 3295 .supports_dp = false, 3296 .regs = &tegra124_sor_regs, 3297 .has_nvdisplay = false, 3298 .xbar_cfg = tegra124_sor_xbar_cfg, 3299 .lane_map = tegra124_sor_lane_map, 3300 .voltage_swing = tegra124_sor_voltage_swing, 3301 .pre_emphasis = tegra132_sor_pre_emphasis, 3302 .post_cursor = tegra124_sor_post_cursor, 3303 .tx_pu = tegra124_sor_tx_pu, 3304 }; 3305 3306 static const struct tegra_sor_regs tegra210_sor_regs = { 3307 .head_state0 = 0x05, 3308 .head_state1 = 0x07, 3309 .head_state2 = 0x09, 3310 .head_state3 = 0x0b, 3311 .head_state4 = 0x0d, 3312 .head_state5 = 0x0f, 3313 .pll0 = 0x17, 3314 .pll1 = 0x18, 3315 .pll2 = 0x19, 3316 .pll3 = 0x1a, 3317 .dp_padctl0 = 0x5c, 3318 .dp_padctl2 = 0x73, 3319 }; 3320 3321 static const u8 tegra210_sor_xbar_cfg[5] = { 3322 2, 1, 0, 3, 4 3323 }; 3324 3325 static const struct tegra_sor_soc tegra210_sor = { 3326 .supports_edp = true, 3327 .supports_lvds = false, 3328 .supports_hdmi = false, 3329 .supports_dp = false, 3330 3331 .regs = &tegra210_sor_regs, 3332 .has_nvdisplay = false, 3333 3334 .xbar_cfg = tegra210_sor_xbar_cfg, 3335 }; 3336 3337 static const struct tegra_sor_soc tegra210_sor1 = { 3338 .supports_edp = false, 3339 .supports_lvds = false, 3340 .supports_hdmi = true, 3341 .supports_dp = true, 3342 3343 .regs = &tegra210_sor_regs, 3344 .has_nvdisplay = false, 3345 3346 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), 3347 .settings = tegra210_sor_hdmi_defaults, 3348 .xbar_cfg = tegra210_sor_xbar_cfg, 3349 }; 3350 3351 static const struct tegra_sor_regs tegra186_sor_regs = { 3352 .head_state0 = 0x151, 3353 .head_state1 = 0x154, 3354 .head_state2 = 0x157, 3355 .head_state3 = 0x15a, 3356 .head_state4 = 0x15d, 3357 .head_state5 = 0x160, 3358 .pll0 = 0x163, 3359 .pll1 = 0x164, 3360 .pll2 = 0x165, 3361 .pll3 = 0x166, 3362 .dp_padctl0 = 0x168, 3363 .dp_padctl2 = 0x16a, 3364 }; 3365 3366 static const struct tegra_sor_soc tegra186_sor = { 3367 .supports_edp = false, 3368 .supports_lvds = false, 3369 .supports_hdmi = false, 3370 .supports_dp = true, 3371 3372 .regs = &tegra186_sor_regs, 3373 .has_nvdisplay = true, 3374 3375 .xbar_cfg = tegra124_sor_xbar_cfg, 3376 }; 3377 3378 static const struct tegra_sor_soc tegra186_sor1 = { 3379 .supports_edp = false, 3380 .supports_lvds = false, 3381 .supports_hdmi = true, 3382 .supports_dp = true, 3383 3384 .regs = &tegra186_sor_regs, 3385 .has_nvdisplay = true, 3386 3387 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults), 3388 .settings = tegra186_sor_hdmi_defaults, 3389 .xbar_cfg = tegra124_sor_xbar_cfg, 3390 }; 3391 3392 static const struct tegra_sor_regs tegra194_sor_regs = { 3393 .head_state0 = 0x151, 3394 .head_state1 = 0x155, 3395 .head_state2 = 0x159, 3396 .head_state3 = 0x15d, 3397 .head_state4 = 0x161, 3398 .head_state5 = 0x165, 3399 .pll0 = 0x169, 3400 .pll1 = 0x16a, 3401 .pll2 = 0x16b, 3402 .pll3 = 0x16c, 3403 .dp_padctl0 = 0x16e, 3404 .dp_padctl2 = 0x16f, 3405 }; 3406 3407 static const struct tegra_sor_soc tegra194_sor = { 3408 .supports_edp = true, 3409 .supports_lvds = false, 3410 .supports_hdmi = true, 3411 .supports_dp = true, 3412 3413 .regs = &tegra194_sor_regs, 3414 .has_nvdisplay = true, 3415 3416 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults), 3417 .settings = tegra194_sor_hdmi_defaults, 3418 3419 .xbar_cfg = tegra210_sor_xbar_cfg, 3420 }; 3421 3422 static const struct of_device_id tegra_sor_of_match[] = { 3423 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor }, 3424 { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 }, 3425 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, 3426 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, 3427 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, 3428 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor }, 3429 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, 3430 { }, 3431 }; 3432 MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 3433 3434 static int tegra_sor_parse_dt(struct tegra_sor *sor) 3435 { 3436 struct device_node *np = sor->dev->of_node; 3437 u32 xbar_cfg[5]; 3438 unsigned int i; 3439 u32 value; 3440 int err; 3441 3442 if (sor->soc->has_nvdisplay) { 3443 err = of_property_read_u32(np, "nvidia,interface", &value); 3444 if (err < 0) 3445 return err; 3446 3447 sor->index = value; 3448 3449 /* 3450 * override the default that we already set for Tegra210 and 3451 * earlier 3452 */ 3453 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; 3454 } 3455 3456 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); 3457 if (err < 0) { 3458 /* fall back to default per-SoC XBAR configuration */ 3459 for (i = 0; i < 5; i++) 3460 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; 3461 } else { 3462 /* copy cells to SOR XBAR configuration */ 3463 for (i = 0; i < 5; i++) 3464 sor->xbar_cfg[i] = xbar_cfg[i]; 3465 } 3466 3467 return 0; 3468 } 3469 3470 static irqreturn_t tegra_sor_irq(int irq, void *data) 3471 { 3472 struct tegra_sor *sor = data; 3473 u32 value; 3474 3475 value = tegra_sor_readl(sor, SOR_INT_STATUS); 3476 tegra_sor_writel(sor, value, SOR_INT_STATUS); 3477 3478 if (value & SOR_INT_CODEC_SCRATCH0) { 3479 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); 3480 3481 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { 3482 unsigned int format; 3483 3484 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; 3485 3486 tegra_hda_parse_format(format, &sor->format); 3487 3488 tegra_sor_hdmi_audio_enable(sor); 3489 } else { 3490 tegra_sor_hdmi_audio_disable(sor); 3491 } 3492 } 3493 3494 return IRQ_HANDLED; 3495 } 3496 3497 static int tegra_sor_probe(struct platform_device *pdev) 3498 { 3499 struct device_node *np; 3500 struct tegra_sor *sor; 3501 struct resource *regs; 3502 int err; 3503 3504 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 3505 if (!sor) 3506 return -ENOMEM; 3507 3508 sor->soc = of_device_get_match_data(&pdev->dev); 3509 sor->output.dev = sor->dev = &pdev->dev; 3510 3511 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, 3512 sor->soc->num_settings * 3513 sizeof(*sor->settings), 3514 GFP_KERNEL); 3515 if (!sor->settings) 3516 return -ENOMEM; 3517 3518 sor->num_settings = sor->soc->num_settings; 3519 3520 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 3521 if (np) { 3522 sor->aux = drm_dp_aux_find_by_of_node(np); 3523 of_node_put(np); 3524 3525 if (!sor->aux) 3526 return -EPROBE_DEFER; 3527 } 3528 3529 if (!sor->aux) { 3530 if (sor->soc->supports_hdmi) { 3531 sor->ops = &tegra_sor_hdmi_ops; 3532 sor->pad = TEGRA_IO_PAD_HDMI; 3533 } else if (sor->soc->supports_lvds) { 3534 dev_err(&pdev->dev, "LVDS not supported yet\n"); 3535 return -ENODEV; 3536 } else { 3537 dev_err(&pdev->dev, "unknown (non-DP) support\n"); 3538 return -ENODEV; 3539 } 3540 } else { 3541 if (sor->soc->supports_edp) { 3542 sor->ops = &tegra_sor_edp_ops; 3543 sor->pad = TEGRA_IO_PAD_LVDS; 3544 } else if (sor->soc->supports_dp) { 3545 dev_err(&pdev->dev, "DisplayPort not supported yet\n"); 3546 return -ENODEV; 3547 } else { 3548 dev_err(&pdev->dev, "unknown (DP) support\n"); 3549 return -ENODEV; 3550 } 3551 } 3552 3553 err = tegra_sor_parse_dt(sor); 3554 if (err < 0) 3555 return err; 3556 3557 err = tegra_output_probe(&sor->output); 3558 if (err < 0) { 3559 dev_err(&pdev->dev, "failed to probe output: %d\n", err); 3560 return err; 3561 } 3562 3563 if (sor->ops && sor->ops->probe) { 3564 err = sor->ops->probe(sor); 3565 if (err < 0) { 3566 dev_err(&pdev->dev, "failed to probe %s: %d\n", 3567 sor->ops->name, err); 3568 goto output; 3569 } 3570 } 3571 3572 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3573 sor->regs = devm_ioremap_resource(&pdev->dev, regs); 3574 if (IS_ERR(sor->regs)) { 3575 err = PTR_ERR(sor->regs); 3576 goto remove; 3577 } 3578 3579 err = platform_get_irq(pdev, 0); 3580 if (err < 0) { 3581 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); 3582 goto remove; 3583 } 3584 3585 sor->irq = err; 3586 3587 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, 3588 dev_name(sor->dev), sor); 3589 if (err < 0) { 3590 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 3591 goto remove; 3592 } 3593 3594 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); 3595 if (IS_ERR(sor->rst)) { 3596 err = PTR_ERR(sor->rst); 3597 3598 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) { 3599 dev_err(&pdev->dev, "failed to get reset control: %d\n", 3600 err); 3601 goto remove; 3602 } 3603 3604 /* 3605 * At this point, the reset control is most likely being used 3606 * by the generic power domain implementation. With any luck 3607 * the power domain will have taken care of resetting the SOR 3608 * and we don't have to do anything. 3609 */ 3610 sor->rst = NULL; 3611 } 3612 3613 sor->clk = devm_clk_get(&pdev->dev, NULL); 3614 if (IS_ERR(sor->clk)) { 3615 err = PTR_ERR(sor->clk); 3616 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); 3617 goto remove; 3618 } 3619 3620 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { 3621 struct device_node *np = pdev->dev.of_node; 3622 const char *name; 3623 3624 /* 3625 * For backwards compatibility with Tegra210 device trees, 3626 * fall back to the old clock name "source" if the new "out" 3627 * clock is not available. 3628 */ 3629 if (of_property_match_string(np, "clock-names", "out") < 0) 3630 name = "source"; 3631 else 3632 name = "out"; 3633 3634 sor->clk_out = devm_clk_get(&pdev->dev, name); 3635 if (IS_ERR(sor->clk_out)) { 3636 err = PTR_ERR(sor->clk_out); 3637 dev_err(sor->dev, "failed to get %s clock: %d\n", 3638 name, err); 3639 goto remove; 3640 } 3641 } else { 3642 /* fall back to the module clock on SOR0 (eDP/LVDS only) */ 3643 sor->clk_out = sor->clk; 3644 } 3645 3646 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 3647 if (IS_ERR(sor->clk_parent)) { 3648 err = PTR_ERR(sor->clk_parent); 3649 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); 3650 goto remove; 3651 } 3652 3653 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 3654 if (IS_ERR(sor->clk_safe)) { 3655 err = PTR_ERR(sor->clk_safe); 3656 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); 3657 goto remove; 3658 } 3659 3660 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 3661 if (IS_ERR(sor->clk_dp)) { 3662 err = PTR_ERR(sor->clk_dp); 3663 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); 3664 goto remove; 3665 } 3666 3667 /* 3668 * Starting with Tegra186, the BPMP provides an implementation for 3669 * the pad output clock, so we have to look it up from device tree. 3670 */ 3671 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); 3672 if (IS_ERR(sor->clk_pad)) { 3673 if (sor->clk_pad != ERR_PTR(-ENOENT)) { 3674 err = PTR_ERR(sor->clk_pad); 3675 goto remove; 3676 } 3677 3678 /* 3679 * If the pad output clock is not available, then we assume 3680 * we're on Tegra210 or earlier and have to provide our own 3681 * implementation. 3682 */ 3683 sor->clk_pad = NULL; 3684 } 3685 3686 /* 3687 * The bootloader may have set up the SOR such that it's module clock 3688 * is sourced by one of the display PLLs. However, that doesn't work 3689 * without properly having set up other bits of the SOR. 3690 */ 3691 err = clk_set_parent(sor->clk_out, sor->clk_safe); 3692 if (err < 0) { 3693 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); 3694 goto remove; 3695 } 3696 3697 platform_set_drvdata(pdev, sor); 3698 pm_runtime_enable(&pdev->dev); 3699 3700 /* 3701 * On Tegra210 and earlier, provide our own implementation for the 3702 * pad output clock. 3703 */ 3704 if (!sor->clk_pad) { 3705 err = pm_runtime_get_sync(&pdev->dev); 3706 if (err < 0) { 3707 dev_err(&pdev->dev, "failed to get runtime PM: %d\n", 3708 err); 3709 goto remove; 3710 } 3711 3712 sor->clk_pad = tegra_clk_sor_pad_register(sor, 3713 "sor1_pad_clkout"); 3714 pm_runtime_put(&pdev->dev); 3715 } 3716 3717 if (IS_ERR(sor->clk_pad)) { 3718 err = PTR_ERR(sor->clk_pad); 3719 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n", 3720 err); 3721 goto remove; 3722 } 3723 3724 INIT_LIST_HEAD(&sor->client.list); 3725 sor->client.ops = &sor_client_ops; 3726 sor->client.dev = &pdev->dev; 3727 3728 err = host1x_client_register(&sor->client); 3729 if (err < 0) { 3730 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3731 err); 3732 goto remove; 3733 } 3734 3735 return 0; 3736 3737 remove: 3738 if (sor->ops && sor->ops->remove) 3739 sor->ops->remove(sor); 3740 output: 3741 tegra_output_remove(&sor->output); 3742 return err; 3743 } 3744 3745 static int tegra_sor_remove(struct platform_device *pdev) 3746 { 3747 struct tegra_sor *sor = platform_get_drvdata(pdev); 3748 int err; 3749 3750 pm_runtime_disable(&pdev->dev); 3751 3752 err = host1x_client_unregister(&sor->client); 3753 if (err < 0) { 3754 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 3755 err); 3756 return err; 3757 } 3758 3759 if (sor->ops && sor->ops->remove) { 3760 err = sor->ops->remove(sor); 3761 if (err < 0) 3762 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err); 3763 } 3764 3765 tegra_output_remove(&sor->output); 3766 3767 return 0; 3768 } 3769 3770 #ifdef CONFIG_PM 3771 static int tegra_sor_suspend(struct device *dev) 3772 { 3773 struct tegra_sor *sor = dev_get_drvdata(dev); 3774 int err; 3775 3776 if (sor->rst) { 3777 err = reset_control_assert(sor->rst); 3778 if (err < 0) { 3779 dev_err(dev, "failed to assert reset: %d\n", err); 3780 return err; 3781 } 3782 3783 reset_control_release(sor->rst); 3784 } 3785 3786 usleep_range(1000, 2000); 3787 3788 clk_disable_unprepare(sor->clk); 3789 3790 return 0; 3791 } 3792 3793 static int tegra_sor_resume(struct device *dev) 3794 { 3795 struct tegra_sor *sor = dev_get_drvdata(dev); 3796 int err; 3797 3798 err = clk_prepare_enable(sor->clk); 3799 if (err < 0) { 3800 dev_err(dev, "failed to enable clock: %d\n", err); 3801 return err; 3802 } 3803 3804 usleep_range(1000, 2000); 3805 3806 if (sor->rst) { 3807 err = reset_control_acquire(sor->rst); 3808 if (err < 0) { 3809 dev_err(dev, "failed to acquire reset: %d\n", err); 3810 clk_disable_unprepare(sor->clk); 3811 return err; 3812 } 3813 3814 err = reset_control_deassert(sor->rst); 3815 if (err < 0) { 3816 dev_err(dev, "failed to deassert reset: %d\n", err); 3817 reset_control_release(sor->rst); 3818 clk_disable_unprepare(sor->clk); 3819 return err; 3820 } 3821 } 3822 3823 return 0; 3824 } 3825 #endif 3826 3827 static const struct dev_pm_ops tegra_sor_pm_ops = { 3828 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL) 3829 }; 3830 3831 struct platform_driver tegra_sor_driver = { 3832 .driver = { 3833 .name = "tegra-sor", 3834 .of_match_table = tegra_sor_of_match, 3835 .pm = &tegra_sor_pm_ops, 3836 }, 3837 .probe = tegra_sor_probe, 3838 .remove = tegra_sor_remove, 3839 }; 3840