rv515.c (a2d07b7438f015a0349bc9af3c96a8164549bbc5) rv515.c (90aca4d2740255bd130ea71a91530b9920c70abe)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 132 unchanged lines hidden (view full) ---

141 WREG32(R_000300_VGA_RENDER_CONTROL,
142 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
143}
144
145void rv515_gpu_init(struct radeon_device *rdev)
146{
147 unsigned pipe_select_current, gb_pipe_select, tmp;
148
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 132 unchanged lines hidden (view full) ---

141 WREG32(R_000300_VGA_RENDER_CONTROL,
142 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
143}
144
145void rv515_gpu_init(struct radeon_device *rdev)
146{
147 unsigned pipe_select_current, gb_pipe_select, tmp;
148
149 r100_hdp_reset(rdev);
150 r100_rb2d_reset(rdev);
151
152 if (r100_gui_wait_for_idle(rdev)) {
153 printk(KERN_WARNING "Failed to wait GUI idle while "
154 "reseting GPU. Bad things might happen.\n");
155 }
149 if (r100_gui_wait_for_idle(rdev)) {
150 printk(KERN_WARNING "Failed to wait GUI idle while "
151 "reseting GPU. Bad things might happen.\n");
152 }
156
157 rv515_vga_render_disable(rdev);
153 rv515_vga_render_disable(rdev);
158
159 r420_pipes_init(rdev);
160 gb_pipe_select = RREG32(0x402C);
161 tmp = RREG32(0x170C);
162 pipe_select_current = (tmp >> 2) & 3;
163 tmp = (1 << pipe_select_current) |
164 (((gb_pipe_select >> 8) & 0xF) << 4);
165 WREG32_PLL(0x000D, tmp);
166 if (r100_gui_wait_for_idle(rdev)) {
167 printk(KERN_WARNING "Failed to wait GUI idle while "
168 "reseting GPU. Bad things might happen.\n");
169 }
170 if (rv515_mc_wait_for_idle(rdev)) {
171 printk(KERN_WARNING "Failed to wait MC idle while "
172 "programming pipes. Bad things might happen.\n");
173 }
174}
175
154 r420_pipes_init(rdev);
155 gb_pipe_select = RREG32(0x402C);
156 tmp = RREG32(0x170C);
157 pipe_select_current = (tmp >> 2) & 3;
158 tmp = (1 << pipe_select_current) |
159 (((gb_pipe_select >> 8) & 0xF) << 4);
160 WREG32_PLL(0x000D, tmp);
161 if (r100_gui_wait_for_idle(rdev)) {
162 printk(KERN_WARNING "Failed to wait GUI idle while "
163 "reseting GPU. Bad things might happen.\n");
164 }
165 if (rv515_mc_wait_for_idle(rdev)) {
166 printk(KERN_WARNING "Failed to wait MC idle while "
167 "programming pipes. Bad things might happen.\n");
168 }
169}
170
176int rv515_ga_reset(struct radeon_device *rdev)
177{
178 uint32_t tmp;
179 bool reinit_cp;
180 int i;
181
182 reinit_cp = rdev->cp.ready;
183 rdev->cp.ready = false;
184 for (i = 0; i < rdev->usec_timeout; i++) {
185 WREG32(CP_CSQ_MODE, 0);
186 WREG32(CP_CSQ_CNTL, 0);
187 WREG32(RBBM_SOFT_RESET, 0x32005);
188 (void)RREG32(RBBM_SOFT_RESET);
189 udelay(200);
190 WREG32(RBBM_SOFT_RESET, 0);
191 /* Wait to prevent race in RBBM_STATUS */
192 mdelay(1);
193 tmp = RREG32(RBBM_STATUS);
194 if (tmp & ((1 << 20) | (1 << 26))) {
195 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
196 /* GA still busy soft reset it */
197 WREG32(0x429C, 0x200);
198 WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
199 WREG32(0x43E0, 0);
200 WREG32(0x43E4, 0);
201 WREG32(0x24AC, 0);
202 }
203 /* Wait to prevent race in RBBM_STATUS */
204 mdelay(1);
205 tmp = RREG32(RBBM_STATUS);
206 if (!(tmp & ((1 << 20) | (1 << 26)))) {
207 break;
208 }
209 }
210 for (i = 0; i < rdev->usec_timeout; i++) {
211 tmp = RREG32(RBBM_STATUS);
212 if (!(tmp & ((1 << 20) | (1 << 26)))) {
213 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
214 tmp);
215 DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
216 DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
217 DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
218 if (reinit_cp) {
219 return r100_cp_init(rdev, rdev->cp.ring_size);
220 }
221 return 0;
222 }
223 DRM_UDELAY(1);
224 }
225 tmp = RREG32(RBBM_STATUS);
226 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
227 return -1;
228}
229
230int rv515_asic_reset(struct radeon_device *rdev)
231{
232 uint32_t status;
233
234 /* reset order likely matter */
235 status = RREG32(RBBM_STATUS);
236 /* reset HDP */
237 r100_hdp_reset(rdev);
238 /* reset rb2d */
239 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
240 r100_rb2d_reset(rdev);
241 }
242 /* reset GA */
243 if (status & ((1 << 20) | (1 << 26))) {
244 rv515_ga_reset(rdev);
245 }
246 /* reset CP */
247 status = RREG32(RBBM_STATUS);
248 if (status & (1 << 16)) {
249 r100_cp_reset(rdev);
250 }
251 /* Check if GPU is idle */
252 status = RREG32(RBBM_STATUS);
253 if (status & (1 << 31)) {
254 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
255 return -1;
256 }
257 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
258 return 0;
259}
260
261static void rv515_vram_get_type(struct radeon_device *rdev)
262{
263 uint32_t tmp;
264
265 rdev->mc.vram_width = 128;
266 rdev->mc.vram_is_ddr = true;
267 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
268 switch (tmp) {

--- 927 unchanged lines hidden --- 		171static void rv515_vram_get_type(struct radeon_device *rdev)
172{
173 uint32_t tmp;
174
175 rdev->mc.vram_width = 128;
176 rdev->mc.vram_is_ddr = true;
177 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
178 switch (tmp) {

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