1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include "drmP.h" 30 #include "rv515d.h" 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "atom.h" 34 #include "rv515_reg_safe.h" 35 36 /* This files gather functions specifics to: rv515 */ 37 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); 38 int rv515_debugfs_ga_info_init(struct radeon_device *rdev); 39 void rv515_gpu_init(struct radeon_device *rdev); 40 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 41 42 void rv515_debugfs(struct radeon_device *rdev) 43 { 44 if (r100_debugfs_rbbm_init(rdev)) { 45 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 46 } 47 if (rv515_debugfs_pipes_info_init(rdev)) { 48 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 49 } 50 if (rv515_debugfs_ga_info_init(rdev)) { 51 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 52 } 53 } 54 55 void rv515_ring_start(struct radeon_device *rdev) 56 { 57 int r; 58 59 r = radeon_ring_lock(rdev, 64); 60 if (r) { 61 return; 62 } 63 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); 64 radeon_ring_write(rdev, 65 ISYNC_ANY2D_IDLE3D | 66 ISYNC_ANY3D_IDLE2D | 67 ISYNC_WAIT_IDLEGUI | 68 ISYNC_CPSCRATCH_IDLEGUI); 69 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); 70 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 71 radeon_ring_write(rdev, PACKET0(0x170C, 0)); 72 radeon_ring_write(rdev, 1 << 31); 73 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); 74 radeon_ring_write(rdev, 0); 75 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); 76 radeon_ring_write(rdev, 0); 77 radeon_ring_write(rdev, PACKET0(0x42C8, 0)); 78 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); 79 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); 80 radeon_ring_write(rdev, 0); 81 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 82 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); 83 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 84 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); 85 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); 86 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 87 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); 88 radeon_ring_write(rdev, 0); 89 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 90 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); 91 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 92 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); 93 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); 94 radeon_ring_write(rdev, 95 ((6 << MS_X0_SHIFT) | 96 (6 << MS_Y0_SHIFT) | 97 (6 << MS_X1_SHIFT) | 98 (6 << MS_Y1_SHIFT) | 99 (6 << MS_X2_SHIFT) | 100 (6 << MS_Y2_SHIFT) | 101 (6 << MSBD0_Y_SHIFT) | 102 (6 << MSBD0_X_SHIFT))); 103 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); 104 radeon_ring_write(rdev, 105 ((6 << MS_X3_SHIFT) | 106 (6 << MS_Y3_SHIFT) | 107 (6 << MS_X4_SHIFT) | 108 (6 << MS_Y4_SHIFT) | 109 (6 << MS_X5_SHIFT) | 110 (6 << MS_Y5_SHIFT) | 111 (6 << MSBD1_SHIFT))); 112 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); 113 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 114 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); 115 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 116 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); 117 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 118 radeon_ring_write(rdev, PACKET0(0x20C8, 0)); 119 radeon_ring_write(rdev, 0); 120 radeon_ring_unlock_commit(rdev); 121 } 122 123 int rv515_mc_wait_for_idle(struct radeon_device *rdev) 124 { 125 unsigned i; 126 uint32_t tmp; 127 128 for (i = 0; i < rdev->usec_timeout; i++) { 129 /* read MC_STATUS */ 130 tmp = RREG32_MC(MC_STATUS); 131 if (tmp & MC_STATUS_IDLE) { 132 return 0; 133 } 134 DRM_UDELAY(1); 135 } 136 return -1; 137 } 138 139 void rv515_vga_render_disable(struct radeon_device *rdev) 140 { 141 WREG32(R_000300_VGA_RENDER_CONTROL, 142 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); 143 } 144 145 void rv515_gpu_init(struct radeon_device *rdev) 146 { 147 unsigned pipe_select_current, gb_pipe_select, tmp; 148 149 if (r100_gui_wait_for_idle(rdev)) { 150 printk(KERN_WARNING "Failed to wait GUI idle while " 151 "reseting GPU. Bad things might happen.\n"); 152 } 153 rv515_vga_render_disable(rdev); 154 r420_pipes_init(rdev); 155 gb_pipe_select = RREG32(0x402C); 156 tmp = RREG32(0x170C); 157 pipe_select_current = (tmp >> 2) & 3; 158 tmp = (1 << pipe_select_current) | 159 (((gb_pipe_select >> 8) & 0xF) << 4); 160 WREG32_PLL(0x000D, tmp); 161 if (r100_gui_wait_for_idle(rdev)) { 162 printk(KERN_WARNING "Failed to wait GUI idle while " 163 "reseting GPU. Bad things might happen.\n"); 164 } 165 if (rv515_mc_wait_for_idle(rdev)) { 166 printk(KERN_WARNING "Failed to wait MC idle while " 167 "programming pipes. Bad things might happen.\n"); 168 } 169 } 170 171 static void rv515_vram_get_type(struct radeon_device *rdev) 172 { 173 uint32_t tmp; 174 175 rdev->mc.vram_width = 128; 176 rdev->mc.vram_is_ddr = true; 177 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK; 178 switch (tmp) { 179 case 0: 180 rdev->mc.vram_width = 64; 181 break; 182 case 1: 183 rdev->mc.vram_width = 128; 184 break; 185 default: 186 rdev->mc.vram_width = 128; 187 break; 188 } 189 } 190 191 void rv515_mc_init(struct radeon_device *rdev) 192 { 193 194 rv515_vram_get_type(rdev); 195 r100_vram_init_sizes(rdev); 196 radeon_vram_location(rdev, &rdev->mc, 0); 197 if (!(rdev->flags & RADEON_IS_AGP)) 198 radeon_gtt_location(rdev, &rdev->mc); 199 radeon_update_bandwidth_info(rdev); 200 } 201 202 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) 203 { 204 uint32_t r; 205 206 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); 207 r = RREG32(MC_IND_DATA); 208 WREG32(MC_IND_INDEX, 0); 209 return r; 210 } 211 212 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 213 { 214 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); 215 WREG32(MC_IND_DATA, (v)); 216 WREG32(MC_IND_INDEX, 0); 217 } 218 219 #if defined(CONFIG_DEBUG_FS) 220 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) 221 { 222 struct drm_info_node *node = (struct drm_info_node *) m->private; 223 struct drm_device *dev = node->minor->dev; 224 struct radeon_device *rdev = dev->dev_private; 225 uint32_t tmp; 226 227 tmp = RREG32(GB_PIPE_SELECT); 228 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 229 tmp = RREG32(SU_REG_DEST); 230 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); 231 tmp = RREG32(GB_TILE_CONFIG); 232 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 233 tmp = RREG32(DST_PIPE_CONFIG); 234 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 235 return 0; 236 } 237 238 static int rv515_debugfs_ga_info(struct seq_file *m, void *data) 239 { 240 struct drm_info_node *node = (struct drm_info_node *) m->private; 241 struct drm_device *dev = node->minor->dev; 242 struct radeon_device *rdev = dev->dev_private; 243 uint32_t tmp; 244 245 tmp = RREG32(0x2140); 246 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); 247 radeon_asic_reset(rdev); 248 tmp = RREG32(0x425C); 249 seq_printf(m, "GA_IDLE 0x%08x\n", tmp); 250 return 0; 251 } 252 253 static struct drm_info_list rv515_pipes_info_list[] = { 254 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, 255 }; 256 257 static struct drm_info_list rv515_ga_info_list[] = { 258 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, 259 }; 260 #endif 261 262 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) 263 { 264 #if defined(CONFIG_DEBUG_FS) 265 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); 266 #else 267 return 0; 268 #endif 269 } 270 271 int rv515_debugfs_ga_info_init(struct radeon_device *rdev) 272 { 273 #if defined(CONFIG_DEBUG_FS) 274 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); 275 #else 276 return 0; 277 #endif 278 } 279 280 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) 281 { 282 save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); 283 save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); 284 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); 285 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); 286 save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); 287 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); 288 289 /* Stop all video */ 290 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 291 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 292 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 293 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 294 WREG32(R_006080_D1CRTC_CONTROL, 0); 295 WREG32(R_006880_D2CRTC_CONTROL, 0); 296 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 297 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 298 WREG32(R_000330_D1VGA_CONTROL, 0); 299 WREG32(R_000338_D2VGA_CONTROL, 0); 300 } 301 302 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 303 { 304 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 305 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 306 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); 307 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); 308 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); 309 /* Unlock host access */ 310 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 311 mdelay(1); 312 /* Restore video state */ 313 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); 314 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); 315 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 316 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 317 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); 318 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); 319 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 320 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 321 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 322 } 323 324 void rv515_mc_program(struct radeon_device *rdev) 325 { 326 struct rv515_mc_save save; 327 328 /* Stops all mc clients */ 329 rv515_mc_stop(rdev, &save); 330 331 /* Wait for mc idle */ 332 if (rv515_mc_wait_for_idle(rdev)) 333 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 334 /* Write VRAM size in case we are limiting it */ 335 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 336 /* Program MC, should be a 32bits limited address space */ 337 WREG32_MC(R_000001_MC_FB_LOCATION, 338 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | 339 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); 340 WREG32(R_000134_HDP_FB_LOCATION, 341 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 342 if (rdev->flags & RADEON_IS_AGP) { 343 WREG32_MC(R_000002_MC_AGP_LOCATION, 344 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | 345 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 346 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 347 WREG32_MC(R_000004_MC_AGP_BASE_2, 348 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 349 } else { 350 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); 351 WREG32_MC(R_000003_MC_AGP_BASE, 0); 352 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); 353 } 354 355 rv515_mc_resume(rdev, &save); 356 } 357 358 void rv515_clock_startup(struct radeon_device *rdev) 359 { 360 if (radeon_dynclks != -1 && radeon_dynclks) 361 radeon_atom_set_clock_gating(rdev, 1); 362 /* We need to force on some of the block */ 363 WREG32_PLL(R_00000F_CP_DYN_CNTL, 364 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); 365 WREG32_PLL(R_000011_E2_DYN_CNTL, 366 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); 367 WREG32_PLL(R_000013_IDCT_DYN_CNTL, 368 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); 369 } 370 371 static int rv515_startup(struct radeon_device *rdev) 372 { 373 int r; 374 375 rv515_mc_program(rdev); 376 /* Resume clock */ 377 rv515_clock_startup(rdev); 378 /* Initialize GPU configuration (# pipes, ...) */ 379 rv515_gpu_init(rdev); 380 /* Initialize GART (initialize after TTM so we can allocate 381 * memory through TTM but finalize after TTM) */ 382 if (rdev->flags & RADEON_IS_PCIE) { 383 r = rv370_pcie_gart_enable(rdev); 384 if (r) 385 return r; 386 } 387 /* Enable IRQ */ 388 rs600_irq_set(rdev); 389 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 390 /* 1M ring buffer */ 391 r = r100_cp_init(rdev, 1024 * 1024); 392 if (r) { 393 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 394 return r; 395 } 396 r = r100_wb_init(rdev); 397 if (r) 398 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 399 r = r100_ib_init(rdev); 400 if (r) { 401 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 402 return r; 403 } 404 return 0; 405 } 406 407 int rv515_resume(struct radeon_device *rdev) 408 { 409 /* Make sur GART are not working */ 410 if (rdev->flags & RADEON_IS_PCIE) 411 rv370_pcie_gart_disable(rdev); 412 /* Resume clock before doing reset */ 413 rv515_clock_startup(rdev); 414 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 415 if (radeon_asic_reset(rdev)) { 416 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 417 RREG32(R_000E40_RBBM_STATUS), 418 RREG32(R_0007C0_CP_STAT)); 419 } 420 /* post */ 421 atom_asic_init(rdev->mode_info.atom_context); 422 /* Resume clock after posting */ 423 rv515_clock_startup(rdev); 424 /* Initialize surface registers */ 425 radeon_surface_init(rdev); 426 return rv515_startup(rdev); 427 } 428 429 int rv515_suspend(struct radeon_device *rdev) 430 { 431 r100_cp_disable(rdev); 432 r100_wb_disable(rdev); 433 rs600_irq_disable(rdev); 434 if (rdev->flags & RADEON_IS_PCIE) 435 rv370_pcie_gart_disable(rdev); 436 return 0; 437 } 438 439 void rv515_set_safe_registers(struct radeon_device *rdev) 440 { 441 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; 442 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); 443 } 444 445 void rv515_fini(struct radeon_device *rdev) 446 { 447 radeon_pm_fini(rdev); 448 r100_cp_fini(rdev); 449 r100_wb_fini(rdev); 450 r100_ib_fini(rdev); 451 radeon_gem_fini(rdev); 452 rv370_pcie_gart_fini(rdev); 453 radeon_agp_fini(rdev); 454 radeon_irq_kms_fini(rdev); 455 radeon_fence_driver_fini(rdev); 456 radeon_bo_fini(rdev); 457 radeon_atombios_fini(rdev); 458 kfree(rdev->bios); 459 rdev->bios = NULL; 460 } 461 462 int rv515_init(struct radeon_device *rdev) 463 { 464 int r; 465 466 /* Initialize scratch registers */ 467 radeon_scratch_init(rdev); 468 /* Initialize surface registers */ 469 radeon_surface_init(rdev); 470 /* TODO: disable VGA need to use VGA request */ 471 /* BIOS*/ 472 if (!radeon_get_bios(rdev)) { 473 if (ASIC_IS_AVIVO(rdev)) 474 return -EINVAL; 475 } 476 if (rdev->is_atom_bios) { 477 r = radeon_atombios_init(rdev); 478 if (r) 479 return r; 480 } else { 481 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 482 return -EINVAL; 483 } 484 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 485 if (radeon_asic_reset(rdev)) { 486 dev_warn(rdev->dev, 487 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 488 RREG32(R_000E40_RBBM_STATUS), 489 RREG32(R_0007C0_CP_STAT)); 490 } 491 /* check if cards are posted or not */ 492 if (radeon_boot_test_post_card(rdev) == false) 493 return -EINVAL; 494 /* Initialize clocks */ 495 radeon_get_clock_info(rdev->ddev); 496 /* Initialize power management */ 497 radeon_pm_init(rdev); 498 /* initialize AGP */ 499 if (rdev->flags & RADEON_IS_AGP) { 500 r = radeon_agp_init(rdev); 501 if (r) { 502 radeon_agp_disable(rdev); 503 } 504 } 505 /* initialize memory controller */ 506 rv515_mc_init(rdev); 507 rv515_debugfs(rdev); 508 /* Fence driver */ 509 r = radeon_fence_driver_init(rdev); 510 if (r) 511 return r; 512 r = radeon_irq_kms_init(rdev); 513 if (r) 514 return r; 515 /* Memory manager */ 516 r = radeon_bo_init(rdev); 517 if (r) 518 return r; 519 r = rv370_pcie_gart_init(rdev); 520 if (r) 521 return r; 522 rv515_set_safe_registers(rdev); 523 rdev->accel_working = true; 524 r = rv515_startup(rdev); 525 if (r) { 526 /* Somethings want wront with the accel init stop accel */ 527 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 528 r100_cp_fini(rdev); 529 r100_wb_fini(rdev); 530 r100_ib_fini(rdev); 531 radeon_irq_kms_fini(rdev); 532 rv370_pcie_gart_fini(rdev); 533 radeon_agp_fini(rdev); 534 rdev->accel_working = false; 535 } 536 return 0; 537 } 538 539 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc) 540 { 541 int index_reg = 0x6578 + crtc->crtc_offset; 542 int data_reg = 0x657c + crtc->crtc_offset; 543 544 WREG32(0x659C + crtc->crtc_offset, 0x0); 545 WREG32(0x6594 + crtc->crtc_offset, 0x705); 546 WREG32(0x65A4 + crtc->crtc_offset, 0x10001); 547 WREG32(0x65D8 + crtc->crtc_offset, 0x0); 548 WREG32(0x65B0 + crtc->crtc_offset, 0x0); 549 WREG32(0x65C0 + crtc->crtc_offset, 0x0); 550 WREG32(0x65D4 + crtc->crtc_offset, 0x0); 551 WREG32(index_reg, 0x0); 552 WREG32(data_reg, 0x841880A8); 553 WREG32(index_reg, 0x1); 554 WREG32(data_reg, 0x84208680); 555 WREG32(index_reg, 0x2); 556 WREG32(data_reg, 0xBFF880B0); 557 WREG32(index_reg, 0x100); 558 WREG32(data_reg, 0x83D88088); 559 WREG32(index_reg, 0x101); 560 WREG32(data_reg, 0x84608680); 561 WREG32(index_reg, 0x102); 562 WREG32(data_reg, 0xBFF080D0); 563 WREG32(index_reg, 0x200); 564 WREG32(data_reg, 0x83988068); 565 WREG32(index_reg, 0x201); 566 WREG32(data_reg, 0x84A08680); 567 WREG32(index_reg, 0x202); 568 WREG32(data_reg, 0xBFF080F8); 569 WREG32(index_reg, 0x300); 570 WREG32(data_reg, 0x83588058); 571 WREG32(index_reg, 0x301); 572 WREG32(data_reg, 0x84E08660); 573 WREG32(index_reg, 0x302); 574 WREG32(data_reg, 0xBFF88120); 575 WREG32(index_reg, 0x400); 576 WREG32(data_reg, 0x83188040); 577 WREG32(index_reg, 0x401); 578 WREG32(data_reg, 0x85008660); 579 WREG32(index_reg, 0x402); 580 WREG32(data_reg, 0xBFF88150); 581 WREG32(index_reg, 0x500); 582 WREG32(data_reg, 0x82D88030); 583 WREG32(index_reg, 0x501); 584 WREG32(data_reg, 0x85408640); 585 WREG32(index_reg, 0x502); 586 WREG32(data_reg, 0xBFF88180); 587 WREG32(index_reg, 0x600); 588 WREG32(data_reg, 0x82A08018); 589 WREG32(index_reg, 0x601); 590 WREG32(data_reg, 0x85808620); 591 WREG32(index_reg, 0x602); 592 WREG32(data_reg, 0xBFF081B8); 593 WREG32(index_reg, 0x700); 594 WREG32(data_reg, 0x82608010); 595 WREG32(index_reg, 0x701); 596 WREG32(data_reg, 0x85A08600); 597 WREG32(index_reg, 0x702); 598 WREG32(data_reg, 0x800081F0); 599 WREG32(index_reg, 0x800); 600 WREG32(data_reg, 0x8228BFF8); 601 WREG32(index_reg, 0x801); 602 WREG32(data_reg, 0x85E085E0); 603 WREG32(index_reg, 0x802); 604 WREG32(data_reg, 0xBFF88228); 605 WREG32(index_reg, 0x10000); 606 WREG32(data_reg, 0x82A8BF00); 607 WREG32(index_reg, 0x10001); 608 WREG32(data_reg, 0x82A08CC0); 609 WREG32(index_reg, 0x10002); 610 WREG32(data_reg, 0x8008BEF8); 611 WREG32(index_reg, 0x10100); 612 WREG32(data_reg, 0x81F0BF28); 613 WREG32(index_reg, 0x10101); 614 WREG32(data_reg, 0x83608CA0); 615 WREG32(index_reg, 0x10102); 616 WREG32(data_reg, 0x8018BED0); 617 WREG32(index_reg, 0x10200); 618 WREG32(data_reg, 0x8148BF38); 619 WREG32(index_reg, 0x10201); 620 WREG32(data_reg, 0x84408C80); 621 WREG32(index_reg, 0x10202); 622 WREG32(data_reg, 0x8008BEB8); 623 WREG32(index_reg, 0x10300); 624 WREG32(data_reg, 0x80B0BF78); 625 WREG32(index_reg, 0x10301); 626 WREG32(data_reg, 0x85008C20); 627 WREG32(index_reg, 0x10302); 628 WREG32(data_reg, 0x8020BEA0); 629 WREG32(index_reg, 0x10400); 630 WREG32(data_reg, 0x8028BF90); 631 WREG32(index_reg, 0x10401); 632 WREG32(data_reg, 0x85E08BC0); 633 WREG32(index_reg, 0x10402); 634 WREG32(data_reg, 0x8018BE90); 635 WREG32(index_reg, 0x10500); 636 WREG32(data_reg, 0xBFB8BFB0); 637 WREG32(index_reg, 0x10501); 638 WREG32(data_reg, 0x86C08B40); 639 WREG32(index_reg, 0x10502); 640 WREG32(data_reg, 0x8010BE90); 641 WREG32(index_reg, 0x10600); 642 WREG32(data_reg, 0xBF58BFC8); 643 WREG32(index_reg, 0x10601); 644 WREG32(data_reg, 0x87A08AA0); 645 WREG32(index_reg, 0x10602); 646 WREG32(data_reg, 0x8010BE98); 647 WREG32(index_reg, 0x10700); 648 WREG32(data_reg, 0xBF10BFF0); 649 WREG32(index_reg, 0x10701); 650 WREG32(data_reg, 0x886089E0); 651 WREG32(index_reg, 0x10702); 652 WREG32(data_reg, 0x8018BEB0); 653 WREG32(index_reg, 0x10800); 654 WREG32(data_reg, 0xBED8BFE8); 655 WREG32(index_reg, 0x10801); 656 WREG32(data_reg, 0x89408940); 657 WREG32(index_reg, 0x10802); 658 WREG32(data_reg, 0xBFE8BED8); 659 WREG32(index_reg, 0x20000); 660 WREG32(data_reg, 0x80008000); 661 WREG32(index_reg, 0x20001); 662 WREG32(data_reg, 0x90008000); 663 WREG32(index_reg, 0x20002); 664 WREG32(data_reg, 0x80008000); 665 WREG32(index_reg, 0x20003); 666 WREG32(data_reg, 0x80008000); 667 WREG32(index_reg, 0x20100); 668 WREG32(data_reg, 0x80108000); 669 WREG32(index_reg, 0x20101); 670 WREG32(data_reg, 0x8FE0BF70); 671 WREG32(index_reg, 0x20102); 672 WREG32(data_reg, 0xBFE880C0); 673 WREG32(index_reg, 0x20103); 674 WREG32(data_reg, 0x80008000); 675 WREG32(index_reg, 0x20200); 676 WREG32(data_reg, 0x8018BFF8); 677 WREG32(index_reg, 0x20201); 678 WREG32(data_reg, 0x8F80BF08); 679 WREG32(index_reg, 0x20202); 680 WREG32(data_reg, 0xBFD081A0); 681 WREG32(index_reg, 0x20203); 682 WREG32(data_reg, 0xBFF88000); 683 WREG32(index_reg, 0x20300); 684 WREG32(data_reg, 0x80188000); 685 WREG32(index_reg, 0x20301); 686 WREG32(data_reg, 0x8EE0BEC0); 687 WREG32(index_reg, 0x20302); 688 WREG32(data_reg, 0xBFB082A0); 689 WREG32(index_reg, 0x20303); 690 WREG32(data_reg, 0x80008000); 691 WREG32(index_reg, 0x20400); 692 WREG32(data_reg, 0x80188000); 693 WREG32(index_reg, 0x20401); 694 WREG32(data_reg, 0x8E00BEA0); 695 WREG32(index_reg, 0x20402); 696 WREG32(data_reg, 0xBF8883C0); 697 WREG32(index_reg, 0x20403); 698 WREG32(data_reg, 0x80008000); 699 WREG32(index_reg, 0x20500); 700 WREG32(data_reg, 0x80188000); 701 WREG32(index_reg, 0x20501); 702 WREG32(data_reg, 0x8D00BE90); 703 WREG32(index_reg, 0x20502); 704 WREG32(data_reg, 0xBF588500); 705 WREG32(index_reg, 0x20503); 706 WREG32(data_reg, 0x80008008); 707 WREG32(index_reg, 0x20600); 708 WREG32(data_reg, 0x80188000); 709 WREG32(index_reg, 0x20601); 710 WREG32(data_reg, 0x8BC0BE98); 711 WREG32(index_reg, 0x20602); 712 WREG32(data_reg, 0xBF308660); 713 WREG32(index_reg, 0x20603); 714 WREG32(data_reg, 0x80008008); 715 WREG32(index_reg, 0x20700); 716 WREG32(data_reg, 0x80108000); 717 WREG32(index_reg, 0x20701); 718 WREG32(data_reg, 0x8A80BEB0); 719 WREG32(index_reg, 0x20702); 720 WREG32(data_reg, 0xBF0087C0); 721 WREG32(index_reg, 0x20703); 722 WREG32(data_reg, 0x80008008); 723 WREG32(index_reg, 0x20800); 724 WREG32(data_reg, 0x80108000); 725 WREG32(index_reg, 0x20801); 726 WREG32(data_reg, 0x8920BED0); 727 WREG32(index_reg, 0x20802); 728 WREG32(data_reg, 0xBED08920); 729 WREG32(index_reg, 0x20803); 730 WREG32(data_reg, 0x80008010); 731 WREG32(index_reg, 0x30000); 732 WREG32(data_reg, 0x90008000); 733 WREG32(index_reg, 0x30001); 734 WREG32(data_reg, 0x80008000); 735 WREG32(index_reg, 0x30100); 736 WREG32(data_reg, 0x8FE0BF90); 737 WREG32(index_reg, 0x30101); 738 WREG32(data_reg, 0xBFF880A0); 739 WREG32(index_reg, 0x30200); 740 WREG32(data_reg, 0x8F60BF40); 741 WREG32(index_reg, 0x30201); 742 WREG32(data_reg, 0xBFE88180); 743 WREG32(index_reg, 0x30300); 744 WREG32(data_reg, 0x8EC0BF00); 745 WREG32(index_reg, 0x30301); 746 WREG32(data_reg, 0xBFC88280); 747 WREG32(index_reg, 0x30400); 748 WREG32(data_reg, 0x8DE0BEE0); 749 WREG32(index_reg, 0x30401); 750 WREG32(data_reg, 0xBFA083A0); 751 WREG32(index_reg, 0x30500); 752 WREG32(data_reg, 0x8CE0BED0); 753 WREG32(index_reg, 0x30501); 754 WREG32(data_reg, 0xBF7884E0); 755 WREG32(index_reg, 0x30600); 756 WREG32(data_reg, 0x8BA0BED8); 757 WREG32(index_reg, 0x30601); 758 WREG32(data_reg, 0xBF508640); 759 WREG32(index_reg, 0x30700); 760 WREG32(data_reg, 0x8A60BEE8); 761 WREG32(index_reg, 0x30701); 762 WREG32(data_reg, 0xBF2087A0); 763 WREG32(index_reg, 0x30800); 764 WREG32(data_reg, 0x8900BF00); 765 WREG32(index_reg, 0x30801); 766 WREG32(data_reg, 0xBF008900); 767 } 768 769 struct rv515_watermark { 770 u32 lb_request_fifo_depth; 771 fixed20_12 num_line_pair; 772 fixed20_12 estimated_width; 773 fixed20_12 worst_case_latency; 774 fixed20_12 consumption_rate; 775 fixed20_12 active_time; 776 fixed20_12 dbpp; 777 fixed20_12 priority_mark_max; 778 fixed20_12 priority_mark; 779 fixed20_12 sclk; 780 }; 781 782 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev, 783 struct radeon_crtc *crtc, 784 struct rv515_watermark *wm) 785 { 786 struct drm_display_mode *mode = &crtc->base.mode; 787 fixed20_12 a, b, c; 788 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 789 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 790 791 if (!crtc->base.enabled) { 792 /* FIXME: wouldn't it better to set priority mark to maximum */ 793 wm->lb_request_fifo_depth = 4; 794 return; 795 } 796 797 if (crtc->vsc.full > rfixed_const(2)) 798 wm->num_line_pair.full = rfixed_const(2); 799 else 800 wm->num_line_pair.full = rfixed_const(1); 801 802 b.full = rfixed_const(mode->crtc_hdisplay); 803 c.full = rfixed_const(256); 804 a.full = rfixed_div(b, c); 805 request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair); 806 request_fifo_depth.full = rfixed_ceil(request_fifo_depth); 807 if (a.full < rfixed_const(4)) { 808 wm->lb_request_fifo_depth = 4; 809 } else { 810 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); 811 } 812 813 /* Determine consumption rate 814 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 815 * vtaps = number of vertical taps, 816 * vsc = vertical scaling ratio, defined as source/destination 817 * hsc = horizontal scaling ration, defined as source/destination 818 */ 819 a.full = rfixed_const(mode->clock); 820 b.full = rfixed_const(1000); 821 a.full = rfixed_div(a, b); 822 pclk.full = rfixed_div(b, a); 823 if (crtc->rmx_type != RMX_OFF) { 824 b.full = rfixed_const(2); 825 if (crtc->vsc.full > b.full) 826 b.full = crtc->vsc.full; 827 b.full = rfixed_mul(b, crtc->hsc); 828 c.full = rfixed_const(2); 829 b.full = rfixed_div(b, c); 830 consumption_time.full = rfixed_div(pclk, b); 831 } else { 832 consumption_time.full = pclk.full; 833 } 834 a.full = rfixed_const(1); 835 wm->consumption_rate.full = rfixed_div(a, consumption_time); 836 837 838 /* Determine line time 839 * LineTime = total time for one line of displayhtotal 840 * LineTime = total number of horizontal pixels 841 * pclk = pixel clock period(ns) 842 */ 843 a.full = rfixed_const(crtc->base.mode.crtc_htotal); 844 line_time.full = rfixed_mul(a, pclk); 845 846 /* Determine active time 847 * ActiveTime = time of active region of display within one line, 848 * hactive = total number of horizontal active pixels 849 * htotal = total number of horizontal pixels 850 */ 851 a.full = rfixed_const(crtc->base.mode.crtc_htotal); 852 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); 853 wm->active_time.full = rfixed_mul(line_time, b); 854 wm->active_time.full = rfixed_div(wm->active_time, a); 855 856 /* Determine chunk time 857 * ChunkTime = the time it takes the DCP to send one chunk of data 858 * to the LB which consists of pipeline delay and inter chunk gap 859 * sclk = system clock(Mhz) 860 */ 861 a.full = rfixed_const(600 * 1000); 862 chunk_time.full = rfixed_div(a, rdev->pm.sclk); 863 read_delay_latency.full = rfixed_const(1000); 864 865 /* Determine the worst case latency 866 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 867 * WorstCaseLatency = worst case time from urgent to when the MC starts 868 * to return data 869 * READ_DELAY_IDLE_MAX = constant of 1us 870 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 871 * which consists of pipeline delay and inter chunk gap 872 */ 873 if (rfixed_trunc(wm->num_line_pair) > 1) { 874 a.full = rfixed_const(3); 875 wm->worst_case_latency.full = rfixed_mul(a, chunk_time); 876 wm->worst_case_latency.full += read_delay_latency.full; 877 } else { 878 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; 879 } 880 881 /* Determine the tolerable latency 882 * TolerableLatency = Any given request has only 1 line time 883 * for the data to be returned 884 * LBRequestFifoDepth = Number of chunk requests the LB can 885 * put into the request FIFO for a display 886 * LineTime = total time for one line of display 887 * ChunkTime = the time it takes the DCP to send one chunk 888 * of data to the LB which consists of 889 * pipeline delay and inter chunk gap 890 */ 891 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { 892 tolerable_latency.full = line_time.full; 893 } else { 894 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); 895 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 896 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); 897 tolerable_latency.full = line_time.full - tolerable_latency.full; 898 } 899 /* We assume worst case 32bits (4 bytes) */ 900 wm->dbpp.full = rfixed_const(2 * 16); 901 902 /* Determine the maximum priority mark 903 * width = viewport width in pixels 904 */ 905 a.full = rfixed_const(16); 906 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); 907 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); 908 wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max); 909 910 /* Determine estimated width */ 911 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 912 estimated_width.full = rfixed_div(estimated_width, consumption_time); 913 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 914 wm->priority_mark.full = wm->priority_mark_max.full; 915 } else { 916 a.full = rfixed_const(16); 917 wm->priority_mark.full = rfixed_div(estimated_width, a); 918 wm->priority_mark.full = rfixed_ceil(wm->priority_mark); 919 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 920 } 921 } 922 923 void rv515_bandwidth_avivo_update(struct radeon_device *rdev) 924 { 925 struct drm_display_mode *mode0 = NULL; 926 struct drm_display_mode *mode1 = NULL; 927 struct rv515_watermark wm0; 928 struct rv515_watermark wm1; 929 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt; 930 fixed20_12 priority_mark02, priority_mark12, fill_rate; 931 fixed20_12 a, b; 932 933 if (rdev->mode_info.crtcs[0]->base.enabled) 934 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 935 if (rdev->mode_info.crtcs[1]->base.enabled) 936 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 937 rs690_line_buffer_adjust(rdev, mode0, mode1); 938 939 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 940 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 941 942 tmp = wm0.lb_request_fifo_depth; 943 tmp |= wm1.lb_request_fifo_depth << 16; 944 WREG32(LB_MAX_REQ_OUTSTANDING, tmp); 945 946 if (mode0 && mode1) { 947 if (rfixed_trunc(wm0.dbpp) > 64) 948 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); 949 else 950 a.full = wm0.num_line_pair.full; 951 if (rfixed_trunc(wm1.dbpp) > 64) 952 b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); 953 else 954 b.full = wm1.num_line_pair.full; 955 a.full += b.full; 956 fill_rate.full = rfixed_div(wm0.sclk, a); 957 if (wm0.consumption_rate.full > fill_rate.full) { 958 b.full = wm0.consumption_rate.full - fill_rate.full; 959 b.full = rfixed_mul(b, wm0.active_time); 960 a.full = rfixed_const(16); 961 b.full = rfixed_div(b, a); 962 a.full = rfixed_mul(wm0.worst_case_latency, 963 wm0.consumption_rate); 964 priority_mark02.full = a.full + b.full; 965 } else { 966 a.full = rfixed_mul(wm0.worst_case_latency, 967 wm0.consumption_rate); 968 b.full = rfixed_const(16 * 1000); 969 priority_mark02.full = rfixed_div(a, b); 970 } 971 if (wm1.consumption_rate.full > fill_rate.full) { 972 b.full = wm1.consumption_rate.full - fill_rate.full; 973 b.full = rfixed_mul(b, wm1.active_time); 974 a.full = rfixed_const(16); 975 b.full = rfixed_div(b, a); 976 a.full = rfixed_mul(wm1.worst_case_latency, 977 wm1.consumption_rate); 978 priority_mark12.full = a.full + b.full; 979 } else { 980 a.full = rfixed_mul(wm1.worst_case_latency, 981 wm1.consumption_rate); 982 b.full = rfixed_const(16 * 1000); 983 priority_mark12.full = rfixed_div(a, b); 984 } 985 if (wm0.priority_mark.full > priority_mark02.full) 986 priority_mark02.full = wm0.priority_mark.full; 987 if (rfixed_trunc(priority_mark02) < 0) 988 priority_mark02.full = 0; 989 if (wm0.priority_mark_max.full > priority_mark02.full) 990 priority_mark02.full = wm0.priority_mark_max.full; 991 if (wm1.priority_mark.full > priority_mark12.full) 992 priority_mark12.full = wm1.priority_mark.full; 993 if (rfixed_trunc(priority_mark12) < 0) 994 priority_mark12.full = 0; 995 if (wm1.priority_mark_max.full > priority_mark12.full) 996 priority_mark12.full = wm1.priority_mark_max.full; 997 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); 998 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); 999 if (rdev->disp_priority == 2) { 1000 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1001 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1002 } 1003 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1004 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 1005 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1006 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 1007 } else if (mode0) { 1008 if (rfixed_trunc(wm0.dbpp) > 64) 1009 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); 1010 else 1011 a.full = wm0.num_line_pair.full; 1012 fill_rate.full = rfixed_div(wm0.sclk, a); 1013 if (wm0.consumption_rate.full > fill_rate.full) { 1014 b.full = wm0.consumption_rate.full - fill_rate.full; 1015 b.full = rfixed_mul(b, wm0.active_time); 1016 a.full = rfixed_const(16); 1017 b.full = rfixed_div(b, a); 1018 a.full = rfixed_mul(wm0.worst_case_latency, 1019 wm0.consumption_rate); 1020 priority_mark02.full = a.full + b.full; 1021 } else { 1022 a.full = rfixed_mul(wm0.worst_case_latency, 1023 wm0.consumption_rate); 1024 b.full = rfixed_const(16); 1025 priority_mark02.full = rfixed_div(a, b); 1026 } 1027 if (wm0.priority_mark.full > priority_mark02.full) 1028 priority_mark02.full = wm0.priority_mark.full; 1029 if (rfixed_trunc(priority_mark02) < 0) 1030 priority_mark02.full = 0; 1031 if (wm0.priority_mark_max.full > priority_mark02.full) 1032 priority_mark02.full = wm0.priority_mark_max.full; 1033 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02); 1034 if (rdev->disp_priority == 2) 1035 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1036 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 1037 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 1038 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); 1039 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); 1040 } else { 1041 if (rfixed_trunc(wm1.dbpp) > 64) 1042 a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair); 1043 else 1044 a.full = wm1.num_line_pair.full; 1045 fill_rate.full = rfixed_div(wm1.sclk, a); 1046 if (wm1.consumption_rate.full > fill_rate.full) { 1047 b.full = wm1.consumption_rate.full - fill_rate.full; 1048 b.full = rfixed_mul(b, wm1.active_time); 1049 a.full = rfixed_const(16); 1050 b.full = rfixed_div(b, a); 1051 a.full = rfixed_mul(wm1.worst_case_latency, 1052 wm1.consumption_rate); 1053 priority_mark12.full = a.full + b.full; 1054 } else { 1055 a.full = rfixed_mul(wm1.worst_case_latency, 1056 wm1.consumption_rate); 1057 b.full = rfixed_const(16 * 1000); 1058 priority_mark12.full = rfixed_div(a, b); 1059 } 1060 if (wm1.priority_mark.full > priority_mark12.full) 1061 priority_mark12.full = wm1.priority_mark.full; 1062 if (rfixed_trunc(priority_mark12) < 0) 1063 priority_mark12.full = 0; 1064 if (wm1.priority_mark_max.full > priority_mark12.full) 1065 priority_mark12.full = wm1.priority_mark_max.full; 1066 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12); 1067 if (rdev->disp_priority == 2) 1068 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON; 1069 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); 1070 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); 1071 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 1072 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 1073 } 1074 } 1075 1076 void rv515_bandwidth_update(struct radeon_device *rdev) 1077 { 1078 uint32_t tmp; 1079 struct drm_display_mode *mode0 = NULL; 1080 struct drm_display_mode *mode1 = NULL; 1081 1082 radeon_update_display_priority(rdev); 1083 1084 if (rdev->mode_info.crtcs[0]->base.enabled) 1085 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1086 if (rdev->mode_info.crtcs[1]->base.enabled) 1087 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 1088 /* 1089 * Set display0/1 priority up in the memory controller for 1090 * modes if the user specifies HIGH for displaypriority 1091 * option. 1092 */ 1093 if ((rdev->disp_priority == 2) && 1094 (rdev->family == CHIP_RV515)) { 1095 tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1096 tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1097 tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1098 if (mode1) 1099 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); 1100 if (mode0) 1101 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); 1102 WREG32_MC(MC_MISC_LAT_TIMER, tmp); 1103 } 1104 rv515_bandwidth_avivo_update(rdev); 1105 } 1106