r600.c (a2d07b7438f015a0349bc9af3c96a8164549bbc5) r600.c (90aca4d2740255bd130ea71a91530b9920c70abe)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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744 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
745 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
746 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
747 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
748 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
749 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
750 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
751 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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744 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
745 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
746 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
747 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
748 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
749 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
750 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
751 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
752 u32 srbm_reset = 0;
753 u32 tmp;
754
755 dev_info(rdev->dev, "GPU softreset \n");
756 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
757 RREG32(R_008010_GRBM_STATUS));
758 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
759 RREG32(R_008014_GRBM_STATUS2));
760 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
761 RREG32(R_000E50_SRBM_STATUS));
762 rv515_mc_stop(rdev, &save);
763 if (r600_mc_wait_for_idle(rdev)) {
764 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
765 }
766 /* Disable CP parsing/prefetching */
752 u32 tmp;
753
754 dev_info(rdev->dev, "GPU softreset \n");
755 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
756 RREG32(R_008010_GRBM_STATUS));
757 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
758 RREG32(R_008014_GRBM_STATUS2));
759 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
760 RREG32(R_000E50_SRBM_STATUS));
761 rv515_mc_stop(rdev, &save);
762 if (r600_mc_wait_for_idle(rdev)) {
763 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
764 }
765 /* Disable CP parsing/prefetching */
767 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
766 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
768 /* Check if any of the rendering block is busy and reset it */
769 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
770 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
771 tmp = S_008020_SOFT_RESET_CR(1) |
772 S_008020_SOFT_RESET_DB(1) |
773 S_008020_SOFT_RESET_CB(1) |
774 S_008020_SOFT_RESET_PA(1) |
775 S_008020_SOFT_RESET_SC(1) |
776 S_008020_SOFT_RESET_SMX(1) |
777 S_008020_SOFT_RESET_SPI(1) |
778 S_008020_SOFT_RESET_SX(1) |
779 S_008020_SOFT_RESET_SH(1) |
780 S_008020_SOFT_RESET_TC(1) |
781 S_008020_SOFT_RESET_TA(1) |
782 S_008020_SOFT_RESET_VC(1) |
783 S_008020_SOFT_RESET_VGT(1);
784 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
785 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
767 /* Check if any of the rendering block is busy and reset it */
768 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
769 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
770 tmp = S_008020_SOFT_RESET_CR(1) |
771 S_008020_SOFT_RESET_DB(1) |
772 S_008020_SOFT_RESET_CB(1) |
773 S_008020_SOFT_RESET_PA(1) |
774 S_008020_SOFT_RESET_SC(1) |
775 S_008020_SOFT_RESET_SMX(1) |
776 S_008020_SOFT_RESET_SPI(1) |
777 S_008020_SOFT_RESET_SX(1) |
778 S_008020_SOFT_RESET_SH(1) |
779 S_008020_SOFT_RESET_TC(1) |
780 S_008020_SOFT_RESET_TA(1) |
781 S_008020_SOFT_RESET_VC(1) |
782 S_008020_SOFT_RESET_VGT(1);
783 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
784 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
786 (void)RREG32(R_008020_GRBM_SOFT_RESET);
787 mdelay(1);
785 RREG32(R_008020_GRBM_SOFT_RESET);
786 mdelay(15);
788 WREG32(R_008020_GRBM_SOFT_RESET, 0);
787 WREG32(R_008020_GRBM_SOFT_RESET, 0);
789 (void)RREG32(R_008020_GRBM_SOFT_RESET);
790 }
791 /* Reset CP (we always reset CP) */
792 tmp = S_008020_SOFT_RESET_CP(1);
793 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
794 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
788 }
789 /* Reset CP (we always reset CP) */
790 tmp = S_008020_SOFT_RESET_CP(1);
791 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
792 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
795 (void)RREG32(R_008020_GRBM_SOFT_RESET);
796 udelay(50);
793 RREG32(R_008020_GRBM_SOFT_RESET);
794 mdelay(15);
797 WREG32(R_008020_GRBM_SOFT_RESET, 0);
795 WREG32(R_008020_GRBM_SOFT_RESET, 0);
798 (void)RREG32(R_008020_GRBM_SOFT_RESET);
799 /* Reset others GPU block if necessary */
800 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
801 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
802 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
803 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
804 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
805 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
806 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
807 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
808 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
809 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
810 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
811 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
812 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
813 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
814 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
815 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
816 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
817 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
818 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
819 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
820 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
821 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
822 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
823 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
824 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
825 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
826 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
827 mdelay(1);
828 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
829 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
830 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
831 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
832 mdelay(1);
833 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
834 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
835 /* Wait a little for things to settle down */
836 mdelay(1);
837 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
838 RREG32(R_008010_GRBM_STATUS));
839 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
840 RREG32(R_008014_GRBM_STATUS2));
841 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
842 RREG32(R_000E50_SRBM_STATUS));
796 /* Wait a little for things to settle down */
797 mdelay(1);
798 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
799 RREG32(R_008010_GRBM_STATUS));
800 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
801 RREG32(R_008014_GRBM_STATUS2));
802 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
803 RREG32(R_000E50_SRBM_STATUS));
843 /* After reset we need to reinit the asic as GPU often endup in an
844 * incoherent state.
845 */
846 atom_asic_init(rdev->mode_info.atom_context);
847 rv515_mc_resume(rdev, &save);
848 return 0;
849}
850
851bool r600_gpu_is_lockup(struct radeon_device *rdev)
852{
853 u32 srbm_status;
854 u32 grbm_status;

--- 2124 unchanged lines hidden --- 		804 rv515_mc_resume(rdev, &save);
805 return 0;
806}
807
808bool r600_gpu_is_lockup(struct radeon_device *rdev)
809{
810 u32 srbm_status;
811 u32 grbm_status;

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