1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/firmware.h> 30 #include <linux/platform_device.h> 31 #include "drmP.h" 32 #include "radeon_drm.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include "radeon_mode.h" 36 #include "r600d.h" 37 #include "atom.h" 38 #include "avivod.h" 39 40 #define PFP_UCODE_SIZE 576 41 #define PM4_UCODE_SIZE 1792 42 #define RLC_UCODE_SIZE 768 43 #define R700_PFP_UCODE_SIZE 848 44 #define R700_PM4_UCODE_SIZE 1360 45 #define R700_RLC_UCODE_SIZE 1024 46 47 /* Firmware Names */ 48 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 49 MODULE_FIRMWARE("radeon/R600_me.bin"); 50 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 51 MODULE_FIRMWARE("radeon/RV610_me.bin"); 52 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 53 MODULE_FIRMWARE("radeon/RV630_me.bin"); 54 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 55 MODULE_FIRMWARE("radeon/RV620_me.bin"); 56 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 57 MODULE_FIRMWARE("radeon/RV635_me.bin"); 58 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 59 MODULE_FIRMWARE("radeon/RV670_me.bin"); 60 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 61 MODULE_FIRMWARE("radeon/RS780_me.bin"); 62 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 63 MODULE_FIRMWARE("radeon/RV770_me.bin"); 64 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 65 MODULE_FIRMWARE("radeon/RV730_me.bin"); 66 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 67 MODULE_FIRMWARE("radeon/RV710_me.bin"); 68 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 69 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 70 71 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 72 73 /* r600,rv610,rv630,rv620,rv635,rv670 */ 74 int r600_mc_wait_for_idle(struct radeon_device *rdev); 75 void r600_gpu_init(struct radeon_device *rdev); 76 void r600_fini(struct radeon_device *rdev); 77 78 /* hpd for digital panel detect/disconnect */ 79 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 80 { 81 bool connected = false; 82 83 if (ASIC_IS_DCE3(rdev)) { 84 switch (hpd) { 85 case RADEON_HPD_1: 86 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 87 connected = true; 88 break; 89 case RADEON_HPD_2: 90 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 91 connected = true; 92 break; 93 case RADEON_HPD_3: 94 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 95 connected = true; 96 break; 97 case RADEON_HPD_4: 98 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 99 connected = true; 100 break; 101 /* DCE 3.2 */ 102 case RADEON_HPD_5: 103 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 104 connected = true; 105 break; 106 case RADEON_HPD_6: 107 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 108 connected = true; 109 break; 110 default: 111 break; 112 } 113 } else { 114 switch (hpd) { 115 case RADEON_HPD_1: 116 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 117 connected = true; 118 break; 119 case RADEON_HPD_2: 120 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 121 connected = true; 122 break; 123 case RADEON_HPD_3: 124 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 125 connected = true; 126 break; 127 default: 128 break; 129 } 130 } 131 return connected; 132 } 133 134 void r600_hpd_set_polarity(struct radeon_device *rdev, 135 enum radeon_hpd_id hpd) 136 { 137 u32 tmp; 138 bool connected = r600_hpd_sense(rdev, hpd); 139 140 if (ASIC_IS_DCE3(rdev)) { 141 switch (hpd) { 142 case RADEON_HPD_1: 143 tmp = RREG32(DC_HPD1_INT_CONTROL); 144 if (connected) 145 tmp &= ~DC_HPDx_INT_POLARITY; 146 else 147 tmp |= DC_HPDx_INT_POLARITY; 148 WREG32(DC_HPD1_INT_CONTROL, tmp); 149 break; 150 case RADEON_HPD_2: 151 tmp = RREG32(DC_HPD2_INT_CONTROL); 152 if (connected) 153 tmp &= ~DC_HPDx_INT_POLARITY; 154 else 155 tmp |= DC_HPDx_INT_POLARITY; 156 WREG32(DC_HPD2_INT_CONTROL, tmp); 157 break; 158 case RADEON_HPD_3: 159 tmp = RREG32(DC_HPD3_INT_CONTROL); 160 if (connected) 161 tmp &= ~DC_HPDx_INT_POLARITY; 162 else 163 tmp |= DC_HPDx_INT_POLARITY; 164 WREG32(DC_HPD3_INT_CONTROL, tmp); 165 break; 166 case RADEON_HPD_4: 167 tmp = RREG32(DC_HPD4_INT_CONTROL); 168 if (connected) 169 tmp &= ~DC_HPDx_INT_POLARITY; 170 else 171 tmp |= DC_HPDx_INT_POLARITY; 172 WREG32(DC_HPD4_INT_CONTROL, tmp); 173 break; 174 case RADEON_HPD_5: 175 tmp = RREG32(DC_HPD5_INT_CONTROL); 176 if (connected) 177 tmp &= ~DC_HPDx_INT_POLARITY; 178 else 179 tmp |= DC_HPDx_INT_POLARITY; 180 WREG32(DC_HPD5_INT_CONTROL, tmp); 181 break; 182 /* DCE 3.2 */ 183 case RADEON_HPD_6: 184 tmp = RREG32(DC_HPD6_INT_CONTROL); 185 if (connected) 186 tmp &= ~DC_HPDx_INT_POLARITY; 187 else 188 tmp |= DC_HPDx_INT_POLARITY; 189 WREG32(DC_HPD6_INT_CONTROL, tmp); 190 break; 191 default: 192 break; 193 } 194 } else { 195 switch (hpd) { 196 case RADEON_HPD_1: 197 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 198 if (connected) 199 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 200 else 201 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 202 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 203 break; 204 case RADEON_HPD_2: 205 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 206 if (connected) 207 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 208 else 209 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 210 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 211 break; 212 case RADEON_HPD_3: 213 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 214 if (connected) 215 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 216 else 217 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 218 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 219 break; 220 default: 221 break; 222 } 223 } 224 } 225 226 void r600_hpd_init(struct radeon_device *rdev) 227 { 228 struct drm_device *dev = rdev->ddev; 229 struct drm_connector *connector; 230 231 if (ASIC_IS_DCE3(rdev)) { 232 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 233 if (ASIC_IS_DCE32(rdev)) 234 tmp |= DC_HPDx_EN; 235 236 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 237 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 238 switch (radeon_connector->hpd.hpd) { 239 case RADEON_HPD_1: 240 WREG32(DC_HPD1_CONTROL, tmp); 241 rdev->irq.hpd[0] = true; 242 break; 243 case RADEON_HPD_2: 244 WREG32(DC_HPD2_CONTROL, tmp); 245 rdev->irq.hpd[1] = true; 246 break; 247 case RADEON_HPD_3: 248 WREG32(DC_HPD3_CONTROL, tmp); 249 rdev->irq.hpd[2] = true; 250 break; 251 case RADEON_HPD_4: 252 WREG32(DC_HPD4_CONTROL, tmp); 253 rdev->irq.hpd[3] = true; 254 break; 255 /* DCE 3.2 */ 256 case RADEON_HPD_5: 257 WREG32(DC_HPD5_CONTROL, tmp); 258 rdev->irq.hpd[4] = true; 259 break; 260 case RADEON_HPD_6: 261 WREG32(DC_HPD6_CONTROL, tmp); 262 rdev->irq.hpd[5] = true; 263 break; 264 default: 265 break; 266 } 267 } 268 } else { 269 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 270 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 271 switch (radeon_connector->hpd.hpd) { 272 case RADEON_HPD_1: 273 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 274 rdev->irq.hpd[0] = true; 275 break; 276 case RADEON_HPD_2: 277 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 278 rdev->irq.hpd[1] = true; 279 break; 280 case RADEON_HPD_3: 281 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 282 rdev->irq.hpd[2] = true; 283 break; 284 default: 285 break; 286 } 287 } 288 } 289 if (rdev->irq.installed) 290 r600_irq_set(rdev); 291 } 292 293 void r600_hpd_fini(struct radeon_device *rdev) 294 { 295 struct drm_device *dev = rdev->ddev; 296 struct drm_connector *connector; 297 298 if (ASIC_IS_DCE3(rdev)) { 299 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 300 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 301 switch (radeon_connector->hpd.hpd) { 302 case RADEON_HPD_1: 303 WREG32(DC_HPD1_CONTROL, 0); 304 rdev->irq.hpd[0] = false; 305 break; 306 case RADEON_HPD_2: 307 WREG32(DC_HPD2_CONTROL, 0); 308 rdev->irq.hpd[1] = false; 309 break; 310 case RADEON_HPD_3: 311 WREG32(DC_HPD3_CONTROL, 0); 312 rdev->irq.hpd[2] = false; 313 break; 314 case RADEON_HPD_4: 315 WREG32(DC_HPD4_CONTROL, 0); 316 rdev->irq.hpd[3] = false; 317 break; 318 /* DCE 3.2 */ 319 case RADEON_HPD_5: 320 WREG32(DC_HPD5_CONTROL, 0); 321 rdev->irq.hpd[4] = false; 322 break; 323 case RADEON_HPD_6: 324 WREG32(DC_HPD6_CONTROL, 0); 325 rdev->irq.hpd[5] = false; 326 break; 327 default: 328 break; 329 } 330 } 331 } else { 332 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 333 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 334 switch (radeon_connector->hpd.hpd) { 335 case RADEON_HPD_1: 336 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 337 rdev->irq.hpd[0] = false; 338 break; 339 case RADEON_HPD_2: 340 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 341 rdev->irq.hpd[1] = false; 342 break; 343 case RADEON_HPD_3: 344 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 345 rdev->irq.hpd[2] = false; 346 break; 347 default: 348 break; 349 } 350 } 351 } 352 } 353 354 /* 355 * R600 PCIE GART 356 */ 357 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 358 { 359 unsigned i; 360 u32 tmp; 361 362 /* flush hdp cache so updates hit vram */ 363 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 364 365 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 366 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 367 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 368 for (i = 0; i < rdev->usec_timeout; i++) { 369 /* read MC_STATUS */ 370 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 371 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 372 if (tmp == 2) { 373 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 374 return; 375 } 376 if (tmp) { 377 return; 378 } 379 udelay(1); 380 } 381 } 382 383 int r600_pcie_gart_init(struct radeon_device *rdev) 384 { 385 int r; 386 387 if (rdev->gart.table.vram.robj) { 388 WARN(1, "R600 PCIE GART already initialized.\n"); 389 return 0; 390 } 391 /* Initialize common gart structure */ 392 r = radeon_gart_init(rdev); 393 if (r) 394 return r; 395 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 396 return radeon_gart_table_vram_alloc(rdev); 397 } 398 399 int r600_pcie_gart_enable(struct radeon_device *rdev) 400 { 401 u32 tmp; 402 int r, i; 403 404 if (rdev->gart.table.vram.robj == NULL) { 405 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 406 return -EINVAL; 407 } 408 r = radeon_gart_table_vram_pin(rdev); 409 if (r) 410 return r; 411 radeon_gart_restore(rdev); 412 413 /* Setup L2 cache */ 414 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 415 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 416 EFFECTIVE_L2_QUEUE_SIZE(7)); 417 WREG32(VM_L2_CNTL2, 0); 418 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 419 /* Setup TLB control */ 420 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 421 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 422 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 423 ENABLE_WAIT_L2_QUERY; 424 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 425 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 426 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 427 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 428 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 429 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 430 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 431 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 432 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 433 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 434 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 435 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 436 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 437 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 438 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 439 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 440 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 441 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 442 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 443 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 444 (u32)(rdev->dummy_page.addr >> 12)); 445 for (i = 1; i < 7; i++) 446 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 447 448 r600_pcie_gart_tlb_flush(rdev); 449 rdev->gart.ready = true; 450 return 0; 451 } 452 453 void r600_pcie_gart_disable(struct radeon_device *rdev) 454 { 455 u32 tmp; 456 int i, r; 457 458 /* Disable all tables */ 459 for (i = 0; i < 7; i++) 460 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 461 462 /* Disable L2 cache */ 463 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 464 EFFECTIVE_L2_QUEUE_SIZE(7)); 465 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 466 /* Setup L1 TLB control */ 467 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 468 ENABLE_WAIT_L2_QUERY; 469 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 470 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 471 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 472 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 473 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 474 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 475 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 476 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 477 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 478 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 479 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 480 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 481 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 482 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 483 if (rdev->gart.table.vram.robj) { 484 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 485 if (likely(r == 0)) { 486 radeon_bo_kunmap(rdev->gart.table.vram.robj); 487 radeon_bo_unpin(rdev->gart.table.vram.robj); 488 radeon_bo_unreserve(rdev->gart.table.vram.robj); 489 } 490 } 491 } 492 493 void r600_pcie_gart_fini(struct radeon_device *rdev) 494 { 495 radeon_gart_fini(rdev); 496 r600_pcie_gart_disable(rdev); 497 radeon_gart_table_vram_free(rdev); 498 } 499 500 void r600_agp_enable(struct radeon_device *rdev) 501 { 502 u32 tmp; 503 int i; 504 505 /* Setup L2 cache */ 506 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 507 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 508 EFFECTIVE_L2_QUEUE_SIZE(7)); 509 WREG32(VM_L2_CNTL2, 0); 510 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 511 /* Setup TLB control */ 512 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 513 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 514 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 515 ENABLE_WAIT_L2_QUERY; 516 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 517 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 518 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 519 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 520 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 521 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 522 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 523 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 524 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 525 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 526 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 527 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 528 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 529 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 530 for (i = 0; i < 7; i++) 531 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 532 } 533 534 int r600_mc_wait_for_idle(struct radeon_device *rdev) 535 { 536 unsigned i; 537 u32 tmp; 538 539 for (i = 0; i < rdev->usec_timeout; i++) { 540 /* read MC_STATUS */ 541 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 542 if (!tmp) 543 return 0; 544 udelay(1); 545 } 546 return -1; 547 } 548 549 static void r600_mc_program(struct radeon_device *rdev) 550 { 551 struct rv515_mc_save save; 552 u32 tmp; 553 int i, j; 554 555 /* Initialize HDP */ 556 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 557 WREG32((0x2c14 + j), 0x00000000); 558 WREG32((0x2c18 + j), 0x00000000); 559 WREG32((0x2c1c + j), 0x00000000); 560 WREG32((0x2c20 + j), 0x00000000); 561 WREG32((0x2c24 + j), 0x00000000); 562 } 563 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 564 565 rv515_mc_stop(rdev, &save); 566 if (r600_mc_wait_for_idle(rdev)) { 567 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 568 } 569 /* Lockout access through VGA aperture (doesn't exist before R600) */ 570 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 571 /* Update configuration */ 572 if (rdev->flags & RADEON_IS_AGP) { 573 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 574 /* VRAM before AGP */ 575 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 576 rdev->mc.vram_start >> 12); 577 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 578 rdev->mc.gtt_end >> 12); 579 } else { 580 /* VRAM after AGP */ 581 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 582 rdev->mc.gtt_start >> 12); 583 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 584 rdev->mc.vram_end >> 12); 585 } 586 } else { 587 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 588 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 589 } 590 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 591 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 592 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 593 WREG32(MC_VM_FB_LOCATION, tmp); 594 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 595 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 596 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF); 597 if (rdev->flags & RADEON_IS_AGP) { 598 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 599 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 600 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 601 } else { 602 WREG32(MC_VM_AGP_BASE, 0); 603 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 604 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 605 } 606 if (r600_mc_wait_for_idle(rdev)) { 607 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 608 } 609 rv515_mc_resume(rdev, &save); 610 /* we need to own VRAM, so turn off the VGA renderer here 611 * to stop it overwriting our objects */ 612 rv515_vga_render_disable(rdev); 613 } 614 615 /** 616 * r600_vram_gtt_location - try to find VRAM & GTT location 617 * @rdev: radeon device structure holding all necessary informations 618 * @mc: memory controller structure holding memory informations 619 * 620 * Function will place try to place VRAM at same place as in CPU (PCI) 621 * address space as some GPU seems to have issue when we reprogram at 622 * different address space. 623 * 624 * If there is not enough space to fit the unvisible VRAM after the 625 * aperture then we limit the VRAM size to the aperture. 626 * 627 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 628 * them to be in one from GPU point of view so that we can program GPU to 629 * catch access outside them (weird GPU policy see ??). 630 * 631 * This function will never fails, worst case are limiting VRAM or GTT. 632 * 633 * Note: GTT start, end, size should be initialized before calling this 634 * function on AGP platform. 635 */ 636 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 637 { 638 u64 size_bf, size_af; 639 640 if (mc->mc_vram_size > 0xE0000000) { 641 /* leave room for at least 512M GTT */ 642 dev_warn(rdev->dev, "limiting VRAM\n"); 643 mc->real_vram_size = 0xE0000000; 644 mc->mc_vram_size = 0xE0000000; 645 } 646 if (rdev->flags & RADEON_IS_AGP) { 647 size_bf = mc->gtt_start; 648 size_af = 0xFFFFFFFF - mc->gtt_end + 1; 649 if (size_bf > size_af) { 650 if (mc->mc_vram_size > size_bf) { 651 dev_warn(rdev->dev, "limiting VRAM\n"); 652 mc->real_vram_size = size_bf; 653 mc->mc_vram_size = size_bf; 654 } 655 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 656 } else { 657 if (mc->mc_vram_size > size_af) { 658 dev_warn(rdev->dev, "limiting VRAM\n"); 659 mc->real_vram_size = size_af; 660 mc->mc_vram_size = size_af; 661 } 662 mc->vram_start = mc->gtt_end; 663 } 664 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 665 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 666 mc->mc_vram_size >> 20, mc->vram_start, 667 mc->vram_end, mc->real_vram_size >> 20); 668 } else { 669 u64 base = 0; 670 if (rdev->flags & RADEON_IS_IGP) 671 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; 672 radeon_vram_location(rdev, &rdev->mc, base); 673 radeon_gtt_location(rdev, mc); 674 } 675 } 676 677 int r600_mc_init(struct radeon_device *rdev) 678 { 679 u32 tmp; 680 int chansize, numchan; 681 682 /* Get VRAM informations */ 683 rdev->mc.vram_is_ddr = true; 684 tmp = RREG32(RAMCFG); 685 if (tmp & CHANSIZE_OVERRIDE) { 686 chansize = 16; 687 } else if (tmp & CHANSIZE_MASK) { 688 chansize = 64; 689 } else { 690 chansize = 32; 691 } 692 tmp = RREG32(CHMAP); 693 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 694 case 0: 695 default: 696 numchan = 1; 697 break; 698 case 1: 699 numchan = 2; 700 break; 701 case 2: 702 numchan = 4; 703 break; 704 case 3: 705 numchan = 8; 706 break; 707 } 708 rdev->mc.vram_width = numchan * chansize; 709 /* Could aper size report 0 ? */ 710 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 711 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 712 /* Setup GPU memory space */ 713 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 714 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 715 rdev->mc.visible_vram_size = rdev->mc.aper_size; 716 /* FIXME remove this once we support unmappable VRAM */ 717 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { 718 rdev->mc.mc_vram_size = rdev->mc.aper_size; 719 rdev->mc.real_vram_size = rdev->mc.aper_size; 720 } 721 r600_vram_gtt_location(rdev, &rdev->mc); 722 723 if (rdev->flags & RADEON_IS_IGP) 724 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 725 radeon_update_bandwidth_info(rdev); 726 return 0; 727 } 728 729 /* We doesn't check that the GPU really needs a reset we simply do the 730 * reset, it's up to the caller to determine if the GPU needs one. We 731 * might add an helper function to check that. 732 */ 733 int r600_gpu_soft_reset(struct radeon_device *rdev) 734 { 735 struct rv515_mc_save save; 736 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | 737 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | 738 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | 739 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | 740 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | 741 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | 742 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | 743 S_008010_GUI_ACTIVE(1); 744 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | 745 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | 746 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | 747 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | 748 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | 749 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | 750 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | 751 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); 752 u32 tmp; 753 754 dev_info(rdev->dev, "GPU softreset \n"); 755 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", 756 RREG32(R_008010_GRBM_STATUS)); 757 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", 758 RREG32(R_008014_GRBM_STATUS2)); 759 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", 760 RREG32(R_000E50_SRBM_STATUS)); 761 rv515_mc_stop(rdev, &save); 762 if (r600_mc_wait_for_idle(rdev)) { 763 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 764 } 765 /* Disable CP parsing/prefetching */ 766 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 767 /* Check if any of the rendering block is busy and reset it */ 768 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || 769 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { 770 tmp = S_008020_SOFT_RESET_CR(1) | 771 S_008020_SOFT_RESET_DB(1) | 772 S_008020_SOFT_RESET_CB(1) | 773 S_008020_SOFT_RESET_PA(1) | 774 S_008020_SOFT_RESET_SC(1) | 775 S_008020_SOFT_RESET_SMX(1) | 776 S_008020_SOFT_RESET_SPI(1) | 777 S_008020_SOFT_RESET_SX(1) | 778 S_008020_SOFT_RESET_SH(1) | 779 S_008020_SOFT_RESET_TC(1) | 780 S_008020_SOFT_RESET_TA(1) | 781 S_008020_SOFT_RESET_VC(1) | 782 S_008020_SOFT_RESET_VGT(1); 783 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 784 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 785 RREG32(R_008020_GRBM_SOFT_RESET); 786 mdelay(15); 787 WREG32(R_008020_GRBM_SOFT_RESET, 0); 788 } 789 /* Reset CP (we always reset CP) */ 790 tmp = S_008020_SOFT_RESET_CP(1); 791 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 792 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 793 RREG32(R_008020_GRBM_SOFT_RESET); 794 mdelay(15); 795 WREG32(R_008020_GRBM_SOFT_RESET, 0); 796 /* Wait a little for things to settle down */ 797 mdelay(1); 798 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", 799 RREG32(R_008010_GRBM_STATUS)); 800 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", 801 RREG32(R_008014_GRBM_STATUS2)); 802 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", 803 RREG32(R_000E50_SRBM_STATUS)); 804 rv515_mc_resume(rdev, &save); 805 return 0; 806 } 807 808 bool r600_gpu_is_lockup(struct radeon_device *rdev) 809 { 810 u32 srbm_status; 811 u32 grbm_status; 812 u32 grbm_status2; 813 int r; 814 815 srbm_status = RREG32(R_000E50_SRBM_STATUS); 816 grbm_status = RREG32(R_008010_GRBM_STATUS); 817 grbm_status2 = RREG32(R_008014_GRBM_STATUS2); 818 if (!G_008010_GUI_ACTIVE(grbm_status)) { 819 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); 820 return false; 821 } 822 /* force CP activities */ 823 r = radeon_ring_lock(rdev, 2); 824 if (!r) { 825 /* PACKET2 NOP */ 826 radeon_ring_write(rdev, 0x80000000); 827 radeon_ring_write(rdev, 0x80000000); 828 radeon_ring_unlock_commit(rdev); 829 } 830 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); 831 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); 832 } 833 834 int r600_asic_reset(struct radeon_device *rdev) 835 { 836 return r600_gpu_soft_reset(rdev); 837 } 838 839 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 840 u32 num_backends, 841 u32 backend_disable_mask) 842 { 843 u32 backend_map = 0; 844 u32 enabled_backends_mask; 845 u32 enabled_backends_count; 846 u32 cur_pipe; 847 u32 swizzle_pipe[R6XX_MAX_PIPES]; 848 u32 cur_backend; 849 u32 i; 850 851 if (num_tile_pipes > R6XX_MAX_PIPES) 852 num_tile_pipes = R6XX_MAX_PIPES; 853 if (num_tile_pipes < 1) 854 num_tile_pipes = 1; 855 if (num_backends > R6XX_MAX_BACKENDS) 856 num_backends = R6XX_MAX_BACKENDS; 857 if (num_backends < 1) 858 num_backends = 1; 859 860 enabled_backends_mask = 0; 861 enabled_backends_count = 0; 862 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 863 if (((backend_disable_mask >> i) & 1) == 0) { 864 enabled_backends_mask |= (1 << i); 865 ++enabled_backends_count; 866 } 867 if (enabled_backends_count == num_backends) 868 break; 869 } 870 871 if (enabled_backends_count == 0) { 872 enabled_backends_mask = 1; 873 enabled_backends_count = 1; 874 } 875 876 if (enabled_backends_count != num_backends) 877 num_backends = enabled_backends_count; 878 879 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 880 switch (num_tile_pipes) { 881 case 1: 882 swizzle_pipe[0] = 0; 883 break; 884 case 2: 885 swizzle_pipe[0] = 0; 886 swizzle_pipe[1] = 1; 887 break; 888 case 3: 889 swizzle_pipe[0] = 0; 890 swizzle_pipe[1] = 1; 891 swizzle_pipe[2] = 2; 892 break; 893 case 4: 894 swizzle_pipe[0] = 0; 895 swizzle_pipe[1] = 1; 896 swizzle_pipe[2] = 2; 897 swizzle_pipe[3] = 3; 898 break; 899 case 5: 900 swizzle_pipe[0] = 0; 901 swizzle_pipe[1] = 1; 902 swizzle_pipe[2] = 2; 903 swizzle_pipe[3] = 3; 904 swizzle_pipe[4] = 4; 905 break; 906 case 6: 907 swizzle_pipe[0] = 0; 908 swizzle_pipe[1] = 2; 909 swizzle_pipe[2] = 4; 910 swizzle_pipe[3] = 5; 911 swizzle_pipe[4] = 1; 912 swizzle_pipe[5] = 3; 913 break; 914 case 7: 915 swizzle_pipe[0] = 0; 916 swizzle_pipe[1] = 2; 917 swizzle_pipe[2] = 4; 918 swizzle_pipe[3] = 6; 919 swizzle_pipe[4] = 1; 920 swizzle_pipe[5] = 3; 921 swizzle_pipe[6] = 5; 922 break; 923 case 8: 924 swizzle_pipe[0] = 0; 925 swizzle_pipe[1] = 2; 926 swizzle_pipe[2] = 4; 927 swizzle_pipe[3] = 6; 928 swizzle_pipe[4] = 1; 929 swizzle_pipe[5] = 3; 930 swizzle_pipe[6] = 5; 931 swizzle_pipe[7] = 7; 932 break; 933 } 934 935 cur_backend = 0; 936 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 937 while (((1 << cur_backend) & enabled_backends_mask) == 0) 938 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 939 940 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 941 942 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 943 } 944 945 return backend_map; 946 } 947 948 int r600_count_pipe_bits(uint32_t val) 949 { 950 int i, ret = 0; 951 952 for (i = 0; i < 32; i++) { 953 ret += val & 1; 954 val >>= 1; 955 } 956 return ret; 957 } 958 959 void r600_gpu_init(struct radeon_device *rdev) 960 { 961 u32 tiling_config; 962 u32 ramcfg; 963 u32 backend_map; 964 u32 cc_rb_backend_disable; 965 u32 cc_gc_shader_pipe_config; 966 u32 tmp; 967 int i, j; 968 u32 sq_config; 969 u32 sq_gpr_resource_mgmt_1 = 0; 970 u32 sq_gpr_resource_mgmt_2 = 0; 971 u32 sq_thread_resource_mgmt = 0; 972 u32 sq_stack_resource_mgmt_1 = 0; 973 u32 sq_stack_resource_mgmt_2 = 0; 974 975 /* FIXME: implement */ 976 switch (rdev->family) { 977 case CHIP_R600: 978 rdev->config.r600.max_pipes = 4; 979 rdev->config.r600.max_tile_pipes = 8; 980 rdev->config.r600.max_simds = 4; 981 rdev->config.r600.max_backends = 4; 982 rdev->config.r600.max_gprs = 256; 983 rdev->config.r600.max_threads = 192; 984 rdev->config.r600.max_stack_entries = 256; 985 rdev->config.r600.max_hw_contexts = 8; 986 rdev->config.r600.max_gs_threads = 16; 987 rdev->config.r600.sx_max_export_size = 128; 988 rdev->config.r600.sx_max_export_pos_size = 16; 989 rdev->config.r600.sx_max_export_smx_size = 128; 990 rdev->config.r600.sq_num_cf_insts = 2; 991 break; 992 case CHIP_RV630: 993 case CHIP_RV635: 994 rdev->config.r600.max_pipes = 2; 995 rdev->config.r600.max_tile_pipes = 2; 996 rdev->config.r600.max_simds = 3; 997 rdev->config.r600.max_backends = 1; 998 rdev->config.r600.max_gprs = 128; 999 rdev->config.r600.max_threads = 192; 1000 rdev->config.r600.max_stack_entries = 128; 1001 rdev->config.r600.max_hw_contexts = 8; 1002 rdev->config.r600.max_gs_threads = 4; 1003 rdev->config.r600.sx_max_export_size = 128; 1004 rdev->config.r600.sx_max_export_pos_size = 16; 1005 rdev->config.r600.sx_max_export_smx_size = 128; 1006 rdev->config.r600.sq_num_cf_insts = 2; 1007 break; 1008 case CHIP_RV610: 1009 case CHIP_RV620: 1010 case CHIP_RS780: 1011 case CHIP_RS880: 1012 rdev->config.r600.max_pipes = 1; 1013 rdev->config.r600.max_tile_pipes = 1; 1014 rdev->config.r600.max_simds = 2; 1015 rdev->config.r600.max_backends = 1; 1016 rdev->config.r600.max_gprs = 128; 1017 rdev->config.r600.max_threads = 192; 1018 rdev->config.r600.max_stack_entries = 128; 1019 rdev->config.r600.max_hw_contexts = 4; 1020 rdev->config.r600.max_gs_threads = 4; 1021 rdev->config.r600.sx_max_export_size = 128; 1022 rdev->config.r600.sx_max_export_pos_size = 16; 1023 rdev->config.r600.sx_max_export_smx_size = 128; 1024 rdev->config.r600.sq_num_cf_insts = 1; 1025 break; 1026 case CHIP_RV670: 1027 rdev->config.r600.max_pipes = 4; 1028 rdev->config.r600.max_tile_pipes = 4; 1029 rdev->config.r600.max_simds = 4; 1030 rdev->config.r600.max_backends = 4; 1031 rdev->config.r600.max_gprs = 192; 1032 rdev->config.r600.max_threads = 192; 1033 rdev->config.r600.max_stack_entries = 256; 1034 rdev->config.r600.max_hw_contexts = 8; 1035 rdev->config.r600.max_gs_threads = 16; 1036 rdev->config.r600.sx_max_export_size = 128; 1037 rdev->config.r600.sx_max_export_pos_size = 16; 1038 rdev->config.r600.sx_max_export_smx_size = 128; 1039 rdev->config.r600.sq_num_cf_insts = 2; 1040 break; 1041 default: 1042 break; 1043 } 1044 1045 /* Initialize HDP */ 1046 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1047 WREG32((0x2c14 + j), 0x00000000); 1048 WREG32((0x2c18 + j), 0x00000000); 1049 WREG32((0x2c1c + j), 0x00000000); 1050 WREG32((0x2c20 + j), 0x00000000); 1051 WREG32((0x2c24 + j), 0x00000000); 1052 } 1053 1054 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1055 1056 /* Setup tiling */ 1057 tiling_config = 0; 1058 ramcfg = RREG32(RAMCFG); 1059 switch (rdev->config.r600.max_tile_pipes) { 1060 case 1: 1061 tiling_config |= PIPE_TILING(0); 1062 break; 1063 case 2: 1064 tiling_config |= PIPE_TILING(1); 1065 break; 1066 case 4: 1067 tiling_config |= PIPE_TILING(2); 1068 break; 1069 case 8: 1070 tiling_config |= PIPE_TILING(3); 1071 break; 1072 default: 1073 break; 1074 } 1075 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1076 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1077 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1078 tiling_config |= GROUP_SIZE(0); 1079 rdev->config.r600.tiling_group_size = 256; 1080 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1081 if (tmp > 3) { 1082 tiling_config |= ROW_TILING(3); 1083 tiling_config |= SAMPLE_SPLIT(3); 1084 } else { 1085 tiling_config |= ROW_TILING(tmp); 1086 tiling_config |= SAMPLE_SPLIT(tmp); 1087 } 1088 tiling_config |= BANK_SWAPS(1); 1089 1090 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1091 cc_rb_backend_disable |= 1092 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); 1093 1094 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1095 cc_gc_shader_pipe_config |= 1096 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); 1097 cc_gc_shader_pipe_config |= 1098 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); 1099 1100 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, 1101 (R6XX_MAX_BACKENDS - 1102 r600_count_pipe_bits((cc_rb_backend_disable & 1103 R6XX_MAX_BACKENDS_MASK) >> 16)), 1104 (cc_rb_backend_disable >> 16)); 1105 1106 tiling_config |= BACKEND_MAP(backend_map); 1107 WREG32(GB_TILING_CONFIG, tiling_config); 1108 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1109 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1110 1111 /* Setup pipes */ 1112 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1113 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1114 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1115 1116 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1117 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1118 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1119 1120 /* Setup some CP states */ 1121 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1122 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1123 1124 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1125 SYNC_WALKER | SYNC_ALIGNER)); 1126 /* Setup various GPU states */ 1127 if (rdev->family == CHIP_RV670) 1128 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1129 1130 tmp = RREG32(SX_DEBUG_1); 1131 tmp |= SMX_EVENT_RELEASE; 1132 if ((rdev->family > CHIP_R600)) 1133 tmp |= ENABLE_NEW_SMX_ADDRESS; 1134 WREG32(SX_DEBUG_1, tmp); 1135 1136 if (((rdev->family) == CHIP_R600) || 1137 ((rdev->family) == CHIP_RV630) || 1138 ((rdev->family) == CHIP_RV610) || 1139 ((rdev->family) == CHIP_RV620) || 1140 ((rdev->family) == CHIP_RS780) || 1141 ((rdev->family) == CHIP_RS880)) { 1142 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1143 } else { 1144 WREG32(DB_DEBUG, 0); 1145 } 1146 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1147 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1148 1149 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1150 WREG32(VGT_NUM_INSTANCES, 0); 1151 1152 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1153 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1154 1155 tmp = RREG32(SQ_MS_FIFO_SIZES); 1156 if (((rdev->family) == CHIP_RV610) || 1157 ((rdev->family) == CHIP_RV620) || 1158 ((rdev->family) == CHIP_RS780) || 1159 ((rdev->family) == CHIP_RS880)) { 1160 tmp = (CACHE_FIFO_SIZE(0xa) | 1161 FETCH_FIFO_HIWATER(0xa) | 1162 DONE_FIFO_HIWATER(0xe0) | 1163 ALU_UPDATE_FIFO_HIWATER(0x8)); 1164 } else if (((rdev->family) == CHIP_R600) || 1165 ((rdev->family) == CHIP_RV630)) { 1166 tmp &= ~DONE_FIFO_HIWATER(0xff); 1167 tmp |= DONE_FIFO_HIWATER(0x4); 1168 } 1169 WREG32(SQ_MS_FIFO_SIZES, tmp); 1170 1171 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1172 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1173 */ 1174 sq_config = RREG32(SQ_CONFIG); 1175 sq_config &= ~(PS_PRIO(3) | 1176 VS_PRIO(3) | 1177 GS_PRIO(3) | 1178 ES_PRIO(3)); 1179 sq_config |= (DX9_CONSTS | 1180 VC_ENABLE | 1181 PS_PRIO(0) | 1182 VS_PRIO(1) | 1183 GS_PRIO(2) | 1184 ES_PRIO(3)); 1185 1186 if ((rdev->family) == CHIP_R600) { 1187 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1188 NUM_VS_GPRS(124) | 1189 NUM_CLAUSE_TEMP_GPRS(4)); 1190 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1191 NUM_ES_GPRS(0)); 1192 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1193 NUM_VS_THREADS(48) | 1194 NUM_GS_THREADS(4) | 1195 NUM_ES_THREADS(4)); 1196 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1197 NUM_VS_STACK_ENTRIES(128)); 1198 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1199 NUM_ES_STACK_ENTRIES(0)); 1200 } else if (((rdev->family) == CHIP_RV610) || 1201 ((rdev->family) == CHIP_RV620) || 1202 ((rdev->family) == CHIP_RS780) || 1203 ((rdev->family) == CHIP_RS880)) { 1204 /* no vertex cache */ 1205 sq_config &= ~VC_ENABLE; 1206 1207 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1208 NUM_VS_GPRS(44) | 1209 NUM_CLAUSE_TEMP_GPRS(2)); 1210 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1211 NUM_ES_GPRS(17)); 1212 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1213 NUM_VS_THREADS(78) | 1214 NUM_GS_THREADS(4) | 1215 NUM_ES_THREADS(31)); 1216 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1217 NUM_VS_STACK_ENTRIES(40)); 1218 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1219 NUM_ES_STACK_ENTRIES(16)); 1220 } else if (((rdev->family) == CHIP_RV630) || 1221 ((rdev->family) == CHIP_RV635)) { 1222 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1223 NUM_VS_GPRS(44) | 1224 NUM_CLAUSE_TEMP_GPRS(2)); 1225 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1226 NUM_ES_GPRS(18)); 1227 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1228 NUM_VS_THREADS(78) | 1229 NUM_GS_THREADS(4) | 1230 NUM_ES_THREADS(31)); 1231 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1232 NUM_VS_STACK_ENTRIES(40)); 1233 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1234 NUM_ES_STACK_ENTRIES(16)); 1235 } else if ((rdev->family) == CHIP_RV670) { 1236 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1237 NUM_VS_GPRS(44) | 1238 NUM_CLAUSE_TEMP_GPRS(2)); 1239 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1240 NUM_ES_GPRS(17)); 1241 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1242 NUM_VS_THREADS(78) | 1243 NUM_GS_THREADS(4) | 1244 NUM_ES_THREADS(31)); 1245 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 1246 NUM_VS_STACK_ENTRIES(64)); 1247 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 1248 NUM_ES_STACK_ENTRIES(64)); 1249 } 1250 1251 WREG32(SQ_CONFIG, sq_config); 1252 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1253 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1254 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1255 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1256 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1257 1258 if (((rdev->family) == CHIP_RV610) || 1259 ((rdev->family) == CHIP_RV620) || 1260 ((rdev->family) == CHIP_RS780) || 1261 ((rdev->family) == CHIP_RS880)) { 1262 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 1263 } else { 1264 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 1265 } 1266 1267 /* More default values. 2D/3D driver should adjust as needed */ 1268 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 1269 S1_X(0x4) | S1_Y(0xc))); 1270 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 1271 S1_X(0x2) | S1_Y(0x2) | 1272 S2_X(0xa) | S2_Y(0x6) | 1273 S3_X(0x6) | S3_Y(0xa))); 1274 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 1275 S1_X(0x4) | S1_Y(0xc) | 1276 S2_X(0x1) | S2_Y(0x6) | 1277 S3_X(0xa) | S3_Y(0xe))); 1278 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 1279 S5_X(0x0) | S5_Y(0x0) | 1280 S6_X(0xb) | S6_Y(0x4) | 1281 S7_X(0x7) | S7_Y(0x8))); 1282 1283 WREG32(VGT_STRMOUT_EN, 0); 1284 tmp = rdev->config.r600.max_pipes * 16; 1285 switch (rdev->family) { 1286 case CHIP_RV610: 1287 case CHIP_RV620: 1288 case CHIP_RS780: 1289 case CHIP_RS880: 1290 tmp += 32; 1291 break; 1292 case CHIP_RV670: 1293 tmp += 128; 1294 break; 1295 default: 1296 break; 1297 } 1298 if (tmp > 256) { 1299 tmp = 256; 1300 } 1301 WREG32(VGT_ES_PER_GS, 128); 1302 WREG32(VGT_GS_PER_ES, tmp); 1303 WREG32(VGT_GS_PER_VS, 2); 1304 WREG32(VGT_GS_VERTEX_REUSE, 16); 1305 1306 /* more default values. 2D/3D driver should adjust as needed */ 1307 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1308 WREG32(VGT_STRMOUT_EN, 0); 1309 WREG32(SX_MISC, 0); 1310 WREG32(PA_SC_MODE_CNTL, 0); 1311 WREG32(PA_SC_AA_CONFIG, 0); 1312 WREG32(PA_SC_LINE_STIPPLE, 0); 1313 WREG32(SPI_INPUT_Z, 0); 1314 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1315 WREG32(CB_COLOR7_FRAG, 0); 1316 1317 /* Clear render buffer base addresses */ 1318 WREG32(CB_COLOR0_BASE, 0); 1319 WREG32(CB_COLOR1_BASE, 0); 1320 WREG32(CB_COLOR2_BASE, 0); 1321 WREG32(CB_COLOR3_BASE, 0); 1322 WREG32(CB_COLOR4_BASE, 0); 1323 WREG32(CB_COLOR5_BASE, 0); 1324 WREG32(CB_COLOR6_BASE, 0); 1325 WREG32(CB_COLOR7_BASE, 0); 1326 WREG32(CB_COLOR7_FRAG, 0); 1327 1328 switch (rdev->family) { 1329 case CHIP_RV610: 1330 case CHIP_RV620: 1331 case CHIP_RS780: 1332 case CHIP_RS880: 1333 tmp = TC_L2_SIZE(8); 1334 break; 1335 case CHIP_RV630: 1336 case CHIP_RV635: 1337 tmp = TC_L2_SIZE(4); 1338 break; 1339 case CHIP_R600: 1340 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 1341 break; 1342 default: 1343 tmp = TC_L2_SIZE(0); 1344 break; 1345 } 1346 WREG32(TC_CNTL, tmp); 1347 1348 tmp = RREG32(HDP_HOST_PATH_CNTL); 1349 WREG32(HDP_HOST_PATH_CNTL, tmp); 1350 1351 tmp = RREG32(ARB_POP); 1352 tmp |= ENABLE_TC128; 1353 WREG32(ARB_POP, tmp); 1354 1355 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1356 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1357 NUM_CLIP_SEQ(3))); 1358 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 1359 } 1360 1361 1362 /* 1363 * Indirect registers accessor 1364 */ 1365 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 1366 { 1367 u32 r; 1368 1369 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1370 (void)RREG32(PCIE_PORT_INDEX); 1371 r = RREG32(PCIE_PORT_DATA); 1372 return r; 1373 } 1374 1375 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 1376 { 1377 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1378 (void)RREG32(PCIE_PORT_INDEX); 1379 WREG32(PCIE_PORT_DATA, (v)); 1380 (void)RREG32(PCIE_PORT_DATA); 1381 } 1382 1383 /* 1384 * CP & Ring 1385 */ 1386 void r600_cp_stop(struct radeon_device *rdev) 1387 { 1388 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1389 } 1390 1391 int r600_init_microcode(struct radeon_device *rdev) 1392 { 1393 struct platform_device *pdev; 1394 const char *chip_name; 1395 const char *rlc_chip_name; 1396 size_t pfp_req_size, me_req_size, rlc_req_size; 1397 char fw_name[30]; 1398 int err; 1399 1400 DRM_DEBUG("\n"); 1401 1402 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 1403 err = IS_ERR(pdev); 1404 if (err) { 1405 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 1406 return -EINVAL; 1407 } 1408 1409 switch (rdev->family) { 1410 case CHIP_R600: 1411 chip_name = "R600"; 1412 rlc_chip_name = "R600"; 1413 break; 1414 case CHIP_RV610: 1415 chip_name = "RV610"; 1416 rlc_chip_name = "R600"; 1417 break; 1418 case CHIP_RV630: 1419 chip_name = "RV630"; 1420 rlc_chip_name = "R600"; 1421 break; 1422 case CHIP_RV620: 1423 chip_name = "RV620"; 1424 rlc_chip_name = "R600"; 1425 break; 1426 case CHIP_RV635: 1427 chip_name = "RV635"; 1428 rlc_chip_name = "R600"; 1429 break; 1430 case CHIP_RV670: 1431 chip_name = "RV670"; 1432 rlc_chip_name = "R600"; 1433 break; 1434 case CHIP_RS780: 1435 case CHIP_RS880: 1436 chip_name = "RS780"; 1437 rlc_chip_name = "R600"; 1438 break; 1439 case CHIP_RV770: 1440 chip_name = "RV770"; 1441 rlc_chip_name = "R700"; 1442 break; 1443 case CHIP_RV730: 1444 case CHIP_RV740: 1445 chip_name = "RV730"; 1446 rlc_chip_name = "R700"; 1447 break; 1448 case CHIP_RV710: 1449 chip_name = "RV710"; 1450 rlc_chip_name = "R700"; 1451 break; 1452 default: BUG(); 1453 } 1454 1455 if (rdev->family >= CHIP_RV770) { 1456 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 1457 me_req_size = R700_PM4_UCODE_SIZE * 4; 1458 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 1459 } else { 1460 pfp_req_size = PFP_UCODE_SIZE * 4; 1461 me_req_size = PM4_UCODE_SIZE * 12; 1462 rlc_req_size = RLC_UCODE_SIZE * 4; 1463 } 1464 1465 DRM_INFO("Loading %s Microcode\n", chip_name); 1466 1467 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 1468 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); 1469 if (err) 1470 goto out; 1471 if (rdev->pfp_fw->size != pfp_req_size) { 1472 printk(KERN_ERR 1473 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 1474 rdev->pfp_fw->size, fw_name); 1475 err = -EINVAL; 1476 goto out; 1477 } 1478 1479 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 1480 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 1481 if (err) 1482 goto out; 1483 if (rdev->me_fw->size != me_req_size) { 1484 printk(KERN_ERR 1485 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 1486 rdev->me_fw->size, fw_name); 1487 err = -EINVAL; 1488 } 1489 1490 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); 1491 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); 1492 if (err) 1493 goto out; 1494 if (rdev->rlc_fw->size != rlc_req_size) { 1495 printk(KERN_ERR 1496 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 1497 rdev->rlc_fw->size, fw_name); 1498 err = -EINVAL; 1499 } 1500 1501 out: 1502 platform_device_unregister(pdev); 1503 1504 if (err) { 1505 if (err != -EINVAL) 1506 printk(KERN_ERR 1507 "r600_cp: Failed to load firmware \"%s\"\n", 1508 fw_name); 1509 release_firmware(rdev->pfp_fw); 1510 rdev->pfp_fw = NULL; 1511 release_firmware(rdev->me_fw); 1512 rdev->me_fw = NULL; 1513 release_firmware(rdev->rlc_fw); 1514 rdev->rlc_fw = NULL; 1515 } 1516 return err; 1517 } 1518 1519 static int r600_cp_load_microcode(struct radeon_device *rdev) 1520 { 1521 const __be32 *fw_data; 1522 int i; 1523 1524 if (!rdev->me_fw || !rdev->pfp_fw) 1525 return -EINVAL; 1526 1527 r600_cp_stop(rdev); 1528 1529 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1530 1531 /* Reset cp */ 1532 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 1533 RREG32(GRBM_SOFT_RESET); 1534 mdelay(15); 1535 WREG32(GRBM_SOFT_RESET, 0); 1536 1537 WREG32(CP_ME_RAM_WADDR, 0); 1538 1539 fw_data = (const __be32 *)rdev->me_fw->data; 1540 WREG32(CP_ME_RAM_WADDR, 0); 1541 for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 1542 WREG32(CP_ME_RAM_DATA, 1543 be32_to_cpup(fw_data++)); 1544 1545 fw_data = (const __be32 *)rdev->pfp_fw->data; 1546 WREG32(CP_PFP_UCODE_ADDR, 0); 1547 for (i = 0; i < PFP_UCODE_SIZE; i++) 1548 WREG32(CP_PFP_UCODE_DATA, 1549 be32_to_cpup(fw_data++)); 1550 1551 WREG32(CP_PFP_UCODE_ADDR, 0); 1552 WREG32(CP_ME_RAM_WADDR, 0); 1553 WREG32(CP_ME_RAM_RADDR, 0); 1554 return 0; 1555 } 1556 1557 int r600_cp_start(struct radeon_device *rdev) 1558 { 1559 int r; 1560 uint32_t cp_me; 1561 1562 r = radeon_ring_lock(rdev, 7); 1563 if (r) { 1564 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1565 return r; 1566 } 1567 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1568 radeon_ring_write(rdev, 0x1); 1569 if (rdev->family < CHIP_RV770) { 1570 radeon_ring_write(rdev, 0x3); 1571 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); 1572 } else { 1573 radeon_ring_write(rdev, 0x0); 1574 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); 1575 } 1576 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1577 radeon_ring_write(rdev, 0); 1578 radeon_ring_write(rdev, 0); 1579 radeon_ring_unlock_commit(rdev); 1580 1581 cp_me = 0xff; 1582 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 1583 return 0; 1584 } 1585 1586 int r600_cp_resume(struct radeon_device *rdev) 1587 { 1588 u32 tmp; 1589 u32 rb_bufsz; 1590 int r; 1591 1592 /* Reset cp */ 1593 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 1594 RREG32(GRBM_SOFT_RESET); 1595 mdelay(15); 1596 WREG32(GRBM_SOFT_RESET, 0); 1597 1598 /* Set ring buffer size */ 1599 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 1600 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1601 #ifdef __BIG_ENDIAN 1602 tmp |= BUF_SWAP_32BIT; 1603 #endif 1604 WREG32(CP_RB_CNTL, tmp); 1605 WREG32(CP_SEM_WAIT_TIMER, 0x4); 1606 1607 /* Set the write pointer delay */ 1608 WREG32(CP_RB_WPTR_DELAY, 0); 1609 1610 /* Initialize the ring buffer's read and write pointers */ 1611 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 1612 WREG32(CP_RB_RPTR_WR, 0); 1613 WREG32(CP_RB_WPTR, 0); 1614 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); 1615 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); 1616 mdelay(1); 1617 WREG32(CP_RB_CNTL, tmp); 1618 1619 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); 1620 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 1621 1622 rdev->cp.rptr = RREG32(CP_RB_RPTR); 1623 rdev->cp.wptr = RREG32(CP_RB_WPTR); 1624 1625 r600_cp_start(rdev); 1626 rdev->cp.ready = true; 1627 r = radeon_ring_test(rdev); 1628 if (r) { 1629 rdev->cp.ready = false; 1630 return r; 1631 } 1632 return 0; 1633 } 1634 1635 void r600_cp_commit(struct radeon_device *rdev) 1636 { 1637 WREG32(CP_RB_WPTR, rdev->cp.wptr); 1638 (void)RREG32(CP_RB_WPTR); 1639 } 1640 1641 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) 1642 { 1643 u32 rb_bufsz; 1644 1645 /* Align ring size */ 1646 rb_bufsz = drm_order(ring_size / 8); 1647 ring_size = (1 << (rb_bufsz + 1)) * 4; 1648 rdev->cp.ring_size = ring_size; 1649 rdev->cp.align_mask = 16 - 1; 1650 } 1651 1652 void r600_cp_fini(struct radeon_device *rdev) 1653 { 1654 r600_cp_stop(rdev); 1655 radeon_ring_fini(rdev); 1656 } 1657 1658 1659 /* 1660 * GPU scratch registers helpers function. 1661 */ 1662 void r600_scratch_init(struct radeon_device *rdev) 1663 { 1664 int i; 1665 1666 rdev->scratch.num_reg = 7; 1667 for (i = 0; i < rdev->scratch.num_reg; i++) { 1668 rdev->scratch.free[i] = true; 1669 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); 1670 } 1671 } 1672 1673 int r600_ring_test(struct radeon_device *rdev) 1674 { 1675 uint32_t scratch; 1676 uint32_t tmp = 0; 1677 unsigned i; 1678 int r; 1679 1680 r = radeon_scratch_get(rdev, &scratch); 1681 if (r) { 1682 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 1683 return r; 1684 } 1685 WREG32(scratch, 0xCAFEDEAD); 1686 r = radeon_ring_lock(rdev, 3); 1687 if (r) { 1688 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1689 radeon_scratch_free(rdev, scratch); 1690 return r; 1691 } 1692 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1693 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 1694 radeon_ring_write(rdev, 0xDEADBEEF); 1695 radeon_ring_unlock_commit(rdev); 1696 for (i = 0; i < rdev->usec_timeout; i++) { 1697 tmp = RREG32(scratch); 1698 if (tmp == 0xDEADBEEF) 1699 break; 1700 DRM_UDELAY(1); 1701 } 1702 if (i < rdev->usec_timeout) { 1703 DRM_INFO("ring test succeeded in %d usecs\n", i); 1704 } else { 1705 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 1706 scratch, tmp); 1707 r = -EINVAL; 1708 } 1709 radeon_scratch_free(rdev, scratch); 1710 return r; 1711 } 1712 1713 void r600_wb_disable(struct radeon_device *rdev) 1714 { 1715 int r; 1716 1717 WREG32(SCRATCH_UMSK, 0); 1718 if (rdev->wb.wb_obj) { 1719 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 1720 if (unlikely(r != 0)) 1721 return; 1722 radeon_bo_kunmap(rdev->wb.wb_obj); 1723 radeon_bo_unpin(rdev->wb.wb_obj); 1724 radeon_bo_unreserve(rdev->wb.wb_obj); 1725 } 1726 } 1727 1728 void r600_wb_fini(struct radeon_device *rdev) 1729 { 1730 r600_wb_disable(rdev); 1731 if (rdev->wb.wb_obj) { 1732 radeon_bo_unref(&rdev->wb.wb_obj); 1733 rdev->wb.wb = NULL; 1734 rdev->wb.wb_obj = NULL; 1735 } 1736 } 1737 1738 int r600_wb_enable(struct radeon_device *rdev) 1739 { 1740 int r; 1741 1742 if (rdev->wb.wb_obj == NULL) { 1743 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, 1744 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); 1745 if (r) { 1746 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 1747 return r; 1748 } 1749 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 1750 if (unlikely(r != 0)) { 1751 r600_wb_fini(rdev); 1752 return r; 1753 } 1754 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 1755 &rdev->wb.gpu_addr); 1756 if (r) { 1757 radeon_bo_unreserve(rdev->wb.wb_obj); 1758 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 1759 r600_wb_fini(rdev); 1760 return r; 1761 } 1762 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 1763 radeon_bo_unreserve(rdev->wb.wb_obj); 1764 if (r) { 1765 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 1766 r600_wb_fini(rdev); 1767 return r; 1768 } 1769 } 1770 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF); 1771 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC); 1772 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF); 1773 WREG32(SCRATCH_UMSK, 0xff); 1774 return 0; 1775 } 1776 1777 void r600_fence_ring_emit(struct radeon_device *rdev, 1778 struct radeon_fence *fence) 1779 { 1780 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */ 1781 1782 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); 1783 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT); 1784 /* wait for 3D idle clean */ 1785 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1786 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 1787 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 1788 /* Emit fence sequence & fire IRQ */ 1789 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1790 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 1791 radeon_ring_write(rdev, fence->seq); 1792 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 1793 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); 1794 radeon_ring_write(rdev, RB_INT_STAT); 1795 } 1796 1797 int r600_copy_blit(struct radeon_device *rdev, 1798 uint64_t src_offset, uint64_t dst_offset, 1799 unsigned num_pages, struct radeon_fence *fence) 1800 { 1801 int r; 1802 1803 mutex_lock(&rdev->r600_blit.mutex); 1804 rdev->r600_blit.vb_ib = NULL; 1805 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); 1806 if (r) { 1807 if (rdev->r600_blit.vb_ib) 1808 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); 1809 mutex_unlock(&rdev->r600_blit.mutex); 1810 return r; 1811 } 1812 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); 1813 r600_blit_done_copy(rdev, fence); 1814 mutex_unlock(&rdev->r600_blit.mutex); 1815 return 0; 1816 } 1817 1818 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 1819 uint32_t tiling_flags, uint32_t pitch, 1820 uint32_t offset, uint32_t obj_size) 1821 { 1822 /* FIXME: implement */ 1823 return 0; 1824 } 1825 1826 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 1827 { 1828 /* FIXME: implement */ 1829 } 1830 1831 1832 bool r600_card_posted(struct radeon_device *rdev) 1833 { 1834 uint32_t reg; 1835 1836 /* first check CRTCs */ 1837 reg = RREG32(D1CRTC_CONTROL) | 1838 RREG32(D2CRTC_CONTROL); 1839 if (reg & CRTC_EN) 1840 return true; 1841 1842 /* then check MEM_SIZE, in case the crtcs are off */ 1843 if (RREG32(CONFIG_MEMSIZE)) 1844 return true; 1845 1846 return false; 1847 } 1848 1849 int r600_startup(struct radeon_device *rdev) 1850 { 1851 int r; 1852 1853 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1854 r = r600_init_microcode(rdev); 1855 if (r) { 1856 DRM_ERROR("Failed to load firmware!\n"); 1857 return r; 1858 } 1859 } 1860 1861 r600_mc_program(rdev); 1862 if (rdev->flags & RADEON_IS_AGP) { 1863 r600_agp_enable(rdev); 1864 } else { 1865 r = r600_pcie_gart_enable(rdev); 1866 if (r) 1867 return r; 1868 } 1869 r600_gpu_init(rdev); 1870 r = r600_blit_init(rdev); 1871 if (r) { 1872 r600_blit_fini(rdev); 1873 rdev->asic->copy = NULL; 1874 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 1875 } 1876 /* pin copy shader into vram */ 1877 if (rdev->r600_blit.shader_obj) { 1878 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1879 if (unlikely(r != 0)) 1880 return r; 1881 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, 1882 &rdev->r600_blit.shader_gpu_addr); 1883 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 1884 if (r) { 1885 dev_err(rdev->dev, "(%d) pin blit object failed\n", r); 1886 return r; 1887 } 1888 } 1889 /* Enable IRQ */ 1890 r = r600_irq_init(rdev); 1891 if (r) { 1892 DRM_ERROR("radeon: IH init failed (%d).\n", r); 1893 radeon_irq_kms_fini(rdev); 1894 return r; 1895 } 1896 r600_irq_set(rdev); 1897 1898 r = radeon_ring_init(rdev, rdev->cp.ring_size); 1899 if (r) 1900 return r; 1901 r = r600_cp_load_microcode(rdev); 1902 if (r) 1903 return r; 1904 r = r600_cp_resume(rdev); 1905 if (r) 1906 return r; 1907 /* write back buffer are not vital so don't worry about failure */ 1908 r600_wb_enable(rdev); 1909 return 0; 1910 } 1911 1912 void r600_vga_set_state(struct radeon_device *rdev, bool state) 1913 { 1914 uint32_t temp; 1915 1916 temp = RREG32(CONFIG_CNTL); 1917 if (state == false) { 1918 temp &= ~(1<<0); 1919 temp |= (1<<1); 1920 } else { 1921 temp &= ~(1<<1); 1922 } 1923 WREG32(CONFIG_CNTL, temp); 1924 } 1925 1926 int r600_resume(struct radeon_device *rdev) 1927 { 1928 int r; 1929 1930 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 1931 * posting will perform necessary task to bring back GPU into good 1932 * shape. 1933 */ 1934 /* post card */ 1935 atom_asic_init(rdev->mode_info.atom_context); 1936 /* Initialize clocks */ 1937 r = radeon_clocks_init(rdev); 1938 if (r) { 1939 return r; 1940 } 1941 1942 r = r600_startup(rdev); 1943 if (r) { 1944 DRM_ERROR("r600 startup failed on resume\n"); 1945 return r; 1946 } 1947 1948 r = r600_ib_test(rdev); 1949 if (r) { 1950 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1951 return r; 1952 } 1953 1954 r = r600_audio_init(rdev); 1955 if (r) { 1956 DRM_ERROR("radeon: audio resume failed\n"); 1957 return r; 1958 } 1959 1960 return r; 1961 } 1962 1963 int r600_suspend(struct radeon_device *rdev) 1964 { 1965 int r; 1966 1967 r600_audio_fini(rdev); 1968 /* FIXME: we should wait for ring to be empty */ 1969 r600_cp_stop(rdev); 1970 rdev->cp.ready = false; 1971 r600_irq_suspend(rdev); 1972 r600_wb_disable(rdev); 1973 r600_pcie_gart_disable(rdev); 1974 /* unpin shaders bo */ 1975 if (rdev->r600_blit.shader_obj) { 1976 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1977 if (!r) { 1978 radeon_bo_unpin(rdev->r600_blit.shader_obj); 1979 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 1980 } 1981 } 1982 return 0; 1983 } 1984 1985 /* Plan is to move initialization in that function and use 1986 * helper function so that radeon_device_init pretty much 1987 * do nothing more than calling asic specific function. This 1988 * should also allow to remove a bunch of callback function 1989 * like vram_info. 1990 */ 1991 int r600_init(struct radeon_device *rdev) 1992 { 1993 int r; 1994 1995 r = radeon_dummy_page_init(rdev); 1996 if (r) 1997 return r; 1998 if (r600_debugfs_mc_info_init(rdev)) { 1999 DRM_ERROR("Failed to register debugfs file for mc !\n"); 2000 } 2001 /* This don't do much */ 2002 r = radeon_gem_init(rdev); 2003 if (r) 2004 return r; 2005 /* Read BIOS */ 2006 if (!radeon_get_bios(rdev)) { 2007 if (ASIC_IS_AVIVO(rdev)) 2008 return -EINVAL; 2009 } 2010 /* Must be an ATOMBIOS */ 2011 if (!rdev->is_atom_bios) { 2012 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 2013 return -EINVAL; 2014 } 2015 r = radeon_atombios_init(rdev); 2016 if (r) 2017 return r; 2018 /* Post card if necessary */ 2019 if (!r600_card_posted(rdev)) { 2020 if (!rdev->bios) { 2021 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2022 return -EINVAL; 2023 } 2024 DRM_INFO("GPU not posted. posting now...\n"); 2025 atom_asic_init(rdev->mode_info.atom_context); 2026 } 2027 /* Initialize scratch registers */ 2028 r600_scratch_init(rdev); 2029 /* Initialize surface registers */ 2030 radeon_surface_init(rdev); 2031 /* Initialize clocks */ 2032 radeon_get_clock_info(rdev->ddev); 2033 r = radeon_clocks_init(rdev); 2034 if (r) 2035 return r; 2036 /* Initialize power management */ 2037 radeon_pm_init(rdev); 2038 /* Fence driver */ 2039 r = radeon_fence_driver_init(rdev); 2040 if (r) 2041 return r; 2042 if (rdev->flags & RADEON_IS_AGP) { 2043 r = radeon_agp_init(rdev); 2044 if (r) 2045 radeon_agp_disable(rdev); 2046 } 2047 r = r600_mc_init(rdev); 2048 if (r) 2049 return r; 2050 /* Memory manager */ 2051 r = radeon_bo_init(rdev); 2052 if (r) 2053 return r; 2054 2055 r = radeon_irq_kms_init(rdev); 2056 if (r) 2057 return r; 2058 2059 rdev->cp.ring_obj = NULL; 2060 r600_ring_init(rdev, 1024 * 1024); 2061 2062 rdev->ih.ring_obj = NULL; 2063 r600_ih_ring_init(rdev, 64 * 1024); 2064 2065 r = r600_pcie_gart_init(rdev); 2066 if (r) 2067 return r; 2068 2069 rdev->accel_working = true; 2070 r = r600_startup(rdev); 2071 if (r) { 2072 dev_err(rdev->dev, "disabling GPU acceleration\n"); 2073 r600_cp_fini(rdev); 2074 r600_wb_fini(rdev); 2075 r600_irq_fini(rdev); 2076 radeon_irq_kms_fini(rdev); 2077 r600_pcie_gart_fini(rdev); 2078 rdev->accel_working = false; 2079 } 2080 if (rdev->accel_working) { 2081 r = radeon_ib_pool_init(rdev); 2082 if (r) { 2083 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2084 rdev->accel_working = false; 2085 } else { 2086 r = r600_ib_test(rdev); 2087 if (r) { 2088 dev_err(rdev->dev, "IB test failed (%d).\n", r); 2089 rdev->accel_working = false; 2090 } 2091 } 2092 } 2093 2094 r = r600_audio_init(rdev); 2095 if (r) 2096 return r; /* TODO error handling */ 2097 return 0; 2098 } 2099 2100 void r600_fini(struct radeon_device *rdev) 2101 { 2102 radeon_pm_fini(rdev); 2103 r600_audio_fini(rdev); 2104 r600_blit_fini(rdev); 2105 r600_cp_fini(rdev); 2106 r600_wb_fini(rdev); 2107 r600_irq_fini(rdev); 2108 radeon_irq_kms_fini(rdev); 2109 r600_pcie_gart_fini(rdev); 2110 radeon_agp_fini(rdev); 2111 radeon_gem_fini(rdev); 2112 radeon_fence_driver_fini(rdev); 2113 radeon_clocks_fini(rdev); 2114 radeon_bo_fini(rdev); 2115 radeon_atombios_fini(rdev); 2116 kfree(rdev->bios); 2117 rdev->bios = NULL; 2118 radeon_dummy_page_fini(rdev); 2119 } 2120 2121 2122 /* 2123 * CS stuff 2124 */ 2125 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 2126 { 2127 /* FIXME: implement */ 2128 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2129 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); 2130 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); 2131 radeon_ring_write(rdev, ib->length_dw); 2132 } 2133 2134 int r600_ib_test(struct radeon_device *rdev) 2135 { 2136 struct radeon_ib *ib; 2137 uint32_t scratch; 2138 uint32_t tmp = 0; 2139 unsigned i; 2140 int r; 2141 2142 r = radeon_scratch_get(rdev, &scratch); 2143 if (r) { 2144 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 2145 return r; 2146 } 2147 WREG32(scratch, 0xCAFEDEAD); 2148 r = radeon_ib_get(rdev, &ib); 2149 if (r) { 2150 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 2151 return r; 2152 } 2153 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 2154 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2155 ib->ptr[2] = 0xDEADBEEF; 2156 ib->ptr[3] = PACKET2(0); 2157 ib->ptr[4] = PACKET2(0); 2158 ib->ptr[5] = PACKET2(0); 2159 ib->ptr[6] = PACKET2(0); 2160 ib->ptr[7] = PACKET2(0); 2161 ib->ptr[8] = PACKET2(0); 2162 ib->ptr[9] = PACKET2(0); 2163 ib->ptr[10] = PACKET2(0); 2164 ib->ptr[11] = PACKET2(0); 2165 ib->ptr[12] = PACKET2(0); 2166 ib->ptr[13] = PACKET2(0); 2167 ib->ptr[14] = PACKET2(0); 2168 ib->ptr[15] = PACKET2(0); 2169 ib->length_dw = 16; 2170 r = radeon_ib_schedule(rdev, ib); 2171 if (r) { 2172 radeon_scratch_free(rdev, scratch); 2173 radeon_ib_free(rdev, &ib); 2174 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 2175 return r; 2176 } 2177 r = radeon_fence_wait(ib->fence, false); 2178 if (r) { 2179 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 2180 return r; 2181 } 2182 for (i = 0; i < rdev->usec_timeout; i++) { 2183 tmp = RREG32(scratch); 2184 if (tmp == 0xDEADBEEF) 2185 break; 2186 DRM_UDELAY(1); 2187 } 2188 if (i < rdev->usec_timeout) { 2189 DRM_INFO("ib test succeeded in %u usecs\n", i); 2190 } else { 2191 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", 2192 scratch, tmp); 2193 r = -EINVAL; 2194 } 2195 radeon_scratch_free(rdev, scratch); 2196 radeon_ib_free(rdev, &ib); 2197 return r; 2198 } 2199 2200 /* 2201 * Interrupts 2202 * 2203 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 2204 * the same as the CP ring buffer, but in reverse. Rather than the CPU 2205 * writing to the ring and the GPU consuming, the GPU writes to the ring 2206 * and host consumes. As the host irq handler processes interrupts, it 2207 * increments the rptr. When the rptr catches up with the wptr, all the 2208 * current interrupts have been processed. 2209 */ 2210 2211 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 2212 { 2213 u32 rb_bufsz; 2214 2215 /* Align ring size */ 2216 rb_bufsz = drm_order(ring_size / 4); 2217 ring_size = (1 << rb_bufsz) * 4; 2218 rdev->ih.ring_size = ring_size; 2219 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 2220 rdev->ih.rptr = 0; 2221 } 2222 2223 static int r600_ih_ring_alloc(struct radeon_device *rdev) 2224 { 2225 int r; 2226 2227 /* Allocate ring buffer */ 2228 if (rdev->ih.ring_obj == NULL) { 2229 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, 2230 true, 2231 RADEON_GEM_DOMAIN_GTT, 2232 &rdev->ih.ring_obj); 2233 if (r) { 2234 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 2235 return r; 2236 } 2237 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 2238 if (unlikely(r != 0)) 2239 return r; 2240 r = radeon_bo_pin(rdev->ih.ring_obj, 2241 RADEON_GEM_DOMAIN_GTT, 2242 &rdev->ih.gpu_addr); 2243 if (r) { 2244 radeon_bo_unreserve(rdev->ih.ring_obj); 2245 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 2246 return r; 2247 } 2248 r = radeon_bo_kmap(rdev->ih.ring_obj, 2249 (void **)&rdev->ih.ring); 2250 radeon_bo_unreserve(rdev->ih.ring_obj); 2251 if (r) { 2252 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 2253 return r; 2254 } 2255 } 2256 return 0; 2257 } 2258 2259 static void r600_ih_ring_fini(struct radeon_device *rdev) 2260 { 2261 int r; 2262 if (rdev->ih.ring_obj) { 2263 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 2264 if (likely(r == 0)) { 2265 radeon_bo_kunmap(rdev->ih.ring_obj); 2266 radeon_bo_unpin(rdev->ih.ring_obj); 2267 radeon_bo_unreserve(rdev->ih.ring_obj); 2268 } 2269 radeon_bo_unref(&rdev->ih.ring_obj); 2270 rdev->ih.ring = NULL; 2271 rdev->ih.ring_obj = NULL; 2272 } 2273 } 2274 2275 static void r600_rlc_stop(struct radeon_device *rdev) 2276 { 2277 2278 if (rdev->family >= CHIP_RV770) { 2279 /* r7xx asics need to soft reset RLC before halting */ 2280 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 2281 RREG32(SRBM_SOFT_RESET); 2282 udelay(15000); 2283 WREG32(SRBM_SOFT_RESET, 0); 2284 RREG32(SRBM_SOFT_RESET); 2285 } 2286 2287 WREG32(RLC_CNTL, 0); 2288 } 2289 2290 static void r600_rlc_start(struct radeon_device *rdev) 2291 { 2292 WREG32(RLC_CNTL, RLC_ENABLE); 2293 } 2294 2295 static int r600_rlc_init(struct radeon_device *rdev) 2296 { 2297 u32 i; 2298 const __be32 *fw_data; 2299 2300 if (!rdev->rlc_fw) 2301 return -EINVAL; 2302 2303 r600_rlc_stop(rdev); 2304 2305 WREG32(RLC_HB_BASE, 0); 2306 WREG32(RLC_HB_CNTL, 0); 2307 WREG32(RLC_HB_RPTR, 0); 2308 WREG32(RLC_HB_WPTR, 0); 2309 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 2310 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 2311 WREG32(RLC_MC_CNTL, 0); 2312 WREG32(RLC_UCODE_CNTL, 0); 2313 2314 fw_data = (const __be32 *)rdev->rlc_fw->data; 2315 if (rdev->family >= CHIP_RV770) { 2316 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 2317 WREG32(RLC_UCODE_ADDR, i); 2318 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 2319 } 2320 } else { 2321 for (i = 0; i < RLC_UCODE_SIZE; i++) { 2322 WREG32(RLC_UCODE_ADDR, i); 2323 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 2324 } 2325 } 2326 WREG32(RLC_UCODE_ADDR, 0); 2327 2328 r600_rlc_start(rdev); 2329 2330 return 0; 2331 } 2332 2333 static void r600_enable_interrupts(struct radeon_device *rdev) 2334 { 2335 u32 ih_cntl = RREG32(IH_CNTL); 2336 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 2337 2338 ih_cntl |= ENABLE_INTR; 2339 ih_rb_cntl |= IH_RB_ENABLE; 2340 WREG32(IH_CNTL, ih_cntl); 2341 WREG32(IH_RB_CNTL, ih_rb_cntl); 2342 rdev->ih.enabled = true; 2343 } 2344 2345 static void r600_disable_interrupts(struct radeon_device *rdev) 2346 { 2347 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 2348 u32 ih_cntl = RREG32(IH_CNTL); 2349 2350 ih_rb_cntl &= ~IH_RB_ENABLE; 2351 ih_cntl &= ~ENABLE_INTR; 2352 WREG32(IH_RB_CNTL, ih_rb_cntl); 2353 WREG32(IH_CNTL, ih_cntl); 2354 /* set rptr, wptr to 0 */ 2355 WREG32(IH_RB_RPTR, 0); 2356 WREG32(IH_RB_WPTR, 0); 2357 rdev->ih.enabled = false; 2358 rdev->ih.wptr = 0; 2359 rdev->ih.rptr = 0; 2360 } 2361 2362 static void r600_disable_interrupt_state(struct radeon_device *rdev) 2363 { 2364 u32 tmp; 2365 2366 WREG32(CP_INT_CNTL, 0); 2367 WREG32(GRBM_INT_CNTL, 0); 2368 WREG32(DxMODE_INT_MASK, 0); 2369 if (ASIC_IS_DCE3(rdev)) { 2370 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 2371 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 2372 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2373 WREG32(DC_HPD1_INT_CONTROL, tmp); 2374 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2375 WREG32(DC_HPD2_INT_CONTROL, tmp); 2376 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2377 WREG32(DC_HPD3_INT_CONTROL, tmp); 2378 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2379 WREG32(DC_HPD4_INT_CONTROL, tmp); 2380 if (ASIC_IS_DCE32(rdev)) { 2381 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2382 WREG32(DC_HPD5_INT_CONTROL, tmp); 2383 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2384 WREG32(DC_HPD6_INT_CONTROL, tmp); 2385 } 2386 } else { 2387 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 2388 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 2389 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 2390 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 2391 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 2392 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 2393 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 2394 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 2395 } 2396 } 2397 2398 int r600_irq_init(struct radeon_device *rdev) 2399 { 2400 int ret = 0; 2401 int rb_bufsz; 2402 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 2403 2404 /* allocate ring */ 2405 ret = r600_ih_ring_alloc(rdev); 2406 if (ret) 2407 return ret; 2408 2409 /* disable irqs */ 2410 r600_disable_interrupts(rdev); 2411 2412 /* init rlc */ 2413 ret = r600_rlc_init(rdev); 2414 if (ret) { 2415 r600_ih_ring_fini(rdev); 2416 return ret; 2417 } 2418 2419 /* setup interrupt control */ 2420 /* set dummy read address to ring address */ 2421 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 2422 interrupt_cntl = RREG32(INTERRUPT_CNTL); 2423 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 2424 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 2425 */ 2426 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 2427 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 2428 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 2429 WREG32(INTERRUPT_CNTL, interrupt_cntl); 2430 2431 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 2432 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 2433 2434 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 2435 IH_WPTR_OVERFLOW_CLEAR | 2436 (rb_bufsz << 1)); 2437 /* WPTR writeback, not yet */ 2438 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/ 2439 WREG32(IH_RB_WPTR_ADDR_LO, 0); 2440 WREG32(IH_RB_WPTR_ADDR_HI, 0); 2441 2442 WREG32(IH_RB_CNTL, ih_rb_cntl); 2443 2444 /* set rptr, wptr to 0 */ 2445 WREG32(IH_RB_RPTR, 0); 2446 WREG32(IH_RB_WPTR, 0); 2447 2448 /* Default settings for IH_CNTL (disabled at first) */ 2449 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 2450 /* RPTR_REARM only works if msi's are enabled */ 2451 if (rdev->msi_enabled) 2452 ih_cntl |= RPTR_REARM; 2453 2454 #ifdef __BIG_ENDIAN 2455 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT); 2456 #endif 2457 WREG32(IH_CNTL, ih_cntl); 2458 2459 /* force the active interrupt state to all disabled */ 2460 r600_disable_interrupt_state(rdev); 2461 2462 /* enable irqs */ 2463 r600_enable_interrupts(rdev); 2464 2465 return ret; 2466 } 2467 2468 void r600_irq_suspend(struct radeon_device *rdev) 2469 { 2470 r600_disable_interrupts(rdev); 2471 r600_rlc_stop(rdev); 2472 } 2473 2474 void r600_irq_fini(struct radeon_device *rdev) 2475 { 2476 r600_irq_suspend(rdev); 2477 r600_ih_ring_fini(rdev); 2478 } 2479 2480 int r600_irq_set(struct radeon_device *rdev) 2481 { 2482 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 2483 u32 mode_int = 0; 2484 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 2485 2486 if (!rdev->irq.installed) { 2487 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); 2488 return -EINVAL; 2489 } 2490 /* don't enable anything if the ih is disabled */ 2491 if (!rdev->ih.enabled) { 2492 r600_disable_interrupts(rdev); 2493 /* force the active interrupt state to all disabled */ 2494 r600_disable_interrupt_state(rdev); 2495 return 0; 2496 } 2497 2498 if (ASIC_IS_DCE3(rdev)) { 2499 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2500 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 2501 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 2502 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 2503 if (ASIC_IS_DCE32(rdev)) { 2504 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 2505 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 2506 } 2507 } else { 2508 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2509 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 2510 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 2511 } 2512 2513 if (rdev->irq.sw_int) { 2514 DRM_DEBUG("r600_irq_set: sw int\n"); 2515 cp_int_cntl |= RB_INT_ENABLE; 2516 } 2517 if (rdev->irq.crtc_vblank_int[0]) { 2518 DRM_DEBUG("r600_irq_set: vblank 0\n"); 2519 mode_int |= D1MODE_VBLANK_INT_MASK; 2520 } 2521 if (rdev->irq.crtc_vblank_int[1]) { 2522 DRM_DEBUG("r600_irq_set: vblank 1\n"); 2523 mode_int |= D2MODE_VBLANK_INT_MASK; 2524 } 2525 if (rdev->irq.hpd[0]) { 2526 DRM_DEBUG("r600_irq_set: hpd 1\n"); 2527 hpd1 |= DC_HPDx_INT_EN; 2528 } 2529 if (rdev->irq.hpd[1]) { 2530 DRM_DEBUG("r600_irq_set: hpd 2\n"); 2531 hpd2 |= DC_HPDx_INT_EN; 2532 } 2533 if (rdev->irq.hpd[2]) { 2534 DRM_DEBUG("r600_irq_set: hpd 3\n"); 2535 hpd3 |= DC_HPDx_INT_EN; 2536 } 2537 if (rdev->irq.hpd[3]) { 2538 DRM_DEBUG("r600_irq_set: hpd 4\n"); 2539 hpd4 |= DC_HPDx_INT_EN; 2540 } 2541 if (rdev->irq.hpd[4]) { 2542 DRM_DEBUG("r600_irq_set: hpd 5\n"); 2543 hpd5 |= DC_HPDx_INT_EN; 2544 } 2545 if (rdev->irq.hpd[5]) { 2546 DRM_DEBUG("r600_irq_set: hpd 6\n"); 2547 hpd6 |= DC_HPDx_INT_EN; 2548 } 2549 2550 WREG32(CP_INT_CNTL, cp_int_cntl); 2551 WREG32(DxMODE_INT_MASK, mode_int); 2552 if (ASIC_IS_DCE3(rdev)) { 2553 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2554 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2555 WREG32(DC_HPD3_INT_CONTROL, hpd3); 2556 WREG32(DC_HPD4_INT_CONTROL, hpd4); 2557 if (ASIC_IS_DCE32(rdev)) { 2558 WREG32(DC_HPD5_INT_CONTROL, hpd5); 2559 WREG32(DC_HPD6_INT_CONTROL, hpd6); 2560 } 2561 } else { 2562 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 2563 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 2564 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 2565 } 2566 2567 return 0; 2568 } 2569 2570 static inline void r600_irq_ack(struct radeon_device *rdev, 2571 u32 *disp_int, 2572 u32 *disp_int_cont, 2573 u32 *disp_int_cont2) 2574 { 2575 u32 tmp; 2576 2577 if (ASIC_IS_DCE3(rdev)) { 2578 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 2579 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 2580 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 2581 } else { 2582 *disp_int = RREG32(DISP_INTERRUPT_STATUS); 2583 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 2584 *disp_int_cont2 = 0; 2585 } 2586 2587 if (*disp_int & LB_D1_VBLANK_INTERRUPT) 2588 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 2589 if (*disp_int & LB_D1_VLINE_INTERRUPT) 2590 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 2591 if (*disp_int & LB_D2_VBLANK_INTERRUPT) 2592 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 2593 if (*disp_int & LB_D2_VLINE_INTERRUPT) 2594 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 2595 if (*disp_int & DC_HPD1_INTERRUPT) { 2596 if (ASIC_IS_DCE3(rdev)) { 2597 tmp = RREG32(DC_HPD1_INT_CONTROL); 2598 tmp |= DC_HPDx_INT_ACK; 2599 WREG32(DC_HPD1_INT_CONTROL, tmp); 2600 } else { 2601 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 2602 tmp |= DC_HPDx_INT_ACK; 2603 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 2604 } 2605 } 2606 if (*disp_int & DC_HPD2_INTERRUPT) { 2607 if (ASIC_IS_DCE3(rdev)) { 2608 tmp = RREG32(DC_HPD2_INT_CONTROL); 2609 tmp |= DC_HPDx_INT_ACK; 2610 WREG32(DC_HPD2_INT_CONTROL, tmp); 2611 } else { 2612 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 2613 tmp |= DC_HPDx_INT_ACK; 2614 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 2615 } 2616 } 2617 if (*disp_int_cont & DC_HPD3_INTERRUPT) { 2618 if (ASIC_IS_DCE3(rdev)) { 2619 tmp = RREG32(DC_HPD3_INT_CONTROL); 2620 tmp |= DC_HPDx_INT_ACK; 2621 WREG32(DC_HPD3_INT_CONTROL, tmp); 2622 } else { 2623 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 2624 tmp |= DC_HPDx_INT_ACK; 2625 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 2626 } 2627 } 2628 if (*disp_int_cont & DC_HPD4_INTERRUPT) { 2629 tmp = RREG32(DC_HPD4_INT_CONTROL); 2630 tmp |= DC_HPDx_INT_ACK; 2631 WREG32(DC_HPD4_INT_CONTROL, tmp); 2632 } 2633 if (ASIC_IS_DCE32(rdev)) { 2634 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) { 2635 tmp = RREG32(DC_HPD5_INT_CONTROL); 2636 tmp |= DC_HPDx_INT_ACK; 2637 WREG32(DC_HPD5_INT_CONTROL, tmp); 2638 } 2639 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) { 2640 tmp = RREG32(DC_HPD5_INT_CONTROL); 2641 tmp |= DC_HPDx_INT_ACK; 2642 WREG32(DC_HPD6_INT_CONTROL, tmp); 2643 } 2644 } 2645 } 2646 2647 void r600_irq_disable(struct radeon_device *rdev) 2648 { 2649 u32 disp_int, disp_int_cont, disp_int_cont2; 2650 2651 r600_disable_interrupts(rdev); 2652 /* Wait and acknowledge irq */ 2653 mdelay(1); 2654 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); 2655 r600_disable_interrupt_state(rdev); 2656 } 2657 2658 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev) 2659 { 2660 u32 wptr, tmp; 2661 2662 /* XXX use writeback */ 2663 wptr = RREG32(IH_RB_WPTR); 2664 2665 if (wptr & RB_OVERFLOW) { 2666 /* When a ring buffer overflow happen start parsing interrupt 2667 * from the last not overwritten vector (wptr + 16). Hopefully 2668 * this should allow us to catchup. 2669 */ 2670 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 2671 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 2672 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 2673 tmp = RREG32(IH_RB_CNTL); 2674 tmp |= IH_WPTR_OVERFLOW_CLEAR; 2675 WREG32(IH_RB_CNTL, tmp); 2676 } 2677 return (wptr & rdev->ih.ptr_mask); 2678 } 2679 2680 /* r600 IV Ring 2681 * Each IV ring entry is 128 bits: 2682 * [7:0] - interrupt source id 2683 * [31:8] - reserved 2684 * [59:32] - interrupt source data 2685 * [127:60] - reserved 2686 * 2687 * The basic interrupt vector entries 2688 * are decoded as follows: 2689 * src_id src_data description 2690 * 1 0 D1 Vblank 2691 * 1 1 D1 Vline 2692 * 5 0 D2 Vblank 2693 * 5 1 D2 Vline 2694 * 19 0 FP Hot plug detection A 2695 * 19 1 FP Hot plug detection B 2696 * 19 2 DAC A auto-detection 2697 * 19 3 DAC B auto-detection 2698 * 176 - CP_INT RB 2699 * 177 - CP_INT IB1 2700 * 178 - CP_INT IB2 2701 * 181 - EOP Interrupt 2702 * 233 - GUI Idle 2703 * 2704 * Note, these are based on r600 and may need to be 2705 * adjusted or added to on newer asics 2706 */ 2707 2708 int r600_irq_process(struct radeon_device *rdev) 2709 { 2710 u32 wptr = r600_get_ih_wptr(rdev); 2711 u32 rptr = rdev->ih.rptr; 2712 u32 src_id, src_data; 2713 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2; 2714 unsigned long flags; 2715 bool queue_hotplug = false; 2716 2717 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2718 if (!rdev->ih.enabled) 2719 return IRQ_NONE; 2720 2721 spin_lock_irqsave(&rdev->ih.lock, flags); 2722 2723 if (rptr == wptr) { 2724 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2725 return IRQ_NONE; 2726 } 2727 if (rdev->shutdown) { 2728 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2729 return IRQ_NONE; 2730 } 2731 2732 restart_ih: 2733 /* display interrupts */ 2734 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); 2735 2736 rdev->ih.wptr = wptr; 2737 while (rptr != wptr) { 2738 /* wptr/rptr are in bytes! */ 2739 ring_index = rptr / 4; 2740 src_id = rdev->ih.ring[ring_index] & 0xff; 2741 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; 2742 2743 switch (src_id) { 2744 case 1: /* D1 vblank/vline */ 2745 switch (src_data) { 2746 case 0: /* D1 vblank */ 2747 if (disp_int & LB_D1_VBLANK_INTERRUPT) { 2748 drm_handle_vblank(rdev->ddev, 0); 2749 rdev->pm.vblank_sync = true; 2750 wake_up(&rdev->irq.vblank_queue); 2751 disp_int &= ~LB_D1_VBLANK_INTERRUPT; 2752 DRM_DEBUG("IH: D1 vblank\n"); 2753 } 2754 break; 2755 case 1: /* D1 vline */ 2756 if (disp_int & LB_D1_VLINE_INTERRUPT) { 2757 disp_int &= ~LB_D1_VLINE_INTERRUPT; 2758 DRM_DEBUG("IH: D1 vline\n"); 2759 } 2760 break; 2761 default: 2762 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2763 break; 2764 } 2765 break; 2766 case 5: /* D2 vblank/vline */ 2767 switch (src_data) { 2768 case 0: /* D2 vblank */ 2769 if (disp_int & LB_D2_VBLANK_INTERRUPT) { 2770 drm_handle_vblank(rdev->ddev, 1); 2771 rdev->pm.vblank_sync = true; 2772 wake_up(&rdev->irq.vblank_queue); 2773 disp_int &= ~LB_D2_VBLANK_INTERRUPT; 2774 DRM_DEBUG("IH: D2 vblank\n"); 2775 } 2776 break; 2777 case 1: /* D1 vline */ 2778 if (disp_int & LB_D2_VLINE_INTERRUPT) { 2779 disp_int &= ~LB_D2_VLINE_INTERRUPT; 2780 DRM_DEBUG("IH: D2 vline\n"); 2781 } 2782 break; 2783 default: 2784 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2785 break; 2786 } 2787 break; 2788 case 19: /* HPD/DAC hotplug */ 2789 switch (src_data) { 2790 case 0: 2791 if (disp_int & DC_HPD1_INTERRUPT) { 2792 disp_int &= ~DC_HPD1_INTERRUPT; 2793 queue_hotplug = true; 2794 DRM_DEBUG("IH: HPD1\n"); 2795 } 2796 break; 2797 case 1: 2798 if (disp_int & DC_HPD2_INTERRUPT) { 2799 disp_int &= ~DC_HPD2_INTERRUPT; 2800 queue_hotplug = true; 2801 DRM_DEBUG("IH: HPD2\n"); 2802 } 2803 break; 2804 case 4: 2805 if (disp_int_cont & DC_HPD3_INTERRUPT) { 2806 disp_int_cont &= ~DC_HPD3_INTERRUPT; 2807 queue_hotplug = true; 2808 DRM_DEBUG("IH: HPD3\n"); 2809 } 2810 break; 2811 case 5: 2812 if (disp_int_cont & DC_HPD4_INTERRUPT) { 2813 disp_int_cont &= ~DC_HPD4_INTERRUPT; 2814 queue_hotplug = true; 2815 DRM_DEBUG("IH: HPD4\n"); 2816 } 2817 break; 2818 case 10: 2819 if (disp_int_cont2 & DC_HPD5_INTERRUPT) { 2820 disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 2821 queue_hotplug = true; 2822 DRM_DEBUG("IH: HPD5\n"); 2823 } 2824 break; 2825 case 12: 2826 if (disp_int_cont2 & DC_HPD6_INTERRUPT) { 2827 disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 2828 queue_hotplug = true; 2829 DRM_DEBUG("IH: HPD6\n"); 2830 } 2831 break; 2832 default: 2833 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2834 break; 2835 } 2836 break; 2837 case 176: /* CP_INT in ring buffer */ 2838 case 177: /* CP_INT in IB1 */ 2839 case 178: /* CP_INT in IB2 */ 2840 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 2841 radeon_fence_process(rdev); 2842 break; 2843 case 181: /* CP EOP event */ 2844 DRM_DEBUG("IH: CP EOP\n"); 2845 break; 2846 default: 2847 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2848 break; 2849 } 2850 2851 /* wptr/rptr are in bytes! */ 2852 rptr += 16; 2853 rptr &= rdev->ih.ptr_mask; 2854 } 2855 /* make sure wptr hasn't changed while processing */ 2856 wptr = r600_get_ih_wptr(rdev); 2857 if (wptr != rdev->ih.wptr) 2858 goto restart_ih; 2859 if (queue_hotplug) 2860 queue_work(rdev->wq, &rdev->hotplug_work); 2861 rdev->ih.rptr = rptr; 2862 WREG32(IH_RB_RPTR, rdev->ih.rptr); 2863 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2864 return IRQ_HANDLED; 2865 } 2866 2867 /* 2868 * Debugfs info 2869 */ 2870 #if defined(CONFIG_DEBUG_FS) 2871 2872 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) 2873 { 2874 struct drm_info_node *node = (struct drm_info_node *) m->private; 2875 struct drm_device *dev = node->minor->dev; 2876 struct radeon_device *rdev = dev->dev_private; 2877 unsigned count, i, j; 2878 2879 radeon_ring_free_size(rdev); 2880 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; 2881 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); 2882 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); 2883 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); 2884 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); 2885 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); 2886 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); 2887 seq_printf(m, "%u dwords in ring\n", count); 2888 i = rdev->cp.rptr; 2889 for (j = 0; j <= count; j++) { 2890 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); 2891 i = (i + 1) & rdev->cp.ptr_mask; 2892 } 2893 return 0; 2894 } 2895 2896 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 2897 { 2898 struct drm_info_node *node = (struct drm_info_node *) m->private; 2899 struct drm_device *dev = node->minor->dev; 2900 struct radeon_device *rdev = dev->dev_private; 2901 2902 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 2903 DREG32_SYS(m, rdev, VM_L2_STATUS); 2904 return 0; 2905 } 2906 2907 static struct drm_info_list r600_mc_info_list[] = { 2908 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 2909 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, 2910 }; 2911 #endif 2912 2913 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 2914 { 2915 #if defined(CONFIG_DEBUG_FS) 2916 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 2917 #else 2918 return 0; 2919 #endif 2920 } 2921 2922 /** 2923 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl 2924 * rdev: radeon device structure 2925 * bo: buffer object struct which userspace is waiting for idle 2926 * 2927 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed 2928 * through ring buffer, this leads to corruption in rendering, see 2929 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we 2930 * directly perform HDP flush by writing register through MMIO. 2931 */ 2932 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 2933 { 2934 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 2935 } 2936