r300.c (e0273728564a395a13cfed70e34da4f2613d2d44) r300.c (721604a15b934f0a8d1909acb8017f029128be2f)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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170 radeon_gart_fini(rdev);
171 rv370_pcie_gart_disable(rdev);
172 radeon_gart_table_vram_free(rdev);
173}
174
175void r300_fence_ring_emit(struct radeon_device *rdev,
176 struct radeon_fence *fence)
177{
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 161 unchanged lines hidden (view full) ---

170 radeon_gart_fini(rdev);
171 rv370_pcie_gart_disable(rdev);
172 radeon_gart_table_vram_free(rdev);
173}
174
175void r300_fence_ring_emit(struct radeon_device *rdev,
176 struct radeon_fence *fence)
177{
178 struct radeon_ring *ring = &rdev->ring[fence->ring];
179
178 /* Who ever call radeon_fence_emit should call ring_lock and ask
179 * for enough space (today caller are ib schedule and buffer move) */
180 /* Write SC register so SC & US assert idle */
180 /* Who ever call radeon_fence_emit should call ring_lock and ask
181 * for enough space (today caller are ib schedule and buffer move) */
182 /* Write SC register so SC & US assert idle */
181 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
182 radeon_ring_write(rdev, 0);
183 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
184 radeon_ring_write(rdev, 0);
183 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
184 radeon_ring_write(ring, 0);
185 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
186 radeon_ring_write(ring, 0);
185 /* Flush 3D cache */
187 /* Flush 3D cache */
186 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
187 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
188 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
189 radeon_ring_write(rdev, R300_ZC_FLUSH);
188 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
189 radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
190 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
191 radeon_ring_write(ring, R300_ZC_FLUSH);
190 /* Wait until IDLE & CLEAN */
192 /* Wait until IDLE & CLEAN */
191 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
192 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
193 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
194 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
193 RADEON_WAIT_2D_IDLECLEAN |
194 RADEON_WAIT_DMA_GUI_IDLE));
195 RADEON_WAIT_2D_IDLECLEAN |
196 RADEON_WAIT_DMA_GUI_IDLE));
195 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
196 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
197 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
198 radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
197 RADEON_HDP_READ_BUFFER_INVALIDATE);
199 RADEON_HDP_READ_BUFFER_INVALIDATE);
198 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
199 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
200 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
201 radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
200 /* Emit fence sequence & fire IRQ */
202 /* Emit fence sequence & fire IRQ */
201 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
202 radeon_ring_write(rdev, fence->seq);
203 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
204 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
203 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
204 radeon_ring_write(ring, fence->seq);
205 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
206 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
205}
206
207void r300_ring_start(struct radeon_device *rdev)
208{
207}
208
209void r300_ring_start(struct radeon_device *rdev)
210{
211 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
209 unsigned gb_tile_config;
210 int r;
211
212 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
213 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
214 switch(rdev->num_gb_pipes) {
215 case 2:
216 gb_tile_config |= R300_PIPE_COUNT_R300;

--- 5 unchanged lines hidden (view full) ---

222 gb_tile_config |= R300_PIPE_COUNT_R420;
223 break;
224 case 1:
225 default:
226 gb_tile_config |= R300_PIPE_COUNT_RV350;
227 break;
228 }
229
212 unsigned gb_tile_config;
213 int r;
214
215 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
216 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
217 switch(rdev->num_gb_pipes) {
218 case 2:
219 gb_tile_config |= R300_PIPE_COUNT_R300;

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225 gb_tile_config |= R300_PIPE_COUNT_R420;
226 break;
227 case 1:
228 default:
229 gb_tile_config |= R300_PIPE_COUNT_RV350;
230 break;
231 }
232
230 r = radeon_ring_lock(rdev, 64);
233 r = radeon_ring_lock(rdev, ring, 64);
231 if (r) {
232 return;
233 }
234 if (r) {
235 return;
236 }
234 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
235 radeon_ring_write(rdev,
237 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
238 radeon_ring_write(ring,
236 RADEON_ISYNC_ANY2D_IDLE3D |
237 RADEON_ISYNC_ANY3D_IDLE2D |
238 RADEON_ISYNC_WAIT_IDLEGUI |
239 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
239 RADEON_ISYNC_ANY2D_IDLE3D |
240 RADEON_ISYNC_ANY3D_IDLE2D |
241 RADEON_ISYNC_WAIT_IDLEGUI |
242 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
240 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
241 radeon_ring_write(rdev, gb_tile_config);
242 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
243 radeon_ring_write(rdev,
243 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
244 radeon_ring_write(ring, gb_tile_config);
245 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
246 radeon_ring_write(ring,
244 RADEON_WAIT_2D_IDLECLEAN |
245 RADEON_WAIT_3D_IDLECLEAN);
247 RADEON_WAIT_2D_IDLECLEAN |
248 RADEON_WAIT_3D_IDLECLEAN);
246 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
247 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
248 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
249 radeon_ring_write(rdev, 0);
250 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
251 radeon_ring_write(rdev, 0);
252 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
253 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
254 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
255 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
256 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
257 radeon_ring_write(rdev,
249 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
250 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
251 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
252 radeon_ring_write(ring, 0);
253 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
254 radeon_ring_write(ring, 0);
255 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
256 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
257 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
258 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
259 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
260 radeon_ring_write(ring,
258 RADEON_WAIT_2D_IDLECLEAN |
259 RADEON_WAIT_3D_IDLECLEAN);
261 RADEON_WAIT_2D_IDLECLEAN |
262 RADEON_WAIT_3D_IDLECLEAN);
260 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
261 radeon_ring_write(rdev, 0);
262 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
263 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
264 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
265 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
266 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
267 radeon_ring_write(rdev,
263 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
264 radeon_ring_write(ring, 0);
265 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
266 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
267 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
268 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
269 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
270 radeon_ring_write(ring,
268 ((6 << R300_MS_X0_SHIFT) |
269 (6 << R300_MS_Y0_SHIFT) |
270 (6 << R300_MS_X1_SHIFT) |
271 (6 << R300_MS_Y1_SHIFT) |
272 (6 << R300_MS_X2_SHIFT) |
273 (6 << R300_MS_Y2_SHIFT) |
274 (6 << R300_MSBD0_Y_SHIFT) |
275 (6 << R300_MSBD0_X_SHIFT)));
271 ((6 << R300_MS_X0_SHIFT) |
272 (6 << R300_MS_Y0_SHIFT) |
273 (6 << R300_MS_X1_SHIFT) |
274 (6 << R300_MS_Y1_SHIFT) |
275 (6 << R300_MS_X2_SHIFT) |
276 (6 << R300_MS_Y2_SHIFT) |
277 (6 << R300_MSBD0_Y_SHIFT) |
278 (6 << R300_MSBD0_X_SHIFT)));
276 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
277 radeon_ring_write(rdev,
279 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
280 radeon_ring_write(ring,
278 ((6 << R300_MS_X3_SHIFT) |
279 (6 << R300_MS_Y3_SHIFT) |
280 (6 << R300_MS_X4_SHIFT) |
281 (6 << R300_MS_Y4_SHIFT) |
282 (6 << R300_MS_X5_SHIFT) |
283 (6 << R300_MS_Y5_SHIFT) |
284 (6 << R300_MSBD1_SHIFT)));
281 ((6 << R300_MS_X3_SHIFT) |
282 (6 << R300_MS_Y3_SHIFT) |
283 (6 << R300_MS_X4_SHIFT) |
284 (6 << R300_MS_Y4_SHIFT) |
285 (6 << R300_MS_X5_SHIFT) |
286 (6 << R300_MS_Y5_SHIFT) |
287 (6 << R300_MSBD1_SHIFT)));
285 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
286 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
287 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
288 radeon_ring_write(rdev,
288 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
289 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
290 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
291 radeon_ring_write(ring,
289 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
292 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
290 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
291 radeon_ring_write(rdev,
293 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
294 radeon_ring_write(ring,
292 R300_GEOMETRY_ROUND_NEAREST |
293 R300_COLOR_ROUND_NEAREST);
295 R300_GEOMETRY_ROUND_NEAREST |
296 R300_COLOR_ROUND_NEAREST);
294 radeon_ring_unlock_commit(rdev);
297 radeon_ring_unlock_commit(rdev, ring);
295}
296
297void r300_errata(struct radeon_device *rdev)
298{
299 rdev->pll_errata = 0;
300
301 if (rdev->family == CHIP_R300 &&
302 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {

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370 if (r300_mc_wait_for_idle(rdev)) {
371 printk(KERN_WARNING "Failed to wait MC idle while "
372 "programming pipes. Bad things might happen.\n");
373 }
374 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
375 rdev->num_gb_pipes, rdev->num_z_pipes);
376}
377
298}
299
300void r300_errata(struct radeon_device *rdev)
301{
302 rdev->pll_errata = 0;
303
304 if (rdev->family == CHIP_R300 &&
305 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {

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373 if (r300_mc_wait_for_idle(rdev)) {
374 printk(KERN_WARNING "Failed to wait MC idle while "
375 "programming pipes. Bad things might happen.\n");
376 }
377 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
378 rdev->num_gb_pipes, rdev->num_z_pipes);
379}
380
378bool r300_gpu_is_lockup(struct radeon_device *rdev)
381bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
379{
380 u32 rbbm_status;
381 int r;
382
383 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
384 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
382{
383 u32 rbbm_status;
384 int r;
385
386 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
387 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
385 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
388 r100_gpu_lockup_update(&rdev->config.r300.lockup, ring);
386 return false;
387 }
388 /* force CP activities */
389 return false;
390 }
391 /* force CP activities */
389 r = radeon_ring_lock(rdev, 2);
392 r = radeon_ring_lock(rdev, ring, 2);
390 if (!r) {
391 /* PACKET2 NOP */
393 if (!r) {
394 /* PACKET2 NOP */
392 radeon_ring_write(rdev, 0x80000000);
393 radeon_ring_write(rdev, 0x80000000);
394 radeon_ring_unlock_commit(rdev);
395 radeon_ring_write(ring, 0x80000000);
396 radeon_ring_write(ring, 0x80000000);
397 radeon_ring_unlock_commit(rdev, ring);
395 }
398 }
396 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
397 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
399 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
400 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, ring);
398}
399
400int r300_asic_reset(struct radeon_device *rdev)
401{
402 struct r100_mc_save save;
403 u32 status, tmp;
404 int ret = 0;
405

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696 r = r100_cs_packet_next_reloc(p, &reloc);
697 if (r) {
698 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
699 idx, reg);
700 r100_cs_dump_packet(p, pkt);
701 return r;
702 }
703
401}
402
403int r300_asic_reset(struct radeon_device *rdev)
404{
405 struct r100_mc_save save;
406 u32 status, tmp;
407 int ret = 0;
408

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699 r = r100_cs_packet_next_reloc(p, &reloc);
700 if (r) {
701 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
702 idx, reg);
703 r100_cs_dump_packet(p, pkt);
704 return r;
705 }
706
704 if (p->keep_tiling_flags) {
707 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
705 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
706 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
707 } else {
708 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
709 tile_flags |= R300_TXO_MACRO_TILE;
710 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
711 tile_flags |= R300_TXO_MICRO_TILE;
712 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)

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760 case 0x4E38:
761 case 0x4E3C:
762 case 0x4E40:
763 case 0x4E44:
764 /* RB3D_COLORPITCH0 */
765 /* RB3D_COLORPITCH1 */
766 /* RB3D_COLORPITCH2 */
767 /* RB3D_COLORPITCH3 */
708 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
709 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
710 } else {
711 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
712 tile_flags |= R300_TXO_MACRO_TILE;
713 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
714 tile_flags |= R300_TXO_MICRO_TILE;
715 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)

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763 case 0x4E38:
764 case 0x4E3C:
765 case 0x4E40:
766 case 0x4E44:
767 /* RB3D_COLORPITCH0 */
768 /* RB3D_COLORPITCH1 */
769 /* RB3D_COLORPITCH2 */
770 /* RB3D_COLORPITCH3 */
768 if (!p->keep_tiling_flags) {
771 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
769 r = r100_cs_packet_next_reloc(p, &reloc);
770 if (r) {
771 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
772 idx, reg);
773 r100_cs_dump_packet(p, pkt);
774 return r;
775 }
776

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845 DRM_ERROR("Invalid z buffer format (%d) !\n",
846 (idx_value & 0xF));
847 return -EINVAL;
848 }
849 track->zb_dirty = true;
850 break;
851 case 0x4F24:
852 /* ZB_DEPTHPITCH */
772 r = r100_cs_packet_next_reloc(p, &reloc);
773 if (r) {
774 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
775 idx, reg);
776 r100_cs_dump_packet(p, pkt);
777 return r;
778 }
779

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848 DRM_ERROR("Invalid z buffer format (%d) !\n",
849 (idx_value & 0xF));
850 return -EINVAL;
851 }
852 track->zb_dirty = true;
853 break;
854 case 0x4F24:
855 /* ZB_DEPTHPITCH */
853 if (!p->keep_tiling_flags) {
856 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
854 r = r100_cs_packet_next_reloc(p, &reloc);
855 if (r) {
856 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
857 idx, reg);
858 r100_cs_dump_packet(p, pkt);
859 return r;
860 }
861

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1391 return r;
1392 }
1393
1394 /* allocate wb buffer */
1395 r = radeon_wb_init(rdev);
1396 if (r)
1397 return r;
1398
857 r = r100_cs_packet_next_reloc(p, &reloc);
858 if (r) {
859 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
860 idx, reg);
861 r100_cs_dump_packet(p, pkt);
862 return r;
863 }
864

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1394 return r;
1395 }
1396
1397 /* allocate wb buffer */
1398 r = radeon_wb_init(rdev);
1399 if (r)
1400 return r;
1401
1402 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1403 if (r) {
1404 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1405 return r;
1406 }
1407
1399 /* Enable IRQ */
1400 r100_irq_set(rdev);
1401 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1402 /* 1M ring buffer */
1403 r = r100_cp_init(rdev, 1024 * 1024);
1404 if (r) {
1405 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1406 return r;
1407 }
1408 /* Enable IRQ */
1409 r100_irq_set(rdev);
1410 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1411 /* 1M ring buffer */
1412 r = r100_cp_init(rdev, 1024 * 1024);
1413 if (r) {
1414 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1415 return r;
1416 }
1408 r = r100_ib_init(rdev);
1417
1418 r = radeon_ib_pool_start(rdev);
1419 if (r)
1420 return r;
1421
1422 r = r100_ib_test(rdev);
1409 if (r) {
1423 if (r) {
1410 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
1424 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
1425 rdev->accel_working = false;
1411 return r;
1412 }
1426 return r;
1427 }
1428
1413 return 0;
1414}
1415
1416int r300_resume(struct radeon_device *rdev)
1417{
1418 /* Make sur GART are not working */
1419 if (rdev->flags & RADEON_IS_PCIE)
1420 rv370_pcie_gart_disable(rdev);

--- 8 unchanged lines hidden (view full) ---

1429 RREG32(R_0007C0_CP_STAT));
1430 }
1431 /* post */
1432 radeon_combios_asic_init(rdev->ddev);
1433 /* Resume clock after posting */
1434 r300_clock_startup(rdev);
1435 /* Initialize surface registers */
1436 radeon_surface_init(rdev);
1429 return 0;
1430}
1431
1432int r300_resume(struct radeon_device *rdev)
1433{
1434 /* Make sur GART are not working */
1435 if (rdev->flags & RADEON_IS_PCIE)
1436 rv370_pcie_gart_disable(rdev);

--- 8 unchanged lines hidden (view full) ---

1445 RREG32(R_0007C0_CP_STAT));
1446 }
1447 /* post */
1448 radeon_combios_asic_init(rdev->ddev);
1449 /* Resume clock after posting */
1450 r300_clock_startup(rdev);
1451 /* Initialize surface registers */
1452 radeon_surface_init(rdev);
1453
1454 rdev->accel_working = true;
1437 return r300_startup(rdev);
1438}
1439
1440int r300_suspend(struct radeon_device *rdev)
1441{
1455 return r300_startup(rdev);
1456}
1457
1458int r300_suspend(struct radeon_device *rdev)
1459{
1460 radeon_ib_pool_suspend(rdev);
1442 r100_cp_disable(rdev);
1443 radeon_wb_disable(rdev);
1444 r100_irq_disable(rdev);
1445 if (rdev->flags & RADEON_IS_PCIE)
1446 rv370_pcie_gart_disable(rdev);
1447 if (rdev->flags & RADEON_IS_PCI)
1448 r100_pci_gart_disable(rdev);
1449 return 0;

--- 84 unchanged lines hidden (view full) ---

1534 return r;
1535 }
1536 if (rdev->flags & RADEON_IS_PCI) {
1537 r = r100_pci_gart_init(rdev);
1538 if (r)
1539 return r;
1540 }
1541 r300_set_reg_safe(rdev);
1461 r100_cp_disable(rdev);
1462 radeon_wb_disable(rdev);
1463 r100_irq_disable(rdev);
1464 if (rdev->flags & RADEON_IS_PCIE)
1465 rv370_pcie_gart_disable(rdev);
1466 if (rdev->flags & RADEON_IS_PCI)
1467 r100_pci_gart_disable(rdev);
1468 return 0;

--- 84 unchanged lines hidden (view full) ---

1553 return r;
1554 }
1555 if (rdev->flags & RADEON_IS_PCI) {
1556 r = r100_pci_gart_init(rdev);
1557 if (r)
1558 return r;
1559 }
1560 r300_set_reg_safe(rdev);
1561
1562 r = radeon_ib_pool_init(rdev);
1542 rdev->accel_working = true;
1563 rdev->accel_working = true;
1564 if (r) {
1565 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1566 rdev->accel_working = false;
1567 }
1568
1543 r = r300_startup(rdev);
1544 if (r) {
1545 /* Somethings want wront with the accel init stop accel */
1546 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1547 r100_cp_fini(rdev);
1548 radeon_wb_fini(rdev);
1549 r100_ib_fini(rdev);
1550 radeon_irq_kms_fini(rdev);
1551 if (rdev->flags & RADEON_IS_PCIE)
1552 rv370_pcie_gart_fini(rdev);
1553 if (rdev->flags & RADEON_IS_PCI)
1554 r100_pci_gart_fini(rdev);
1555 radeon_agp_fini(rdev);
1556 rdev->accel_working = false;
1557 }
1558 return 0;
1559}
1569 r = r300_startup(rdev);
1570 if (r) {
1571 /* Somethings want wront with the accel init stop accel */
1572 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1573 r100_cp_fini(rdev);
1574 radeon_wb_fini(rdev);
1575 r100_ib_fini(rdev);
1576 radeon_irq_kms_fini(rdev);
1577 if (rdev->flags & RADEON_IS_PCIE)
1578 rv370_pcie_gart_fini(rdev);
1579 if (rdev->flags & RADEON_IS_PCI)
1580 r100_pci_gart_fini(rdev);
1581 radeon_agp_fini(rdev);
1582 rdev->accel_working = false;
1583 }
1584 return 0;
1585}