1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include <drm/drm.h> 32 #include <drm/drm_crtc_helper.h> 33 #include "radeon_reg.h" 34 #include "radeon.h" 35 #include "radeon_asic.h" 36 #include "radeon_drm.h" 37 #include "r100_track.h" 38 #include "r300d.h" 39 #include "rv350d.h" 40 #include "r300_reg_safe.h" 41 42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 43 * 44 * GPU Errata: 45 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 46 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 47 * However, scheduling such write to the ring seems harmless, i suspect 48 * the CP read collide with the flush somehow, or maybe the MC, hard to 49 * tell. (Jerome Glisse) 50 */ 51 52 /* 53 * rv370,rv380 PCIE GART 54 */ 55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 56 57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 58 { 59 uint32_t tmp; 60 int i; 61 62 /* Workaround HW bug do flush 2 times */ 63 for (i = 0; i < 2; i++) { 64 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 65 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 66 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 67 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 68 } 69 mb(); 70 } 71 72 #define R300_PTE_WRITEABLE (1 << 2) 73 #define R300_PTE_READABLE (1 << 3) 74 75 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 76 { 77 void __iomem *ptr = rdev->gart.ptr; 78 79 if (i < 0 || i > rdev->gart.num_gpu_pages) { 80 return -EINVAL; 81 } 82 addr = (lower_32_bits(addr) >> 8) | 83 ((upper_32_bits(addr) & 0xff) << 24) | 84 R300_PTE_WRITEABLE | R300_PTE_READABLE; 85 /* on x86 we want this to be CPU endian, on powerpc 86 * on powerpc without HW swappers, it'll get swapped on way 87 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 88 writel(addr, ((void __iomem *)ptr) + (i * 4)); 89 return 0; 90 } 91 92 int rv370_pcie_gart_init(struct radeon_device *rdev) 93 { 94 int r; 95 96 if (rdev->gart.robj) { 97 WARN(1, "RV370 PCIE GART already initialized\n"); 98 return 0; 99 } 100 /* Initialize common gart structure */ 101 r = radeon_gart_init(rdev); 102 if (r) 103 return r; 104 r = rv370_debugfs_pcie_gart_info_init(rdev); 105 if (r) 106 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 108 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; 109 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; 110 return radeon_gart_table_vram_alloc(rdev); 111 } 112 113 int rv370_pcie_gart_enable(struct radeon_device *rdev) 114 { 115 uint32_t table_addr; 116 uint32_t tmp; 117 int r; 118 119 if (rdev->gart.robj == NULL) { 120 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 121 return -EINVAL; 122 } 123 r = radeon_gart_table_vram_pin(rdev); 124 if (r) 125 return r; 126 radeon_gart_restore(rdev); 127 /* discard memory request outside of configured range */ 128 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 129 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 130 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 131 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 132 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 133 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 134 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 135 table_addr = rdev->gart.table_addr; 136 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 137 /* FIXME: setup default page */ 138 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 139 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 140 /* Clear error */ 141 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 142 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 143 tmp |= RADEON_PCIE_TX_GART_EN; 144 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 145 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 146 rv370_pcie_gart_tlb_flush(rdev); 147 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 148 (unsigned)(rdev->mc.gtt_size >> 20), 149 (unsigned long long)table_addr); 150 rdev->gart.ready = true; 151 return 0; 152 } 153 154 void rv370_pcie_gart_disable(struct radeon_device *rdev) 155 { 156 u32 tmp; 157 158 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 159 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 160 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 162 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 163 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 164 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 165 radeon_gart_table_vram_unpin(rdev); 166 } 167 168 void rv370_pcie_gart_fini(struct radeon_device *rdev) 169 { 170 radeon_gart_fini(rdev); 171 rv370_pcie_gart_disable(rdev); 172 radeon_gart_table_vram_free(rdev); 173 } 174 175 void r300_fence_ring_emit(struct radeon_device *rdev, 176 struct radeon_fence *fence) 177 { 178 /* Who ever call radeon_fence_emit should call ring_lock and ask 179 * for enough space (today caller are ib schedule and buffer move) */ 180 /* Write SC register so SC & US assert idle */ 181 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0)); 182 radeon_ring_write(rdev, 0); 183 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0)); 184 radeon_ring_write(rdev, 0); 185 /* Flush 3D cache */ 186 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 187 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH); 188 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 189 radeon_ring_write(rdev, R300_ZC_FLUSH); 190 /* Wait until IDLE & CLEAN */ 191 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 192 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN | 193 RADEON_WAIT_2D_IDLECLEAN | 194 RADEON_WAIT_DMA_GUI_IDLE)); 195 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 196 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl | 197 RADEON_HDP_READ_BUFFER_INVALIDATE); 198 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 199 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl); 200 /* Emit fence sequence & fire IRQ */ 201 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 202 radeon_ring_write(rdev, fence->seq); 203 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 204 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 205 } 206 207 void r300_ring_start(struct radeon_device *rdev) 208 { 209 unsigned gb_tile_config; 210 int r; 211 212 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 213 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 214 switch(rdev->num_gb_pipes) { 215 case 2: 216 gb_tile_config |= R300_PIPE_COUNT_R300; 217 break; 218 case 3: 219 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 220 break; 221 case 4: 222 gb_tile_config |= R300_PIPE_COUNT_R420; 223 break; 224 case 1: 225 default: 226 gb_tile_config |= R300_PIPE_COUNT_RV350; 227 break; 228 } 229 230 r = radeon_ring_lock(rdev, 64); 231 if (r) { 232 return; 233 } 234 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 235 radeon_ring_write(rdev, 236 RADEON_ISYNC_ANY2D_IDLE3D | 237 RADEON_ISYNC_ANY3D_IDLE2D | 238 RADEON_ISYNC_WAIT_IDLEGUI | 239 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 240 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); 241 radeon_ring_write(rdev, gb_tile_config); 242 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 243 radeon_ring_write(rdev, 244 RADEON_WAIT_2D_IDLECLEAN | 245 RADEON_WAIT_3D_IDLECLEAN); 246 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0)); 247 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG); 248 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); 249 radeon_ring_write(rdev, 0); 250 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); 251 radeon_ring_write(rdev, 0); 252 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 253 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 254 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 255 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 256 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 257 radeon_ring_write(rdev, 258 RADEON_WAIT_2D_IDLECLEAN | 259 RADEON_WAIT_3D_IDLECLEAN); 260 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); 261 radeon_ring_write(rdev, 0); 262 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 263 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 264 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 265 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 266 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); 267 radeon_ring_write(rdev, 268 ((6 << R300_MS_X0_SHIFT) | 269 (6 << R300_MS_Y0_SHIFT) | 270 (6 << R300_MS_X1_SHIFT) | 271 (6 << R300_MS_Y1_SHIFT) | 272 (6 << R300_MS_X2_SHIFT) | 273 (6 << R300_MS_Y2_SHIFT) | 274 (6 << R300_MSBD0_Y_SHIFT) | 275 (6 << R300_MSBD0_X_SHIFT))); 276 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); 277 radeon_ring_write(rdev, 278 ((6 << R300_MS_X3_SHIFT) | 279 (6 << R300_MS_Y3_SHIFT) | 280 (6 << R300_MS_X4_SHIFT) | 281 (6 << R300_MS_Y4_SHIFT) | 282 (6 << R300_MS_X5_SHIFT) | 283 (6 << R300_MS_Y5_SHIFT) | 284 (6 << R300_MSBD1_SHIFT))); 285 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); 286 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 287 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); 288 radeon_ring_write(rdev, 289 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 290 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); 291 radeon_ring_write(rdev, 292 R300_GEOMETRY_ROUND_NEAREST | 293 R300_COLOR_ROUND_NEAREST); 294 radeon_ring_unlock_commit(rdev); 295 } 296 297 void r300_errata(struct radeon_device *rdev) 298 { 299 rdev->pll_errata = 0; 300 301 if (rdev->family == CHIP_R300 && 302 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 303 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 304 } 305 } 306 307 int r300_mc_wait_for_idle(struct radeon_device *rdev) 308 { 309 unsigned i; 310 uint32_t tmp; 311 312 for (i = 0; i < rdev->usec_timeout; i++) { 313 /* read MC_STATUS */ 314 tmp = RREG32(RADEON_MC_STATUS); 315 if (tmp & R300_MC_IDLE) { 316 return 0; 317 } 318 DRM_UDELAY(1); 319 } 320 return -1; 321 } 322 323 void r300_gpu_init(struct radeon_device *rdev) 324 { 325 uint32_t gb_tile_config, tmp; 326 327 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 328 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 329 /* r300,r350 */ 330 rdev->num_gb_pipes = 2; 331 } else { 332 /* rv350,rv370,rv380,r300 AD, r350 AH */ 333 rdev->num_gb_pipes = 1; 334 } 335 rdev->num_z_pipes = 1; 336 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 337 switch (rdev->num_gb_pipes) { 338 case 2: 339 gb_tile_config |= R300_PIPE_COUNT_R300; 340 break; 341 case 3: 342 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 343 break; 344 case 4: 345 gb_tile_config |= R300_PIPE_COUNT_R420; 346 break; 347 default: 348 case 1: 349 gb_tile_config |= R300_PIPE_COUNT_RV350; 350 break; 351 } 352 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 353 354 if (r100_gui_wait_for_idle(rdev)) { 355 printk(KERN_WARNING "Failed to wait GUI idle while " 356 "programming pipes. Bad things might happen.\n"); 357 } 358 359 tmp = RREG32(R300_DST_PIPE_CONFIG); 360 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 361 362 WREG32(R300_RB2D_DSTCACHE_MODE, 363 R300_DC_AUTOFLUSH_ENABLE | 364 R300_DC_DC_DISABLE_IGNORE_PE); 365 366 if (r100_gui_wait_for_idle(rdev)) { 367 printk(KERN_WARNING "Failed to wait GUI idle while " 368 "programming pipes. Bad things might happen.\n"); 369 } 370 if (r300_mc_wait_for_idle(rdev)) { 371 printk(KERN_WARNING "Failed to wait MC idle while " 372 "programming pipes. Bad things might happen.\n"); 373 } 374 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", 375 rdev->num_gb_pipes, rdev->num_z_pipes); 376 } 377 378 bool r300_gpu_is_lockup(struct radeon_device *rdev) 379 { 380 u32 rbbm_status; 381 int r; 382 383 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 384 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 385 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); 386 return false; 387 } 388 /* force CP activities */ 389 r = radeon_ring_lock(rdev, 2); 390 if (!r) { 391 /* PACKET2 NOP */ 392 radeon_ring_write(rdev, 0x80000000); 393 radeon_ring_write(rdev, 0x80000000); 394 radeon_ring_unlock_commit(rdev); 395 } 396 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 397 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); 398 } 399 400 int r300_asic_reset(struct radeon_device *rdev) 401 { 402 struct r100_mc_save save; 403 u32 status, tmp; 404 int ret = 0; 405 406 status = RREG32(R_000E40_RBBM_STATUS); 407 if (!G_000E40_GUI_ACTIVE(status)) { 408 return 0; 409 } 410 r100_mc_stop(rdev, &save); 411 status = RREG32(R_000E40_RBBM_STATUS); 412 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 413 /* stop CP */ 414 WREG32(RADEON_CP_CSQ_CNTL, 0); 415 tmp = RREG32(RADEON_CP_RB_CNTL); 416 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 417 WREG32(RADEON_CP_RB_RPTR_WR, 0); 418 WREG32(RADEON_CP_RB_WPTR, 0); 419 WREG32(RADEON_CP_RB_CNTL, tmp); 420 /* save PCI state */ 421 pci_save_state(rdev->pdev); 422 /* disable bus mastering */ 423 r100_bm_disable(rdev); 424 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 425 S_0000F0_SOFT_RESET_GA(1)); 426 RREG32(R_0000F0_RBBM_SOFT_RESET); 427 mdelay(500); 428 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 429 mdelay(1); 430 status = RREG32(R_000E40_RBBM_STATUS); 431 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 432 /* resetting the CP seems to be problematic sometimes it end up 433 * hard locking the computer, but it's necessary for successful 434 * reset more test & playing is needed on R3XX/R4XX to find a 435 * reliable (if any solution) 436 */ 437 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 438 RREG32(R_0000F0_RBBM_SOFT_RESET); 439 mdelay(500); 440 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 441 mdelay(1); 442 status = RREG32(R_000E40_RBBM_STATUS); 443 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 444 /* restore PCI & busmastering */ 445 pci_restore_state(rdev->pdev); 446 r100_enable_bm(rdev); 447 /* Check if GPU is idle */ 448 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 449 dev_err(rdev->dev, "failed to reset GPU\n"); 450 rdev->gpu_lockup = true; 451 ret = -1; 452 } else 453 dev_info(rdev->dev, "GPU reset succeed\n"); 454 r100_mc_resume(rdev, &save); 455 return ret; 456 } 457 458 /* 459 * r300,r350,rv350,rv380 VRAM info 460 */ 461 void r300_mc_init(struct radeon_device *rdev) 462 { 463 u64 base; 464 u32 tmp; 465 466 /* DDR for all card after R300 & IGP */ 467 rdev->mc.vram_is_ddr = true; 468 tmp = RREG32(RADEON_MEM_CNTL); 469 tmp &= R300_MEM_NUM_CHANNELS_MASK; 470 switch (tmp) { 471 case 0: rdev->mc.vram_width = 64; break; 472 case 1: rdev->mc.vram_width = 128; break; 473 case 2: rdev->mc.vram_width = 256; break; 474 default: rdev->mc.vram_width = 128; break; 475 } 476 r100_vram_init_sizes(rdev); 477 base = rdev->mc.aper_base; 478 if (rdev->flags & RADEON_IS_IGP) 479 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 480 radeon_vram_location(rdev, &rdev->mc, base); 481 rdev->mc.gtt_base_align = 0; 482 if (!(rdev->flags & RADEON_IS_AGP)) 483 radeon_gtt_location(rdev, &rdev->mc); 484 radeon_update_bandwidth_info(rdev); 485 } 486 487 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 488 { 489 uint32_t link_width_cntl, mask; 490 491 if (rdev->flags & RADEON_IS_IGP) 492 return; 493 494 if (!(rdev->flags & RADEON_IS_PCIE)) 495 return; 496 497 /* FIXME wait for idle */ 498 499 switch (lanes) { 500 case 0: 501 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 502 break; 503 case 1: 504 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 505 break; 506 case 2: 507 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 508 break; 509 case 4: 510 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 511 break; 512 case 8: 513 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 514 break; 515 case 12: 516 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 517 break; 518 case 16: 519 default: 520 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 521 break; 522 } 523 524 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 525 526 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 527 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 528 return; 529 530 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 531 RADEON_PCIE_LC_RECONFIG_NOW | 532 RADEON_PCIE_LC_RECONFIG_LATER | 533 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 534 link_width_cntl |= mask; 535 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 536 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 537 RADEON_PCIE_LC_RECONFIG_NOW)); 538 539 /* wait for lane set to complete */ 540 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 541 while (link_width_cntl == 0xffffffff) 542 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 543 544 } 545 546 int rv370_get_pcie_lanes(struct radeon_device *rdev) 547 { 548 u32 link_width_cntl; 549 550 if (rdev->flags & RADEON_IS_IGP) 551 return 0; 552 553 if (!(rdev->flags & RADEON_IS_PCIE)) 554 return 0; 555 556 /* FIXME wait for idle */ 557 558 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 559 560 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 561 case RADEON_PCIE_LC_LINK_WIDTH_X0: 562 return 0; 563 case RADEON_PCIE_LC_LINK_WIDTH_X1: 564 return 1; 565 case RADEON_PCIE_LC_LINK_WIDTH_X2: 566 return 2; 567 case RADEON_PCIE_LC_LINK_WIDTH_X4: 568 return 4; 569 case RADEON_PCIE_LC_LINK_WIDTH_X8: 570 return 8; 571 case RADEON_PCIE_LC_LINK_WIDTH_X16: 572 default: 573 return 16; 574 } 575 } 576 577 #if defined(CONFIG_DEBUG_FS) 578 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 579 { 580 struct drm_info_node *node = (struct drm_info_node *) m->private; 581 struct drm_device *dev = node->minor->dev; 582 struct radeon_device *rdev = dev->dev_private; 583 uint32_t tmp; 584 585 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 586 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 587 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 588 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 589 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 590 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 591 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 592 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 593 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 594 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 596 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 598 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 599 return 0; 600 } 601 602 static struct drm_info_list rv370_pcie_gart_info_list[] = { 603 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 604 }; 605 #endif 606 607 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 608 { 609 #if defined(CONFIG_DEBUG_FS) 610 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 611 #else 612 return 0; 613 #endif 614 } 615 616 static int r300_packet0_check(struct radeon_cs_parser *p, 617 struct radeon_cs_packet *pkt, 618 unsigned idx, unsigned reg) 619 { 620 struct radeon_cs_reloc *reloc; 621 struct r100_cs_track *track; 622 volatile uint32_t *ib; 623 uint32_t tmp, tile_flags = 0; 624 unsigned i; 625 int r; 626 u32 idx_value; 627 628 ib = p->ib->ptr; 629 track = (struct r100_cs_track *)p->track; 630 idx_value = radeon_get_ib_value(p, idx); 631 632 switch(reg) { 633 case AVIVO_D1MODE_VLINE_START_END: 634 case RADEON_CRTC_GUI_TRIG_VLINE: 635 r = r100_cs_packet_parse_vline(p); 636 if (r) { 637 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 638 idx, reg); 639 r100_cs_dump_packet(p, pkt); 640 return r; 641 } 642 break; 643 case RADEON_DST_PITCH_OFFSET: 644 case RADEON_SRC_PITCH_OFFSET: 645 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 646 if (r) 647 return r; 648 break; 649 case R300_RB3D_COLOROFFSET0: 650 case R300_RB3D_COLOROFFSET1: 651 case R300_RB3D_COLOROFFSET2: 652 case R300_RB3D_COLOROFFSET3: 653 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 654 r = r100_cs_packet_next_reloc(p, &reloc); 655 if (r) { 656 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 657 idx, reg); 658 r100_cs_dump_packet(p, pkt); 659 return r; 660 } 661 track->cb[i].robj = reloc->robj; 662 track->cb[i].offset = idx_value; 663 track->cb_dirty = true; 664 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 665 break; 666 case R300_ZB_DEPTHOFFSET: 667 r = r100_cs_packet_next_reloc(p, &reloc); 668 if (r) { 669 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 670 idx, reg); 671 r100_cs_dump_packet(p, pkt); 672 return r; 673 } 674 track->zb.robj = reloc->robj; 675 track->zb.offset = idx_value; 676 track->zb_dirty = true; 677 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 678 break; 679 case R300_TX_OFFSET_0: 680 case R300_TX_OFFSET_0+4: 681 case R300_TX_OFFSET_0+8: 682 case R300_TX_OFFSET_0+12: 683 case R300_TX_OFFSET_0+16: 684 case R300_TX_OFFSET_0+20: 685 case R300_TX_OFFSET_0+24: 686 case R300_TX_OFFSET_0+28: 687 case R300_TX_OFFSET_0+32: 688 case R300_TX_OFFSET_0+36: 689 case R300_TX_OFFSET_0+40: 690 case R300_TX_OFFSET_0+44: 691 case R300_TX_OFFSET_0+48: 692 case R300_TX_OFFSET_0+52: 693 case R300_TX_OFFSET_0+56: 694 case R300_TX_OFFSET_0+60: 695 i = (reg - R300_TX_OFFSET_0) >> 2; 696 r = r100_cs_packet_next_reloc(p, &reloc); 697 if (r) { 698 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 699 idx, reg); 700 r100_cs_dump_packet(p, pkt); 701 return r; 702 } 703 704 if (p->keep_tiling_flags) { 705 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 706 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); 707 } else { 708 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 709 tile_flags |= R300_TXO_MACRO_TILE; 710 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 711 tile_flags |= R300_TXO_MICRO_TILE; 712 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 713 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 714 715 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); 716 tmp |= tile_flags; 717 ib[idx] = tmp; 718 } 719 track->textures[i].robj = reloc->robj; 720 track->tex_dirty = true; 721 break; 722 /* Tracked registers */ 723 case 0x2084: 724 /* VAP_VF_CNTL */ 725 track->vap_vf_cntl = idx_value; 726 break; 727 case 0x20B4: 728 /* VAP_VTX_SIZE */ 729 track->vtx_size = idx_value & 0x7F; 730 break; 731 case 0x2134: 732 /* VAP_VF_MAX_VTX_INDX */ 733 track->max_indx = idx_value & 0x00FFFFFFUL; 734 break; 735 case 0x2088: 736 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 737 if (p->rdev->family < CHIP_RV515) 738 goto fail; 739 track->vap_alt_nverts = idx_value & 0xFFFFFF; 740 break; 741 case 0x43E4: 742 /* SC_SCISSOR1 */ 743 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 744 if (p->rdev->family < CHIP_RV515) { 745 track->maxy -= 1440; 746 } 747 track->cb_dirty = true; 748 track->zb_dirty = true; 749 break; 750 case 0x4E00: 751 /* RB3D_CCTL */ 752 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 753 p->rdev->cmask_filp != p->filp) { 754 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 755 return -EINVAL; 756 } 757 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 758 track->cb_dirty = true; 759 break; 760 case 0x4E38: 761 case 0x4E3C: 762 case 0x4E40: 763 case 0x4E44: 764 /* RB3D_COLORPITCH0 */ 765 /* RB3D_COLORPITCH1 */ 766 /* RB3D_COLORPITCH2 */ 767 /* RB3D_COLORPITCH3 */ 768 if (!p->keep_tiling_flags) { 769 r = r100_cs_packet_next_reloc(p, &reloc); 770 if (r) { 771 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 772 idx, reg); 773 r100_cs_dump_packet(p, pkt); 774 return r; 775 } 776 777 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 778 tile_flags |= R300_COLOR_TILE_ENABLE; 779 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 780 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 781 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 782 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 783 784 tmp = idx_value & ~(0x7 << 16); 785 tmp |= tile_flags; 786 ib[idx] = tmp; 787 } 788 i = (reg - 0x4E38) >> 2; 789 track->cb[i].pitch = idx_value & 0x3FFE; 790 switch (((idx_value >> 21) & 0xF)) { 791 case 9: 792 case 11: 793 case 12: 794 track->cb[i].cpp = 1; 795 break; 796 case 3: 797 case 4: 798 case 13: 799 case 15: 800 track->cb[i].cpp = 2; 801 break; 802 case 5: 803 if (p->rdev->family < CHIP_RV515) { 804 DRM_ERROR("Invalid color buffer format (%d)!\n", 805 ((idx_value >> 21) & 0xF)); 806 return -EINVAL; 807 } 808 /* Pass through. */ 809 case 6: 810 track->cb[i].cpp = 4; 811 break; 812 case 10: 813 track->cb[i].cpp = 8; 814 break; 815 case 7: 816 track->cb[i].cpp = 16; 817 break; 818 default: 819 DRM_ERROR("Invalid color buffer format (%d) !\n", 820 ((idx_value >> 21) & 0xF)); 821 return -EINVAL; 822 } 823 track->cb_dirty = true; 824 break; 825 case 0x4F00: 826 /* ZB_CNTL */ 827 if (idx_value & 2) { 828 track->z_enabled = true; 829 } else { 830 track->z_enabled = false; 831 } 832 track->zb_dirty = true; 833 break; 834 case 0x4F10: 835 /* ZB_FORMAT */ 836 switch ((idx_value & 0xF)) { 837 case 0: 838 case 1: 839 track->zb.cpp = 2; 840 break; 841 case 2: 842 track->zb.cpp = 4; 843 break; 844 default: 845 DRM_ERROR("Invalid z buffer format (%d) !\n", 846 (idx_value & 0xF)); 847 return -EINVAL; 848 } 849 track->zb_dirty = true; 850 break; 851 case 0x4F24: 852 /* ZB_DEPTHPITCH */ 853 if (!p->keep_tiling_flags) { 854 r = r100_cs_packet_next_reloc(p, &reloc); 855 if (r) { 856 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 857 idx, reg); 858 r100_cs_dump_packet(p, pkt); 859 return r; 860 } 861 862 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 863 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 864 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 865 tile_flags |= R300_DEPTHMICROTILE_TILED; 866 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 867 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 868 869 tmp = idx_value & ~(0x7 << 16); 870 tmp |= tile_flags; 871 ib[idx] = tmp; 872 } 873 track->zb.pitch = idx_value & 0x3FFC; 874 track->zb_dirty = true; 875 break; 876 case 0x4104: 877 /* TX_ENABLE */ 878 for (i = 0; i < 16; i++) { 879 bool enabled; 880 881 enabled = !!(idx_value & (1 << i)); 882 track->textures[i].enabled = enabled; 883 } 884 track->tex_dirty = true; 885 break; 886 case 0x44C0: 887 case 0x44C4: 888 case 0x44C8: 889 case 0x44CC: 890 case 0x44D0: 891 case 0x44D4: 892 case 0x44D8: 893 case 0x44DC: 894 case 0x44E0: 895 case 0x44E4: 896 case 0x44E8: 897 case 0x44EC: 898 case 0x44F0: 899 case 0x44F4: 900 case 0x44F8: 901 case 0x44FC: 902 /* TX_FORMAT1_[0-15] */ 903 i = (reg - 0x44C0) >> 2; 904 tmp = (idx_value >> 25) & 0x3; 905 track->textures[i].tex_coord_type = tmp; 906 switch ((idx_value & 0x1F)) { 907 case R300_TX_FORMAT_X8: 908 case R300_TX_FORMAT_Y4X4: 909 case R300_TX_FORMAT_Z3Y3X2: 910 track->textures[i].cpp = 1; 911 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 912 break; 913 case R300_TX_FORMAT_X16: 914 case R300_TX_FORMAT_FL_I16: 915 case R300_TX_FORMAT_Y8X8: 916 case R300_TX_FORMAT_Z5Y6X5: 917 case R300_TX_FORMAT_Z6Y5X5: 918 case R300_TX_FORMAT_W4Z4Y4X4: 919 case R300_TX_FORMAT_W1Z5Y5X5: 920 case R300_TX_FORMAT_D3DMFT_CxV8U8: 921 case R300_TX_FORMAT_B8G8_B8G8: 922 case R300_TX_FORMAT_G8R8_G8B8: 923 track->textures[i].cpp = 2; 924 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 925 break; 926 case R300_TX_FORMAT_Y16X16: 927 case R300_TX_FORMAT_FL_I16A16: 928 case R300_TX_FORMAT_Z11Y11X10: 929 case R300_TX_FORMAT_Z10Y11X11: 930 case R300_TX_FORMAT_W8Z8Y8X8: 931 case R300_TX_FORMAT_W2Z10Y10X10: 932 case 0x17: 933 case R300_TX_FORMAT_FL_I32: 934 case 0x1e: 935 track->textures[i].cpp = 4; 936 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 937 break; 938 case R300_TX_FORMAT_W16Z16Y16X16: 939 case R300_TX_FORMAT_FL_R16G16B16A16: 940 case R300_TX_FORMAT_FL_I32A32: 941 track->textures[i].cpp = 8; 942 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 943 break; 944 case R300_TX_FORMAT_FL_R32G32B32A32: 945 track->textures[i].cpp = 16; 946 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 947 break; 948 case R300_TX_FORMAT_DXT1: 949 track->textures[i].cpp = 1; 950 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 951 break; 952 case R300_TX_FORMAT_ATI2N: 953 if (p->rdev->family < CHIP_R420) { 954 DRM_ERROR("Invalid texture format %u\n", 955 (idx_value & 0x1F)); 956 return -EINVAL; 957 } 958 /* The same rules apply as for DXT3/5. */ 959 /* Pass through. */ 960 case R300_TX_FORMAT_DXT3: 961 case R300_TX_FORMAT_DXT5: 962 track->textures[i].cpp = 1; 963 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 964 break; 965 default: 966 DRM_ERROR("Invalid texture format %u\n", 967 (idx_value & 0x1F)); 968 return -EINVAL; 969 } 970 track->tex_dirty = true; 971 break; 972 case 0x4400: 973 case 0x4404: 974 case 0x4408: 975 case 0x440C: 976 case 0x4410: 977 case 0x4414: 978 case 0x4418: 979 case 0x441C: 980 case 0x4420: 981 case 0x4424: 982 case 0x4428: 983 case 0x442C: 984 case 0x4430: 985 case 0x4434: 986 case 0x4438: 987 case 0x443C: 988 /* TX_FILTER0_[0-15] */ 989 i = (reg - 0x4400) >> 2; 990 tmp = idx_value & 0x7; 991 if (tmp == 2 || tmp == 4 || tmp == 6) { 992 track->textures[i].roundup_w = false; 993 } 994 tmp = (idx_value >> 3) & 0x7; 995 if (tmp == 2 || tmp == 4 || tmp == 6) { 996 track->textures[i].roundup_h = false; 997 } 998 track->tex_dirty = true; 999 break; 1000 case 0x4500: 1001 case 0x4504: 1002 case 0x4508: 1003 case 0x450C: 1004 case 0x4510: 1005 case 0x4514: 1006 case 0x4518: 1007 case 0x451C: 1008 case 0x4520: 1009 case 0x4524: 1010 case 0x4528: 1011 case 0x452C: 1012 case 0x4530: 1013 case 0x4534: 1014 case 0x4538: 1015 case 0x453C: 1016 /* TX_FORMAT2_[0-15] */ 1017 i = (reg - 0x4500) >> 2; 1018 tmp = idx_value & 0x3FFF; 1019 track->textures[i].pitch = tmp + 1; 1020 if (p->rdev->family >= CHIP_RV515) { 1021 tmp = ((idx_value >> 15) & 1) << 11; 1022 track->textures[i].width_11 = tmp; 1023 tmp = ((idx_value >> 16) & 1) << 11; 1024 track->textures[i].height_11 = tmp; 1025 1026 /* ATI1N */ 1027 if (idx_value & (1 << 14)) { 1028 /* The same rules apply as for DXT1. */ 1029 track->textures[i].compress_format = 1030 R100_TRACK_COMP_DXT1; 1031 } 1032 } else if (idx_value & (1 << 14)) { 1033 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1034 return -EINVAL; 1035 } 1036 track->tex_dirty = true; 1037 break; 1038 case 0x4480: 1039 case 0x4484: 1040 case 0x4488: 1041 case 0x448C: 1042 case 0x4490: 1043 case 0x4494: 1044 case 0x4498: 1045 case 0x449C: 1046 case 0x44A0: 1047 case 0x44A4: 1048 case 0x44A8: 1049 case 0x44AC: 1050 case 0x44B0: 1051 case 0x44B4: 1052 case 0x44B8: 1053 case 0x44BC: 1054 /* TX_FORMAT0_[0-15] */ 1055 i = (reg - 0x4480) >> 2; 1056 tmp = idx_value & 0x7FF; 1057 track->textures[i].width = tmp + 1; 1058 tmp = (idx_value >> 11) & 0x7FF; 1059 track->textures[i].height = tmp + 1; 1060 tmp = (idx_value >> 26) & 0xF; 1061 track->textures[i].num_levels = tmp; 1062 tmp = idx_value & (1 << 31); 1063 track->textures[i].use_pitch = !!tmp; 1064 tmp = (idx_value >> 22) & 0xF; 1065 track->textures[i].txdepth = tmp; 1066 track->tex_dirty = true; 1067 break; 1068 case R300_ZB_ZPASS_ADDR: 1069 r = r100_cs_packet_next_reloc(p, &reloc); 1070 if (r) { 1071 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1072 idx, reg); 1073 r100_cs_dump_packet(p, pkt); 1074 return r; 1075 } 1076 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1077 break; 1078 case 0x4e0c: 1079 /* RB3D_COLOR_CHANNEL_MASK */ 1080 track->color_channel_mask = idx_value; 1081 track->cb_dirty = true; 1082 break; 1083 case 0x43a4: 1084 /* SC_HYPERZ_EN */ 1085 /* r300c emits this register - we need to disable hyperz for it 1086 * without complaining */ 1087 if (p->rdev->hyperz_filp != p->filp) { 1088 if (idx_value & 0x1) 1089 ib[idx] = idx_value & ~1; 1090 } 1091 break; 1092 case 0x4f1c: 1093 /* ZB_BW_CNTL */ 1094 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1095 track->cb_dirty = true; 1096 track->zb_dirty = true; 1097 if (p->rdev->hyperz_filp != p->filp) { 1098 if (idx_value & (R300_HIZ_ENABLE | 1099 R300_RD_COMP_ENABLE | 1100 R300_WR_COMP_ENABLE | 1101 R300_FAST_FILL_ENABLE)) 1102 goto fail; 1103 } 1104 break; 1105 case 0x4e04: 1106 /* RB3D_BLENDCNTL */ 1107 track->blend_read_enable = !!(idx_value & (1 << 2)); 1108 track->cb_dirty = true; 1109 break; 1110 case R300_RB3D_AARESOLVE_OFFSET: 1111 r = r100_cs_packet_next_reloc(p, &reloc); 1112 if (r) { 1113 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1114 idx, reg); 1115 r100_cs_dump_packet(p, pkt); 1116 return r; 1117 } 1118 track->aa.robj = reloc->robj; 1119 track->aa.offset = idx_value; 1120 track->aa_dirty = true; 1121 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1122 break; 1123 case R300_RB3D_AARESOLVE_PITCH: 1124 track->aa.pitch = idx_value & 0x3FFE; 1125 track->aa_dirty = true; 1126 break; 1127 case R300_RB3D_AARESOLVE_CTL: 1128 track->aaresolve = idx_value & 0x1; 1129 track->aa_dirty = true; 1130 break; 1131 case 0x4f30: /* ZB_MASK_OFFSET */ 1132 case 0x4f34: /* ZB_ZMASK_PITCH */ 1133 case 0x4f44: /* ZB_HIZ_OFFSET */ 1134 case 0x4f54: /* ZB_HIZ_PITCH */ 1135 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1136 goto fail; 1137 break; 1138 case 0x4028: 1139 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1140 goto fail; 1141 /* GB_Z_PEQ_CONFIG */ 1142 if (p->rdev->family >= CHIP_RV350) 1143 break; 1144 goto fail; 1145 break; 1146 case 0x4be8: 1147 /* valid register only on RV530 */ 1148 if (p->rdev->family == CHIP_RV530) 1149 break; 1150 /* fallthrough do not move */ 1151 default: 1152 goto fail; 1153 } 1154 return 0; 1155 fail: 1156 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1157 reg, idx, idx_value); 1158 return -EINVAL; 1159 } 1160 1161 static int r300_packet3_check(struct radeon_cs_parser *p, 1162 struct radeon_cs_packet *pkt) 1163 { 1164 struct radeon_cs_reloc *reloc; 1165 struct r100_cs_track *track; 1166 volatile uint32_t *ib; 1167 unsigned idx; 1168 int r; 1169 1170 ib = p->ib->ptr; 1171 idx = pkt->idx + 1; 1172 track = (struct r100_cs_track *)p->track; 1173 switch(pkt->opcode) { 1174 case PACKET3_3D_LOAD_VBPNTR: 1175 r = r100_packet3_load_vbpntr(p, pkt, idx); 1176 if (r) 1177 return r; 1178 break; 1179 case PACKET3_INDX_BUFFER: 1180 r = r100_cs_packet_next_reloc(p, &reloc); 1181 if (r) { 1182 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1183 r100_cs_dump_packet(p, pkt); 1184 return r; 1185 } 1186 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1187 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1188 if (r) { 1189 return r; 1190 } 1191 break; 1192 /* Draw packet */ 1193 case PACKET3_3D_DRAW_IMMD: 1194 /* Number of dwords is vtx_size * (num_vertices - 1) 1195 * PRIM_WALK must be equal to 3 vertex data in embedded 1196 * in cmd stream */ 1197 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1198 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1199 return -EINVAL; 1200 } 1201 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1202 track->immd_dwords = pkt->count - 1; 1203 r = r100_cs_track_check(p->rdev, track); 1204 if (r) { 1205 return r; 1206 } 1207 break; 1208 case PACKET3_3D_DRAW_IMMD_2: 1209 /* Number of dwords is vtx_size * (num_vertices - 1) 1210 * PRIM_WALK must be equal to 3 vertex data in embedded 1211 * in cmd stream */ 1212 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1213 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1214 return -EINVAL; 1215 } 1216 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1217 track->immd_dwords = pkt->count; 1218 r = r100_cs_track_check(p->rdev, track); 1219 if (r) { 1220 return r; 1221 } 1222 break; 1223 case PACKET3_3D_DRAW_VBUF: 1224 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1225 r = r100_cs_track_check(p->rdev, track); 1226 if (r) { 1227 return r; 1228 } 1229 break; 1230 case PACKET3_3D_DRAW_VBUF_2: 1231 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1232 r = r100_cs_track_check(p->rdev, track); 1233 if (r) { 1234 return r; 1235 } 1236 break; 1237 case PACKET3_3D_DRAW_INDX: 1238 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1239 r = r100_cs_track_check(p->rdev, track); 1240 if (r) { 1241 return r; 1242 } 1243 break; 1244 case PACKET3_3D_DRAW_INDX_2: 1245 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1246 r = r100_cs_track_check(p->rdev, track); 1247 if (r) { 1248 return r; 1249 } 1250 break; 1251 case PACKET3_3D_CLEAR_HIZ: 1252 case PACKET3_3D_CLEAR_ZMASK: 1253 if (p->rdev->hyperz_filp != p->filp) 1254 return -EINVAL; 1255 break; 1256 case PACKET3_3D_CLEAR_CMASK: 1257 if (p->rdev->cmask_filp != p->filp) 1258 return -EINVAL; 1259 break; 1260 case PACKET3_NOP: 1261 break; 1262 default: 1263 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1264 return -EINVAL; 1265 } 1266 return 0; 1267 } 1268 1269 int r300_cs_parse(struct radeon_cs_parser *p) 1270 { 1271 struct radeon_cs_packet pkt; 1272 struct r100_cs_track *track; 1273 int r; 1274 1275 track = kzalloc(sizeof(*track), GFP_KERNEL); 1276 if (track == NULL) 1277 return -ENOMEM; 1278 r100_cs_track_clear(p->rdev, track); 1279 p->track = track; 1280 do { 1281 r = r100_cs_packet_parse(p, &pkt, p->idx); 1282 if (r) { 1283 return r; 1284 } 1285 p->idx += pkt.count + 2; 1286 switch (pkt.type) { 1287 case PACKET_TYPE0: 1288 r = r100_cs_parse_packet0(p, &pkt, 1289 p->rdev->config.r300.reg_safe_bm, 1290 p->rdev->config.r300.reg_safe_bm_size, 1291 &r300_packet0_check); 1292 break; 1293 case PACKET_TYPE2: 1294 break; 1295 case PACKET_TYPE3: 1296 r = r300_packet3_check(p, &pkt); 1297 break; 1298 default: 1299 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1300 return -EINVAL; 1301 } 1302 if (r) { 1303 return r; 1304 } 1305 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1306 return 0; 1307 } 1308 1309 void r300_set_reg_safe(struct radeon_device *rdev) 1310 { 1311 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1312 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1313 } 1314 1315 void r300_mc_program(struct radeon_device *rdev) 1316 { 1317 struct r100_mc_save save; 1318 int r; 1319 1320 r = r100_debugfs_mc_info_init(rdev); 1321 if (r) { 1322 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1323 } 1324 1325 /* Stops all mc clients */ 1326 r100_mc_stop(rdev, &save); 1327 if (rdev->flags & RADEON_IS_AGP) { 1328 WREG32(R_00014C_MC_AGP_LOCATION, 1329 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1330 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1331 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1332 WREG32(R_00015C_AGP_BASE_2, 1333 upper_32_bits(rdev->mc.agp_base) & 0xff); 1334 } else { 1335 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1336 WREG32(R_000170_AGP_BASE, 0); 1337 WREG32(R_00015C_AGP_BASE_2, 0); 1338 } 1339 /* Wait for mc idle */ 1340 if (r300_mc_wait_for_idle(rdev)) 1341 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1342 /* Program MC, should be a 32bits limited address space */ 1343 WREG32(R_000148_MC_FB_LOCATION, 1344 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1345 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1346 r100_mc_resume(rdev, &save); 1347 } 1348 1349 void r300_clock_startup(struct radeon_device *rdev) 1350 { 1351 u32 tmp; 1352 1353 if (radeon_dynclks != -1 && radeon_dynclks) 1354 radeon_legacy_set_clock_gating(rdev, 1); 1355 /* We need to force on some of the block */ 1356 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1357 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1358 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1359 tmp |= S_00000D_FORCE_VAP(1); 1360 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1361 } 1362 1363 static int r300_startup(struct radeon_device *rdev) 1364 { 1365 int r; 1366 1367 /* set common regs */ 1368 r100_set_common_regs(rdev); 1369 /* program mc */ 1370 r300_mc_program(rdev); 1371 /* Resume clock */ 1372 r300_clock_startup(rdev); 1373 /* Initialize GPU configuration (# pipes, ...) */ 1374 r300_gpu_init(rdev); 1375 /* Initialize GART (initialize after TTM so we can allocate 1376 * memory through TTM but finalize after TTM) */ 1377 if (rdev->flags & RADEON_IS_PCIE) { 1378 r = rv370_pcie_gart_enable(rdev); 1379 if (r) 1380 return r; 1381 } 1382 1383 if (rdev->family == CHIP_R300 || 1384 rdev->family == CHIP_R350 || 1385 rdev->family == CHIP_RV350) 1386 r100_enable_bm(rdev); 1387 1388 if (rdev->flags & RADEON_IS_PCI) { 1389 r = r100_pci_gart_enable(rdev); 1390 if (r) 1391 return r; 1392 } 1393 1394 /* allocate wb buffer */ 1395 r = radeon_wb_init(rdev); 1396 if (r) 1397 return r; 1398 1399 /* Enable IRQ */ 1400 r100_irq_set(rdev); 1401 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1402 /* 1M ring buffer */ 1403 r = r100_cp_init(rdev, 1024 * 1024); 1404 if (r) { 1405 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1406 return r; 1407 } 1408 r = r100_ib_init(rdev); 1409 if (r) { 1410 dev_err(rdev->dev, "failed initializing IB (%d).\n", r); 1411 return r; 1412 } 1413 return 0; 1414 } 1415 1416 int r300_resume(struct radeon_device *rdev) 1417 { 1418 /* Make sur GART are not working */ 1419 if (rdev->flags & RADEON_IS_PCIE) 1420 rv370_pcie_gart_disable(rdev); 1421 if (rdev->flags & RADEON_IS_PCI) 1422 r100_pci_gart_disable(rdev); 1423 /* Resume clock before doing reset */ 1424 r300_clock_startup(rdev); 1425 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1426 if (radeon_asic_reset(rdev)) { 1427 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1428 RREG32(R_000E40_RBBM_STATUS), 1429 RREG32(R_0007C0_CP_STAT)); 1430 } 1431 /* post */ 1432 radeon_combios_asic_init(rdev->ddev); 1433 /* Resume clock after posting */ 1434 r300_clock_startup(rdev); 1435 /* Initialize surface registers */ 1436 radeon_surface_init(rdev); 1437 return r300_startup(rdev); 1438 } 1439 1440 int r300_suspend(struct radeon_device *rdev) 1441 { 1442 r100_cp_disable(rdev); 1443 radeon_wb_disable(rdev); 1444 r100_irq_disable(rdev); 1445 if (rdev->flags & RADEON_IS_PCIE) 1446 rv370_pcie_gart_disable(rdev); 1447 if (rdev->flags & RADEON_IS_PCI) 1448 r100_pci_gart_disable(rdev); 1449 return 0; 1450 } 1451 1452 void r300_fini(struct radeon_device *rdev) 1453 { 1454 r100_cp_fini(rdev); 1455 radeon_wb_fini(rdev); 1456 r100_ib_fini(rdev); 1457 radeon_gem_fini(rdev); 1458 if (rdev->flags & RADEON_IS_PCIE) 1459 rv370_pcie_gart_fini(rdev); 1460 if (rdev->flags & RADEON_IS_PCI) 1461 r100_pci_gart_fini(rdev); 1462 radeon_agp_fini(rdev); 1463 radeon_irq_kms_fini(rdev); 1464 radeon_fence_driver_fini(rdev); 1465 radeon_bo_fini(rdev); 1466 radeon_atombios_fini(rdev); 1467 kfree(rdev->bios); 1468 rdev->bios = NULL; 1469 } 1470 1471 int r300_init(struct radeon_device *rdev) 1472 { 1473 int r; 1474 1475 /* Disable VGA */ 1476 r100_vga_render_disable(rdev); 1477 /* Initialize scratch registers */ 1478 radeon_scratch_init(rdev); 1479 /* Initialize surface registers */ 1480 radeon_surface_init(rdev); 1481 /* TODO: disable VGA need to use VGA request */ 1482 /* restore some register to sane defaults */ 1483 r100_restore_sanity(rdev); 1484 /* BIOS*/ 1485 if (!radeon_get_bios(rdev)) { 1486 if (ASIC_IS_AVIVO(rdev)) 1487 return -EINVAL; 1488 } 1489 if (rdev->is_atom_bios) { 1490 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1491 return -EINVAL; 1492 } else { 1493 r = radeon_combios_init(rdev); 1494 if (r) 1495 return r; 1496 } 1497 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1498 if (radeon_asic_reset(rdev)) { 1499 dev_warn(rdev->dev, 1500 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1501 RREG32(R_000E40_RBBM_STATUS), 1502 RREG32(R_0007C0_CP_STAT)); 1503 } 1504 /* check if cards are posted or not */ 1505 if (radeon_boot_test_post_card(rdev) == false) 1506 return -EINVAL; 1507 /* Set asic errata */ 1508 r300_errata(rdev); 1509 /* Initialize clocks */ 1510 radeon_get_clock_info(rdev->ddev); 1511 /* initialize AGP */ 1512 if (rdev->flags & RADEON_IS_AGP) { 1513 r = radeon_agp_init(rdev); 1514 if (r) { 1515 radeon_agp_disable(rdev); 1516 } 1517 } 1518 /* initialize memory controller */ 1519 r300_mc_init(rdev); 1520 /* Fence driver */ 1521 r = radeon_fence_driver_init(rdev); 1522 if (r) 1523 return r; 1524 r = radeon_irq_kms_init(rdev); 1525 if (r) 1526 return r; 1527 /* Memory manager */ 1528 r = radeon_bo_init(rdev); 1529 if (r) 1530 return r; 1531 if (rdev->flags & RADEON_IS_PCIE) { 1532 r = rv370_pcie_gart_init(rdev); 1533 if (r) 1534 return r; 1535 } 1536 if (rdev->flags & RADEON_IS_PCI) { 1537 r = r100_pci_gart_init(rdev); 1538 if (r) 1539 return r; 1540 } 1541 r300_set_reg_safe(rdev); 1542 rdev->accel_working = true; 1543 r = r300_startup(rdev); 1544 if (r) { 1545 /* Somethings want wront with the accel init stop accel */ 1546 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1547 r100_cp_fini(rdev); 1548 radeon_wb_fini(rdev); 1549 r100_ib_fini(rdev); 1550 radeon_irq_kms_fini(rdev); 1551 if (rdev->flags & RADEON_IS_PCIE) 1552 rv370_pcie_gart_fini(rdev); 1553 if (rdev->flags & RADEON_IS_PCI) 1554 r100_pci_gart_fini(rdev); 1555 radeon_agp_fini(rdev); 1556 rdev->accel_working = false; 1557 } 1558 return 0; 1559 } 1560