tc358767.c (5761a259aa9efc61b3253675643a87b3092e90b5) tc358767.c (80d57245063f8cb133a50943a021a8789460101e)
1/*
2 * tc358767 eDP bridge driver
3 *
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
6 *
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
8 *

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1009 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1010 return ret;
1011err_dpcd_write:
1012 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1013err:
1014 return ret;
1015}
1016
1/*
2 * tc358767 eDP bridge driver
3 *
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
6 *
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
8 *

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1009 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1010 return ret;
1011err_dpcd_write:
1012 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1013err:
1014 return ret;
1015}
1016
1017static int tc_main_link_stream(struct tc_data *tc, int state)
1017static int tc_stream_enable(struct tc_data *tc)
1018{
1019 int ret;
1020 u32 value;
1021
1018{
1019 int ret;
1020 u32 value;
1021
1022 dev_dbg(tc->dev, "stream: %d\n", state);
1022 dev_dbg(tc->dev, "enable video stream\n");
1023
1023
1024 if (state) {
1025 ret = tc_set_video_mode(tc, tc->mode);
1026 if (ret)
1027 goto err;
1024 ret = tc_set_video_mode(tc, tc->mode);
1025 if (ret)
1026 return ret;
1028
1027
1029 /* Set M/N */
1030 ret = tc_stream_clock_calc(tc);
1031 if (ret)
1032 goto err;
1028 /* Set M/N */
1029 ret = tc_stream_clock_calc(tc);
1030 if (ret)
1031 return ret;
1033
1032
1034 value = VID_MN_GEN | DP_EN;
1035 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1036 value |= EF_EN;
1037 tc_write(DP0CTL, value);
1038 /*
1039 * VID_EN assertion should be delayed by at least N * LSCLK
1040 * cycles from the time VID_MN_GEN is enabled in order to
1041 * generate stable values for VID_M. LSCLK is 270 MHz or
1042 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1043 * so a delay of at least 203 us should suffice.
1044 */
1045 usleep_range(500, 1000);
1046 value |= VID_EN;
1047 tc_write(DP0CTL, value);
1048 /* Set input interface */
1049 value = DP0_AUDSRC_NO_INPUT;
1050 if (tc_test_pattern)
1051 value |= DP0_VIDSRC_COLOR_BAR;
1052 else
1053 value |= DP0_VIDSRC_DPI_RX;
1054 tc_write(SYSCTRL, value);
1055 } else {
1056 tc_write(DP0CTL, 0);
1057 }
1033 value = VID_MN_GEN | DP_EN;
1034 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1035 value |= EF_EN;
1036 tc_write(DP0CTL, value);
1037 /*
1038 * VID_EN assertion should be delayed by at least N * LSCLK
1039 * cycles from the time VID_MN_GEN is enabled in order to
1040 * generate stable values for VID_M. LSCLK is 270 MHz or
1041 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1042 * so a delay of at least 203 us should suffice.
1043 */
1044 usleep_range(500, 1000);
1045 value |= VID_EN;
1046 tc_write(DP0CTL, value);
1047 /* Set input interface */
1048 value = DP0_AUDSRC_NO_INPUT;
1049 if (tc_test_pattern)
1050 value |= DP0_VIDSRC_COLOR_BAR;
1051 else
1052 value |= DP0_VIDSRC_DPI_RX;
1053 tc_write(SYSCTRL, value);
1058
1059 return 0;
1060err:
1061 return ret;
1062}
1063
1054
1055 return 0;
1056err:
1057 return ret;
1058}
1059
1060static int tc_stream_disable(struct tc_data *tc)
1061{
1062 int ret;
1063
1064 dev_dbg(tc->dev, "disable video stream\n");
1065
1066 tc_write(DP0CTL, 0);
1067
1068 return 0;
1069err:
1070 return ret;
1071}
1072
1064static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1065{
1066 struct tc_data *tc = bridge_to_tc(bridge);
1067
1068 drm_panel_prepare(tc->panel);
1069}
1070
1071static void tc_bridge_enable(struct drm_bridge *bridge)
1072{
1073 struct tc_data *tc = bridge_to_tc(bridge);
1074 int ret;
1075
1076 ret = tc_main_link_setup(tc);
1077 if (ret < 0) {
1078 dev_err(tc->dev, "main link setup error: %d\n", ret);
1079 return;
1080 }
1081
1073static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1074{
1075 struct tc_data *tc = bridge_to_tc(bridge);
1076
1077 drm_panel_prepare(tc->panel);
1078}
1079
1080static void tc_bridge_enable(struct drm_bridge *bridge)
1081{
1082 struct tc_data *tc = bridge_to_tc(bridge);
1083 int ret;
1084
1085 ret = tc_main_link_setup(tc);
1086 if (ret < 0) {
1087 dev_err(tc->dev, "main link setup error: %d\n", ret);
1088 return;
1089 }
1090
1082 ret = tc_main_link_stream(tc, 1);
1091 ret = tc_stream_enable(tc);
1083 if (ret < 0) {
1084 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1085 return;
1086 }
1087
1088 drm_panel_enable(tc->panel);
1089}
1090
1091static void tc_bridge_disable(struct drm_bridge *bridge)
1092{
1093 struct tc_data *tc = bridge_to_tc(bridge);
1094 int ret;
1095
1096 drm_panel_disable(tc->panel);
1097
1092 if (ret < 0) {
1093 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1094 return;
1095 }
1096
1097 drm_panel_enable(tc->panel);
1098}
1099
1100static void tc_bridge_disable(struct drm_bridge *bridge)
1101{
1102 struct tc_data *tc = bridge_to_tc(bridge);
1103 int ret;
1104
1105 drm_panel_disable(tc->panel);
1106
1098 ret = tc_main_link_stream(tc, 0);
1107 ret = tc_stream_disable(tc);
1099 if (ret < 0)
1100 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1101}
1102
1103static void tc_bridge_post_disable(struct drm_bridge *bridge)
1104{
1105 struct tc_data *tc = bridge_to_tc(bridge);
1106

--- 309 unchanged lines hidden --- 		1108 if (ret < 0)
1109 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1110}
1111
1112static void tc_bridge_post_disable(struct drm_bridge *bridge)
1113{
1114 struct tc_data *tc = bridge_to_tc(bridge);
1115

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