1 /* 2 * tc358767 eDP bridge driver 3 * 4 * Copyright (C) 2016 CogentEmbedded Inc 5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com> 6 * 7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 8 * 9 * Copyright (C) 2016 Zodiac Inflight Innovations 10 * 11 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c 12 * 13 * Copyright (C) 2012 Texas Instruments 14 * Author: Rob Clark <robdclark@gmail.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 */ 26 27 #include <linux/clk.h> 28 #include <linux/device.h> 29 #include <linux/gpio/consumer.h> 30 #include <linux/i2c.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/regmap.h> 34 #include <linux/slab.h> 35 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_of.h> 40 #include <drm/drm_panel.h> 41 #include <drm/drm_probe_helper.h> 42 43 /* Registers */ 44 45 /* Display Parallel Interface */ 46 #define DPIPXLFMT 0x0440 47 #define VS_POL_ACTIVE_LOW (1 << 10) 48 #define HS_POL_ACTIVE_LOW (1 << 9) 49 #define DE_POL_ACTIVE_HIGH (0 << 8) 50 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */ 51 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */ 52 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */ 53 #define DPI_BPP_RGB888 (0 << 0) 54 #define DPI_BPP_RGB666 (1 << 0) 55 #define DPI_BPP_RGB565 (2 << 0) 56 57 /* Video Path */ 58 #define VPCTRL0 0x0450 59 #define OPXLFMT_RGB666 (0 << 8) 60 #define OPXLFMT_RGB888 (1 << 8) 61 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ 62 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */ 63 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ 64 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ 65 #define HTIM01 0x0454 66 #define HTIM02 0x0458 67 #define VTIM01 0x045c 68 #define VTIM02 0x0460 69 #define VFUEN0 0x0464 70 #define VFUEN BIT(0) /* Video Frame Timing Upload */ 71 72 /* System */ 73 #define TC_IDREG 0x0500 74 #define SYSCTRL 0x0510 75 #define DP0_AUDSRC_NO_INPUT (0 << 3) 76 #define DP0_AUDSRC_I2S_RX (1 << 3) 77 #define DP0_VIDSRC_NO_INPUT (0 << 0) 78 #define DP0_VIDSRC_DSI_RX (1 << 0) 79 #define DP0_VIDSRC_DPI_RX (2 << 0) 80 #define DP0_VIDSRC_COLOR_BAR (3 << 0) 81 82 /* Control */ 83 #define DP0CTL 0x0600 84 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */ 85 #define EF_EN BIT(5) /* Enable Enhanced Framing */ 86 #define VID_EN BIT(1) /* Video transmission enable */ 87 #define DP_EN BIT(0) /* Enable DPTX function */ 88 89 /* Clocks */ 90 #define DP0_VIDMNGEN0 0x0610 91 #define DP0_VIDMNGEN1 0x0614 92 #define DP0_VMNGENSTATUS 0x0618 93 94 /* Main Channel */ 95 #define DP0_SECSAMPLE 0x0640 96 #define DP0_VIDSYNCDELAY 0x0644 97 #define DP0_TOTALVAL 0x0648 98 #define DP0_STARTVAL 0x064c 99 #define DP0_ACTIVEVAL 0x0650 100 #define DP0_SYNCVAL 0x0654 101 #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) 102 #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) 103 #define DP0_MISC 0x0658 104 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ 105 #define BPC_6 (0 << 5) 106 #define BPC_8 (1 << 5) 107 108 /* AUX channel */ 109 #define DP0_AUXCFG0 0x0660 110 #define DP0_AUXCFG1 0x0664 111 #define AUX_RX_FILTER_EN BIT(16) 112 113 #define DP0_AUXADDR 0x0668 114 #define DP0_AUXWDATA(i) (0x066c + (i) * 4) 115 #define DP0_AUXRDATA(i) (0x067c + (i) * 4) 116 #define DP0_AUXSTATUS 0x068c 117 #define AUX_STATUS_MASK 0xf0 118 #define AUX_STATUS_SHIFT 4 119 #define AUX_TIMEOUT BIT(1) 120 #define AUX_BUSY BIT(0) 121 #define DP0_AUXI2CADR 0x0698 122 123 /* Link Training */ 124 #define DP0_SRCCTRL 0x06a0 125 #define DP0_SRCCTRL_SCRMBLDIS BIT(13) 126 #define DP0_SRCCTRL_EN810B BIT(12) 127 #define DP0_SRCCTRL_NOTP (0 << 8) 128 #define DP0_SRCCTRL_TP1 (1 << 8) 129 #define DP0_SRCCTRL_TP2 (2 << 8) 130 #define DP0_SRCCTRL_LANESKEW BIT(7) 131 #define DP0_SRCCTRL_SSCG BIT(3) 132 #define DP0_SRCCTRL_LANES_1 (0 << 2) 133 #define DP0_SRCCTRL_LANES_2 (1 << 2) 134 #define DP0_SRCCTRL_BW27 (1 << 1) 135 #define DP0_SRCCTRL_BW162 (0 << 1) 136 #define DP0_SRCCTRL_AUTOCORRECT BIT(0) 137 #define DP0_LTSTAT 0x06d0 138 #define LT_LOOPDONE BIT(13) 139 #define LT_STATUS_MASK (0x1f << 8) 140 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4) 141 #define LT_INTERLANE_ALIGN_DONE BIT(3) 142 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS) 143 #define DP0_SNKLTCHGREQ 0x06d4 144 #define DP0_LTLOOPCTRL 0x06d8 145 #define DP0_SNKLTCTRL 0x06e4 146 147 #define DP1_SRCCTRL 0x07a0 148 149 /* PHY */ 150 #define DP_PHY_CTRL 0x0800 151 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ 152 #define BGREN BIT(25) /* AUX PHY BGR Enable */ 153 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */ 154 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ 155 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ 156 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ 157 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */ 158 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ 159 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ 160 161 /* PLL */ 162 #define DP0_PLLCTRL 0x0900 163 #define DP1_PLLCTRL 0x0904 /* not defined in DS */ 164 #define PXL_PLLCTRL 0x0908 165 #define PLLUPDATE BIT(2) 166 #define PLLBYP BIT(1) 167 #define PLLEN BIT(0) 168 #define PXL_PLLPARAM 0x0914 169 #define IN_SEL_REFCLK (0 << 14) 170 #define SYS_PLLPARAM 0x0918 171 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */ 172 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */ 173 #define REF_FREQ_26M (2 << 8) /* 26 MHz */ 174 #define REF_FREQ_13M (3 << 8) /* 13 MHz */ 175 #define SYSCLK_SEL_LSCLK (0 << 4) 176 #define LSCLK_DIV_1 (0 << 0) 177 #define LSCLK_DIV_2 (1 << 0) 178 179 /* Test & Debug */ 180 #define TSTCTL 0x0a00 181 #define PLL_DBG 0x0a04 182 183 static bool tc_test_pattern; 184 module_param_named(test, tc_test_pattern, bool, 0644); 185 186 struct tc_edp_link { 187 struct drm_dp_link base; 188 u8 assr; 189 bool scrambler_dis; 190 bool spread; 191 }; 192 193 struct tc_data { 194 struct device *dev; 195 struct regmap *regmap; 196 struct drm_dp_aux aux; 197 198 struct drm_bridge bridge; 199 struct drm_connector connector; 200 struct drm_panel *panel; 201 202 /* link settings */ 203 struct tc_edp_link link; 204 205 /* display edid */ 206 struct edid *edid; 207 /* current mode */ 208 const struct drm_display_mode *mode; 209 210 u32 rev; 211 u8 assr; 212 213 struct gpio_desc *sd_gpio; 214 struct gpio_desc *reset_gpio; 215 struct clk *refclk; 216 }; 217 218 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a) 219 { 220 return container_of(a, struct tc_data, aux); 221 } 222 223 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 224 { 225 return container_of(b, struct tc_data, bridge); 226 } 227 228 static inline struct tc_data *connector_to_tc(struct drm_connector *c) 229 { 230 return container_of(c, struct tc_data, connector); 231 } 232 233 /* Simple macros to avoid repeated error checks */ 234 #define tc_write(reg, var) \ 235 do { \ 236 ret = regmap_write(tc->regmap, reg, var); \ 237 if (ret) \ 238 goto err; \ 239 } while (0) 240 #define tc_read(reg, var) \ 241 do { \ 242 ret = regmap_read(tc->regmap, reg, var); \ 243 if (ret) \ 244 goto err; \ 245 } while (0) 246 247 static inline int tc_poll_timeout(struct regmap *map, unsigned int addr, 248 unsigned int cond_mask, 249 unsigned int cond_value, 250 unsigned long sleep_us, u64 timeout_us) 251 { 252 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); 253 unsigned int val; 254 int ret; 255 256 for (;;) { 257 ret = regmap_read(map, addr, &val); 258 if (ret) 259 break; 260 if ((val & cond_mask) == cond_value) 261 break; 262 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { 263 ret = regmap_read(map, addr, &val); 264 break; 265 } 266 if (sleep_us) 267 usleep_range((sleep_us >> 2) + 1, sleep_us); 268 } 269 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT); 270 } 271 272 static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms) 273 { 274 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0, 275 1000, 1000 * timeout_ms); 276 } 277 278 static int tc_aux_get_status(struct tc_data *tc, u8 *reply) 279 { 280 int ret; 281 u32 value; 282 283 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value); 284 if (ret < 0) 285 return ret; 286 287 if (value & AUX_BUSY) { 288 dev_err(tc->dev, "aux busy!\n"); 289 return -EBUSY; 290 } 291 292 if (value & AUX_TIMEOUT) { 293 dev_err(tc->dev, "aux access timeout!\n"); 294 return -ETIMEDOUT; 295 } 296 297 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT; 298 return 0; 299 } 300 301 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux, 302 struct drm_dp_aux_msg *msg) 303 { 304 struct tc_data *tc = aux_to_tc(aux); 305 size_t size = min_t(size_t, 8, msg->size); 306 u8 request = msg->request & ~DP_AUX_I2C_MOT; 307 u8 *buf = msg->buffer; 308 u32 tmp = 0; 309 int i = 0; 310 int ret; 311 312 if (size == 0) 313 return 0; 314 315 ret = tc_aux_wait_busy(tc, 100); 316 if (ret) 317 goto err; 318 319 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) { 320 /* Store data */ 321 while (i < size) { 322 if (request == DP_AUX_NATIVE_WRITE) 323 tmp = tmp | (buf[i] << (8 * (i & 0x3))); 324 else 325 tmp = (tmp << 8) | buf[i]; 326 i++; 327 if (((i % 4) == 0) || (i == size)) { 328 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp); 329 tmp = 0; 330 } 331 } 332 } else if (request != DP_AUX_I2C_READ && 333 request != DP_AUX_NATIVE_READ) { 334 return -EINVAL; 335 } 336 337 /* Store address */ 338 tc_write(DP0_AUXADDR, msg->address); 339 /* Start transfer */ 340 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request); 341 342 ret = tc_aux_wait_busy(tc, 100); 343 if (ret) 344 goto err; 345 346 ret = tc_aux_get_status(tc, &msg->reply); 347 if (ret) 348 goto err; 349 350 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) { 351 /* Read data */ 352 while (i < size) { 353 if ((i % 4) == 0) 354 tc_read(DP0_AUXRDATA(i >> 2), &tmp); 355 buf[i] = tmp & 0xff; 356 tmp = tmp >> 8; 357 i++; 358 } 359 } 360 361 return size; 362 err: 363 return ret; 364 } 365 366 static const char * const training_pattern1_errors[] = { 367 "No errors", 368 "Aux write error", 369 "Aux read error", 370 "Max voltage reached error", 371 "Loop counter expired error", 372 "res", "res", "res" 373 }; 374 375 static const char * const training_pattern2_errors[] = { 376 "No errors", 377 "Aux write error", 378 "Aux read error", 379 "Clock recovery failed error", 380 "Loop counter expired error", 381 "res", "res", "res" 382 }; 383 384 static u32 tc_srcctrl(struct tc_data *tc) 385 { 386 /* 387 * No training pattern, skew lane 1 data by two LSCLK cycles with 388 * respect to lane 0 data, AutoCorrect Mode = 0 389 */ 390 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B; 391 392 if (tc->link.scrambler_dis) 393 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ 394 if (tc->link.spread) 395 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ 396 if (tc->link.base.num_lanes == 2) 397 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ 398 if (tc->link.base.rate != 162000) 399 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */ 400 return reg; 401 } 402 403 static void tc_wait_pll_lock(struct tc_data *tc) 404 { 405 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */ 406 usleep_range(3000, 6000); 407 } 408 409 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) 410 { 411 int ret; 412 int i_pre, best_pre = 1; 413 int i_post, best_post = 1; 414 int div, best_div = 1; 415 int mul, best_mul = 1; 416 int delta, best_delta; 417 int ext_div[] = {1, 2, 3, 5, 7}; 418 int best_pixelclock = 0; 419 int vco_hi = 0; 420 421 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, 422 refclk); 423 best_delta = pixelclock; 424 /* Loop over all possible ext_divs, skipping invalid configurations */ 425 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) { 426 /* 427 * refclk / ext_pre_div should be in the 1 to 200 MHz range. 428 * We don't allow any refclk > 200 MHz, only check lower bounds. 429 */ 430 if (refclk / ext_div[i_pre] < 1000000) 431 continue; 432 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { 433 for (div = 1; div <= 16; div++) { 434 u32 clk; 435 u64 tmp; 436 437 tmp = pixelclock * ext_div[i_pre] * 438 ext_div[i_post] * div; 439 do_div(tmp, refclk); 440 mul = tmp; 441 442 /* Check limits */ 443 if ((mul < 1) || (mul > 128)) 444 continue; 445 446 clk = (refclk / ext_div[i_pre] / div) * mul; 447 /* 448 * refclk * mul / (ext_pre_div * pre_div) 449 * should be in the 150 to 650 MHz range 450 */ 451 if ((clk > 650000000) || (clk < 150000000)) 452 continue; 453 454 clk = clk / ext_div[i_post]; 455 delta = clk - pixelclock; 456 457 if (abs(delta) < abs(best_delta)) { 458 best_pre = i_pre; 459 best_post = i_post; 460 best_div = div; 461 best_mul = mul; 462 best_delta = delta; 463 best_pixelclock = clk; 464 } 465 } 466 } 467 } 468 if (best_pixelclock == 0) { 469 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", 470 pixelclock); 471 return -EINVAL; 472 } 473 474 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, 475 best_delta); 476 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, 477 ext_div[best_pre], best_div, best_mul, ext_div[best_post]); 478 479 /* if VCO >= 300 MHz */ 480 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000) 481 vco_hi = 1; 482 /* see DS */ 483 if (best_div == 16) 484 best_div = 0; 485 if (best_mul == 128) 486 best_mul = 0; 487 488 /* Power up PLL and switch to bypass */ 489 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN); 490 491 tc_write(PXL_PLLPARAM, 492 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */ 493 (ext_div[best_pre] << 20) | /* External Pre-divider */ 494 (ext_div[best_post] << 16) | /* External Post-divider */ 495 IN_SEL_REFCLK | /* Use RefClk as PLL input */ 496 (best_div << 8) | /* Divider for PLL RefClk */ 497 (best_mul << 0)); /* Multiplier for PLL */ 498 499 /* Force PLL parameter update and disable bypass */ 500 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN); 501 502 tc_wait_pll_lock(tc); 503 504 return 0; 505 err: 506 return ret; 507 } 508 509 static int tc_pxl_pll_dis(struct tc_data *tc) 510 { 511 /* Enable PLL bypass, power down PLL */ 512 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); 513 } 514 515 static int tc_stream_clock_calc(struct tc_data *tc) 516 { 517 int ret; 518 /* 519 * If the Stream clock and Link Symbol clock are 520 * asynchronous with each other, the value of M changes over 521 * time. This way of generating link clock and stream 522 * clock is called Asynchronous Clock mode. The value M 523 * must change while the value N stays constant. The 524 * value of N in this Asynchronous Clock mode must be set 525 * to 2^15 or 32,768. 526 * 527 * LSCLK = 1/10 of high speed link clock 528 * 529 * f_STRMCLK = M/N * f_LSCLK 530 * M/N = f_STRMCLK / f_LSCLK 531 * 532 */ 533 tc_write(DP0_VIDMNGEN1, 32768); 534 535 return 0; 536 err: 537 return ret; 538 } 539 540 static int tc_aux_link_setup(struct tc_data *tc) 541 { 542 unsigned long rate; 543 u32 value; 544 int ret; 545 546 rate = clk_get_rate(tc->refclk); 547 switch (rate) { 548 case 38400000: 549 value = REF_FREQ_38M4; 550 break; 551 case 26000000: 552 value = REF_FREQ_26M; 553 break; 554 case 19200000: 555 value = REF_FREQ_19M2; 556 break; 557 case 13000000: 558 value = REF_FREQ_13M; 559 break; 560 default: 561 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); 562 return -EINVAL; 563 } 564 565 /* Setup DP-PHY / PLL */ 566 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 567 tc_write(SYS_PLLPARAM, value); 568 569 tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_A0_EN); 570 571 /* 572 * Initially PLLs are in bypass. Force PLL parameter update, 573 * disable PLL bypass, enable PLL 574 */ 575 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); 576 tc_wait_pll_lock(tc); 577 578 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); 579 tc_wait_pll_lock(tc); 580 581 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 582 1000); 583 if (ret == -ETIMEDOUT) { 584 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); 585 return ret; 586 } else if (ret) { 587 goto err; 588 } 589 590 /* Setup AUX link */ 591 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN | 592 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */ 593 (0x3f << 0)); /* Aux Response Timeout Timer */ 594 595 return 0; 596 err: 597 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); 598 return ret; 599 } 600 601 static int tc_get_display_props(struct tc_data *tc) 602 { 603 int ret; 604 /* temp buffer */ 605 u8 tmp[8]; 606 607 /* Read DP Rx Link Capability */ 608 ret = drm_dp_link_probe(&tc->aux, &tc->link.base); 609 if (ret < 0) 610 goto err_dpcd_read; 611 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) { 612 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); 613 tc->link.base.rate = 270000; 614 } 615 616 if (tc->link.base.num_lanes > 2) { 617 dev_dbg(tc->dev, "Falling to 2 lanes\n"); 618 tc->link.base.num_lanes = 2; 619 } 620 621 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp); 622 if (ret < 0) 623 goto err_dpcd_read; 624 tc->link.spread = tmp[0] & DP_MAX_DOWNSPREAD_0_5; 625 626 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp); 627 if (ret < 0) 628 goto err_dpcd_read; 629 630 tc->link.scrambler_dis = false; 631 /* read assr */ 632 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp); 633 if (ret < 0) 634 goto err_dpcd_read; 635 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 636 637 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", 638 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f, 639 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps", 640 tc->link.base.num_lanes, 641 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? 642 "enhanced" : "non-enhanced"); 643 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", 644 tc->link.spread ? "0.5%" : "0.0%", 645 tc->link.scrambler_dis ? "disabled" : "enabled"); 646 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", 647 tc->link.assr, tc->assr); 648 649 return 0; 650 651 err_dpcd_read: 652 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); 653 return ret; 654 } 655 656 static int tc_set_video_mode(struct tc_data *tc, 657 const struct drm_display_mode *mode) 658 { 659 int ret; 660 int vid_sync_dly; 661 int max_tu_symbol; 662 663 int left_margin = mode->htotal - mode->hsync_end; 664 int right_margin = mode->hsync_start - mode->hdisplay; 665 int hsync_len = mode->hsync_end - mode->hsync_start; 666 int upper_margin = mode->vtotal - mode->vsync_end; 667 int lower_margin = mode->vsync_start - mode->vdisplay; 668 int vsync_len = mode->vsync_end - mode->vsync_start; 669 670 /* 671 * Recommended maximum number of symbols transferred in a transfer unit: 672 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size, 673 * (output active video bandwidth in bytes)) 674 * Must be less than tu_size. 675 */ 676 max_tu_symbol = TU_SIZE_RECOMMENDED - 1; 677 678 dev_dbg(tc->dev, "set mode %dx%d\n", 679 mode->hdisplay, mode->vdisplay); 680 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", 681 left_margin, right_margin, hsync_len); 682 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", 683 upper_margin, lower_margin, vsync_len); 684 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); 685 686 687 /* 688 * LCD Ctl Frame Size 689 * datasheet is not clear of vsdelay in case of DPI 690 * assume we do not need any delay when DPI is a source of 691 * sync signals 692 */ 693 tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ | 694 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED); 695 tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */ 696 (ALIGN(hsync_len, 2) << 0)); /* Hsync */ 697 tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */ 698 (ALIGN(mode->hdisplay, 2) << 0)); /* width */ 699 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */ 700 (vsync_len << 0)); /* Vsync */ 701 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */ 702 (mode->vdisplay << 0)); /* height */ 703 tc_write(VFUEN0, VFUEN); /* update settings */ 704 705 /* Test pattern settings */ 706 tc_write(TSTCTL, 707 (120 << 24) | /* Red Color component value */ 708 (20 << 16) | /* Green Color component value */ 709 (99 << 8) | /* Blue Color component value */ 710 (1 << 4) | /* Enable I2C Filter */ 711 (2 << 0) | /* Color bar Mode */ 712 0); 713 714 /* DP Main Stream Attributes */ 715 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; 716 tc_write(DP0_VIDSYNCDELAY, 717 (max_tu_symbol << 16) | /* thresh_dly */ 718 (vid_sync_dly << 0)); 719 720 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal)); 721 722 tc_write(DP0_STARTVAL, 723 ((upper_margin + vsync_len) << 16) | 724 ((left_margin + hsync_len) << 0)); 725 726 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay)); 727 728 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) | 729 ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) | 730 ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0)); 731 732 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW | 733 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888); 734 735 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) | 736 BPC_8); 737 738 return 0; 739 err: 740 return ret; 741 } 742 743 static int tc_link_training(struct tc_data *tc, int pattern) 744 { 745 const char * const *errors; 746 u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 747 DP0_SRCCTRL_AUTOCORRECT; 748 int timeout; 749 int retry; 750 u32 value; 751 int ret; 752 753 if (pattern == DP_TRAINING_PATTERN_1) { 754 srcctrl |= DP0_SRCCTRL_TP1; 755 errors = training_pattern1_errors; 756 } else { 757 srcctrl |= DP0_SRCCTRL_TP2; 758 errors = training_pattern2_errors; 759 } 760 761 /* Set DPCD 0x102 for Training Part 1 or 2 */ 762 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern); 763 764 tc_write(DP0_LTLOOPCTRL, 765 (0x0f << 28) | /* Defer Iteration Count */ 766 (0x0f << 24) | /* Loop Iteration Count */ 767 (0x0d << 0)); /* Loop Timer Delay */ 768 769 retry = 5; 770 do { 771 /* Set DP0 Training Pattern */ 772 tc_write(DP0_SRCCTRL, srcctrl); 773 774 /* Enable DP0 to start Link Training */ 775 tc_write(DP0CTL, DP_EN); 776 777 /* wait */ 778 timeout = 1000; 779 do { 780 tc_read(DP0_LTSTAT, &value); 781 udelay(1); 782 } while ((!(value & LT_LOOPDONE)) && (--timeout)); 783 if (timeout == 0) { 784 dev_err(tc->dev, "Link training timeout!\n"); 785 } else { 786 int pattern = (value >> 11) & 0x3; 787 int error = (value >> 8) & 0x7; 788 789 dev_dbg(tc->dev, 790 "Link training phase %d done after %d uS: %s\n", 791 pattern, 1000 - timeout, errors[error]); 792 if (pattern == DP_TRAINING_PATTERN_1 && error == 0) 793 break; 794 if (pattern == DP_TRAINING_PATTERN_2) { 795 value &= LT_CHANNEL1_EQ_BITS | 796 LT_INTERLANE_ALIGN_DONE | 797 LT_CHANNEL0_EQ_BITS; 798 /* in case of two lanes */ 799 if ((tc->link.base.num_lanes == 2) && 800 (value == (LT_CHANNEL1_EQ_BITS | 801 LT_INTERLANE_ALIGN_DONE | 802 LT_CHANNEL0_EQ_BITS))) 803 break; 804 /* in case of one line */ 805 if ((tc->link.base.num_lanes == 1) && 806 (value == (LT_INTERLANE_ALIGN_DONE | 807 LT_CHANNEL0_EQ_BITS))) 808 break; 809 } 810 } 811 /* restart */ 812 tc_write(DP0CTL, 0); 813 usleep_range(10, 20); 814 } while (--retry); 815 if (retry == 0) { 816 dev_err(tc->dev, "Failed to finish training phase %d\n", 817 pattern); 818 } 819 820 return 0; 821 err: 822 return ret; 823 } 824 825 static int tc_main_link_setup(struct tc_data *tc) 826 { 827 struct drm_dp_aux *aux = &tc->aux; 828 struct device *dev = tc->dev; 829 unsigned int rate; 830 u32 dp_phy_ctrl; 831 int timeout; 832 u32 value; 833 int ret; 834 u8 tmp[8]; 835 836 /* display mode should be set at this point */ 837 if (!tc->mode) 838 return -EINVAL; 839 840 tc_write(DP0_SRCCTRL, tc_srcctrl(tc)); 841 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ 842 tc_write(DP1_SRCCTRL, 843 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | 844 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); 845 846 rate = clk_get_rate(tc->refclk); 847 switch (rate) { 848 case 38400000: 849 value = REF_FREQ_38M4; 850 break; 851 case 26000000: 852 value = REF_FREQ_26M; 853 break; 854 case 19200000: 855 value = REF_FREQ_19M2; 856 break; 857 case 13000000: 858 value = REF_FREQ_13M; 859 break; 860 default: 861 return -EINVAL; 862 } 863 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 864 tc_write(SYS_PLLPARAM, value); 865 866 /* Setup Main Link */ 867 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN; 868 if (tc->link.base.num_lanes == 2) 869 dp_phy_ctrl |= PHY_2LANE; 870 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 871 msleep(100); 872 873 /* PLL setup */ 874 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN); 875 tc_wait_pll_lock(tc); 876 877 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN); 878 tc_wait_pll_lock(tc); 879 880 /* PXL PLL setup */ 881 if (tc_test_pattern) { 882 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 883 1000 * tc->mode->clock); 884 if (ret) 885 goto err; 886 } 887 888 /* Reset/Enable Main Links */ 889 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; 890 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 891 usleep_range(100, 200); 892 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST); 893 tc_write(DP_PHY_CTRL, dp_phy_ctrl); 894 895 timeout = 1000; 896 do { 897 tc_read(DP_PHY_CTRL, &value); 898 udelay(1); 899 } while ((!(value & PHY_RDY)) && (--timeout)); 900 901 if (timeout == 0) { 902 dev_err(dev, "timeout waiting for phy become ready"); 903 return -ETIMEDOUT; 904 } 905 906 /* Set misc: 8 bits per color */ 907 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); 908 if (ret) 909 goto err; 910 911 /* 912 * ASSR mode 913 * on TC358767 side ASSR configured through strap pin 914 * seems there is no way to change this setting from SW 915 * 916 * check is tc configured for same mode 917 */ 918 if (tc->assr != tc->link.assr) { 919 dev_dbg(dev, "Trying to set display to ASSR: %d\n", 920 tc->assr); 921 /* try to set ASSR on display side */ 922 tmp[0] = tc->assr; 923 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]); 924 if (ret < 0) 925 goto err_dpcd_read; 926 /* read back */ 927 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp); 928 if (ret < 0) 929 goto err_dpcd_read; 930 931 if (tmp[0] != tc->assr) { 932 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", 933 tc->assr); 934 /* trying with disabled scrambler */ 935 tc->link.scrambler_dis = true; 936 } 937 } 938 939 /* Setup Link & DPRx Config for Training */ 940 ret = drm_dp_link_configure(aux, &tc->link.base); 941 if (ret < 0) 942 goto err_dpcd_write; 943 944 /* DOWNSPREAD_CTRL */ 945 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; 946 /* MAIN_LINK_CHANNEL_CODING_SET */ 947 tmp[1] = DP_SET_ANSI_8B10B; 948 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); 949 if (ret < 0) 950 goto err_dpcd_write; 951 952 /* Reset voltage-swing & pre-emphasis */ 953 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 954 DP_TRAIN_PRE_EMPH_LEVEL_0; 955 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2); 956 if (ret < 0) 957 goto err_dpcd_write; 958 959 ret = tc_link_training(tc, DP_TRAINING_PATTERN_1); 960 if (ret) 961 goto err; 962 963 ret = tc_link_training(tc, DP_TRAINING_PATTERN_2); 964 if (ret) 965 goto err; 966 967 /* Clear DPCD 0x102 */ 968 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */ 969 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; 970 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]); 971 if (ret < 0) 972 goto err_dpcd_write; 973 974 /* Clear Training Pattern, set AutoCorrect Mode = 1 */ 975 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT); 976 977 /* Wait */ 978 timeout = 100; 979 do { 980 udelay(1); 981 /* Read DPCD 0x202-0x207 */ 982 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2); 983 if (ret < 0) 984 goto err_dpcd_read; 985 } while ((--timeout) && 986 !(drm_dp_channel_eq_ok(tmp + 2, tc->link.base.num_lanes))); 987 988 if (timeout == 0) { 989 /* Read DPCD 0x200-0x201 */ 990 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2); 991 if (ret < 0) 992 goto err_dpcd_read; 993 dev_err(dev, "channel(s) EQ not ok\n"); 994 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]); 995 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n", 996 tmp[1]); 997 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]); 998 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", 999 tmp[4]); 1000 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]); 1001 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", 1002 tmp[6]); 1003 1004 return -EAGAIN; 1005 } 1006 1007 return 0; 1008 err_dpcd_read: 1009 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); 1010 return ret; 1011 err_dpcd_write: 1012 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); 1013 err: 1014 return ret; 1015 } 1016 1017 static int tc_main_link_stream(struct tc_data *tc, int state) 1018 { 1019 int ret; 1020 u32 value; 1021 1022 dev_dbg(tc->dev, "stream: %d\n", state); 1023 1024 if (state) { 1025 ret = tc_set_video_mode(tc, tc->mode); 1026 if (ret) 1027 goto err; 1028 1029 /* Set M/N */ 1030 ret = tc_stream_clock_calc(tc); 1031 if (ret) 1032 goto err; 1033 1034 value = VID_MN_GEN | DP_EN; 1035 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1036 value |= EF_EN; 1037 tc_write(DP0CTL, value); 1038 /* 1039 * VID_EN assertion should be delayed by at least N * LSCLK 1040 * cycles from the time VID_MN_GEN is enabled in order to 1041 * generate stable values for VID_M. LSCLK is 270 MHz or 1042 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(), 1043 * so a delay of at least 203 us should suffice. 1044 */ 1045 usleep_range(500, 1000); 1046 value |= VID_EN; 1047 tc_write(DP0CTL, value); 1048 /* Set input interface */ 1049 value = DP0_AUDSRC_NO_INPUT; 1050 if (tc_test_pattern) 1051 value |= DP0_VIDSRC_COLOR_BAR; 1052 else 1053 value |= DP0_VIDSRC_DPI_RX; 1054 tc_write(SYSCTRL, value); 1055 } else { 1056 tc_write(DP0CTL, 0); 1057 } 1058 1059 return 0; 1060 err: 1061 return ret; 1062 } 1063 1064 static void tc_bridge_pre_enable(struct drm_bridge *bridge) 1065 { 1066 struct tc_data *tc = bridge_to_tc(bridge); 1067 1068 drm_panel_prepare(tc->panel); 1069 } 1070 1071 static void tc_bridge_enable(struct drm_bridge *bridge) 1072 { 1073 struct tc_data *tc = bridge_to_tc(bridge); 1074 int ret; 1075 1076 ret = tc_main_link_setup(tc); 1077 if (ret < 0) { 1078 dev_err(tc->dev, "main link setup error: %d\n", ret); 1079 return; 1080 } 1081 1082 ret = tc_main_link_stream(tc, 1); 1083 if (ret < 0) { 1084 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1085 return; 1086 } 1087 1088 drm_panel_enable(tc->panel); 1089 } 1090 1091 static void tc_bridge_disable(struct drm_bridge *bridge) 1092 { 1093 struct tc_data *tc = bridge_to_tc(bridge); 1094 int ret; 1095 1096 drm_panel_disable(tc->panel); 1097 1098 ret = tc_main_link_stream(tc, 0); 1099 if (ret < 0) 1100 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1101 } 1102 1103 static void tc_bridge_post_disable(struct drm_bridge *bridge) 1104 { 1105 struct tc_data *tc = bridge_to_tc(bridge); 1106 1107 drm_panel_unprepare(tc->panel); 1108 } 1109 1110 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge, 1111 const struct drm_display_mode *mode, 1112 struct drm_display_mode *adj) 1113 { 1114 /* Fixup sync polarities, both hsync and vsync are active low */ 1115 adj->flags = mode->flags; 1116 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1117 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1118 1119 return true; 1120 } 1121 1122 static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connector, 1123 struct drm_display_mode *mode) 1124 { 1125 struct tc_data *tc = connector_to_tc(connector); 1126 u32 req, avail; 1127 u32 bits_per_pixel = 24; 1128 1129 /* DPI interface clock limitation: upto 154 MHz */ 1130 if (mode->clock > 154000) 1131 return MODE_CLOCK_HIGH; 1132 1133 req = mode->clock * bits_per_pixel / 8; 1134 avail = tc->link.base.num_lanes * tc->link.base.rate; 1135 1136 if (req > avail) 1137 return MODE_BAD; 1138 1139 return MODE_OK; 1140 } 1141 1142 static void tc_bridge_mode_set(struct drm_bridge *bridge, 1143 const struct drm_display_mode *mode, 1144 const struct drm_display_mode *adj) 1145 { 1146 struct tc_data *tc = bridge_to_tc(bridge); 1147 1148 tc->mode = mode; 1149 } 1150 1151 static int tc_connector_get_modes(struct drm_connector *connector) 1152 { 1153 struct tc_data *tc = connector_to_tc(connector); 1154 struct edid *edid; 1155 unsigned int count; 1156 1157 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) { 1158 count = tc->panel->funcs->get_modes(tc->panel); 1159 if (count > 0) 1160 return count; 1161 } 1162 1163 edid = drm_get_edid(connector, &tc->aux.ddc); 1164 1165 kfree(tc->edid); 1166 tc->edid = edid; 1167 if (!edid) 1168 return 0; 1169 1170 drm_connector_update_edid_property(connector, edid); 1171 count = drm_add_edid_modes(connector, edid); 1172 1173 return count; 1174 } 1175 1176 static void tc_connector_set_polling(struct tc_data *tc, 1177 struct drm_connector *connector) 1178 { 1179 /* TODO: add support for HPD */ 1180 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1181 DRM_CONNECTOR_POLL_DISCONNECT; 1182 } 1183 1184 static struct drm_encoder * 1185 tc_connector_best_encoder(struct drm_connector *connector) 1186 { 1187 struct tc_data *tc = connector_to_tc(connector); 1188 1189 return tc->bridge.encoder; 1190 } 1191 1192 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = { 1193 .get_modes = tc_connector_get_modes, 1194 .mode_valid = tc_connector_mode_valid, 1195 .best_encoder = tc_connector_best_encoder, 1196 }; 1197 1198 static const struct drm_connector_funcs tc_connector_funcs = { 1199 .fill_modes = drm_helper_probe_single_connector_modes, 1200 .destroy = drm_connector_cleanup, 1201 .reset = drm_atomic_helper_connector_reset, 1202 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1203 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1204 }; 1205 1206 static int tc_bridge_attach(struct drm_bridge *bridge) 1207 { 1208 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1209 struct tc_data *tc = bridge_to_tc(bridge); 1210 struct drm_device *drm = bridge->dev; 1211 int ret; 1212 1213 /* Create eDP connector */ 1214 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); 1215 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, 1216 tc->panel ? DRM_MODE_CONNECTOR_eDP : 1217 DRM_MODE_CONNECTOR_DisplayPort); 1218 if (ret) 1219 return ret; 1220 1221 if (tc->panel) 1222 drm_panel_attach(tc->panel, &tc->connector); 1223 1224 drm_display_info_set_bus_formats(&tc->connector.display_info, 1225 &bus_format, 1); 1226 tc->connector.display_info.bus_flags = 1227 DRM_BUS_FLAG_DE_HIGH | 1228 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE | 1229 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 1230 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); 1231 1232 return 0; 1233 } 1234 1235 static const struct drm_bridge_funcs tc_bridge_funcs = { 1236 .attach = tc_bridge_attach, 1237 .mode_set = tc_bridge_mode_set, 1238 .pre_enable = tc_bridge_pre_enable, 1239 .enable = tc_bridge_enable, 1240 .disable = tc_bridge_disable, 1241 .post_disable = tc_bridge_post_disable, 1242 .mode_fixup = tc_bridge_mode_fixup, 1243 }; 1244 1245 static bool tc_readable_reg(struct device *dev, unsigned int reg) 1246 { 1247 return reg != SYSCTRL; 1248 } 1249 1250 static const struct regmap_range tc_volatile_ranges[] = { 1251 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS), 1252 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 1253 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL), 1254 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL), 1255 regmap_reg_range(VFUEN0, VFUEN0), 1256 }; 1257 1258 static const struct regmap_access_table tc_volatile_table = { 1259 .yes_ranges = tc_volatile_ranges, 1260 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges), 1261 }; 1262 1263 static bool tc_writeable_reg(struct device *dev, unsigned int reg) 1264 { 1265 return (reg != TC_IDREG) && 1266 (reg != DP0_LTSTAT) && 1267 (reg != DP0_SNKLTCHGREQ); 1268 } 1269 1270 static const struct regmap_config tc_regmap_config = { 1271 .name = "tc358767", 1272 .reg_bits = 16, 1273 .val_bits = 32, 1274 .reg_stride = 4, 1275 .max_register = PLL_DBG, 1276 .cache_type = REGCACHE_RBTREE, 1277 .readable_reg = tc_readable_reg, 1278 .volatile_table = &tc_volatile_table, 1279 .writeable_reg = tc_writeable_reg, 1280 .reg_format_endian = REGMAP_ENDIAN_BIG, 1281 .val_format_endian = REGMAP_ENDIAN_LITTLE, 1282 }; 1283 1284 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id) 1285 { 1286 struct device *dev = &client->dev; 1287 struct tc_data *tc; 1288 int ret; 1289 1290 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 1291 if (!tc) 1292 return -ENOMEM; 1293 1294 tc->dev = dev; 1295 1296 /* port@2 is the output port */ 1297 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL); 1298 if (ret && ret != -ENODEV) 1299 return ret; 1300 1301 /* Shut down GPIO is optional */ 1302 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); 1303 if (IS_ERR(tc->sd_gpio)) 1304 return PTR_ERR(tc->sd_gpio); 1305 1306 if (tc->sd_gpio) { 1307 gpiod_set_value_cansleep(tc->sd_gpio, 0); 1308 usleep_range(5000, 10000); 1309 } 1310 1311 /* Reset GPIO is optional */ 1312 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1313 if (IS_ERR(tc->reset_gpio)) 1314 return PTR_ERR(tc->reset_gpio); 1315 1316 if (tc->reset_gpio) { 1317 gpiod_set_value_cansleep(tc->reset_gpio, 1); 1318 usleep_range(5000, 10000); 1319 } 1320 1321 tc->refclk = devm_clk_get(dev, "ref"); 1322 if (IS_ERR(tc->refclk)) { 1323 ret = PTR_ERR(tc->refclk); 1324 dev_err(dev, "Failed to get refclk: %d\n", ret); 1325 return ret; 1326 } 1327 1328 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); 1329 if (IS_ERR(tc->regmap)) { 1330 ret = PTR_ERR(tc->regmap); 1331 dev_err(dev, "Failed to initialize regmap: %d\n", ret); 1332 return ret; 1333 } 1334 1335 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); 1336 if (ret) { 1337 dev_err(tc->dev, "can not read device ID: %d\n", ret); 1338 return ret; 1339 } 1340 1341 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { 1342 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); 1343 return -EINVAL; 1344 } 1345 1346 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ 1347 1348 ret = tc_aux_link_setup(tc); 1349 if (ret) 1350 return ret; 1351 1352 /* Register DP AUX channel */ 1353 tc->aux.name = "TC358767 AUX i2c adapter"; 1354 tc->aux.dev = tc->dev; 1355 tc->aux.transfer = tc_aux_transfer; 1356 ret = drm_dp_aux_register(&tc->aux); 1357 if (ret) 1358 return ret; 1359 1360 ret = tc_get_display_props(tc); 1361 if (ret) 1362 goto err_unregister_aux; 1363 1364 tc_connector_set_polling(tc, &tc->connector); 1365 1366 tc->bridge.funcs = &tc_bridge_funcs; 1367 tc->bridge.of_node = dev->of_node; 1368 drm_bridge_add(&tc->bridge); 1369 1370 i2c_set_clientdata(client, tc); 1371 1372 return 0; 1373 err_unregister_aux: 1374 drm_dp_aux_unregister(&tc->aux); 1375 return ret; 1376 } 1377 1378 static int tc_remove(struct i2c_client *client) 1379 { 1380 struct tc_data *tc = i2c_get_clientdata(client); 1381 1382 drm_bridge_remove(&tc->bridge); 1383 drm_dp_aux_unregister(&tc->aux); 1384 1385 tc_pxl_pll_dis(tc); 1386 1387 return 0; 1388 } 1389 1390 static const struct i2c_device_id tc358767_i2c_ids[] = { 1391 { "tc358767", 0 }, 1392 { } 1393 }; 1394 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids); 1395 1396 static const struct of_device_id tc358767_of_ids[] = { 1397 { .compatible = "toshiba,tc358767", }, 1398 { } 1399 }; 1400 MODULE_DEVICE_TABLE(of, tc358767_of_ids); 1401 1402 static struct i2c_driver tc358767_driver = { 1403 .driver = { 1404 .name = "tc358767", 1405 .of_match_table = tc358767_of_ids, 1406 }, 1407 .id_table = tc358767_i2c_ids, 1408 .probe = tc_probe, 1409 .remove = tc_remove, 1410 }; 1411 module_i2c_driver(tc358767_driver); 1412 1413 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>"); 1414 MODULE_DESCRIPTION("tc358767 eDP encoder driver"); 1415 MODULE_LICENSE("GPL"); 1416