nv.c (3e67f4f2e22ef1f81c82ec8471d5e2b22fdb30e8) nv.c (1d789535a03679e5ce0b56a0d32a5e44596dfcdb)
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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175static const struct amdgpu_video_codecs yc_video_codecs_decode = {
176 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
177 .codec_array = yc_video_codecs_decode_array,
178};
179
180static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
181 const struct amdgpu_video_codecs **codecs)
182{
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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175static const struct amdgpu_video_codecs yc_video_codecs_decode = {
176 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
177 .codec_array = yc_video_codecs_decode_array,
178};
179
180static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
181 const struct amdgpu_video_codecs **codecs)
182{
183 switch (adev->ip_versions[UVD_HWIP]) {
183 switch (adev->ip_versions[UVD_HWIP][0]) {
184 case IP_VERSION(3, 0, 0):
185 if (amdgpu_sriov_vf(adev)) {
186 if (encode)
187 *codecs = &sriov_sc_video_codecs_encode;
188 else
189 *codecs = &sriov_sc_video_codecs_decode;
190 } else {
191 if (encode)

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504 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
505 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
506 return amdgpu_reset_method;
507
508 if (amdgpu_reset_method != -1)
509 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
510 amdgpu_reset_method);
511
184 case IP_VERSION(3, 0, 0):
185 if (amdgpu_sriov_vf(adev)) {
186 if (encode)
187 *codecs = &sriov_sc_video_codecs_encode;
188 else
189 *codecs = &sriov_sc_video_codecs_decode;
190 } else {
191 if (encode)

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504 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
505 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
506 return amdgpu_reset_method;
507
508 if (amdgpu_reset_method != -1)
509 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
510 amdgpu_reset_method);
511
512 switch (adev->ip_versions[MP1_HWIP]) {
512 switch (adev->ip_versions[MP1_HWIP][0]) {
513 case IP_VERSION(11, 5, 0):
514 case IP_VERSION(13, 0, 1):
515 case IP_VERSION(13, 0, 3):
516 return AMD_RESET_METHOD_MODE2;
517 case IP_VERSION(11, 0, 7):
518 case IP_VERSION(11, 0, 11):
519 case IP_VERSION(11, 0, 12):
520 case IP_VERSION(11, 0, 13):

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1043
1044 adev->asic_funcs = &nv_asic_funcs;
1045
1046 adev->rev_id = nv_get_rev_id(adev);
1047 adev->external_rev_id = 0xff;
1048 /* TODO: split the GC and PG flags based on the relevant IP version for which
1049 * they are relevant.
1050 */
513 case IP_VERSION(11, 5, 0):
514 case IP_VERSION(13, 0, 1):
515 case IP_VERSION(13, 0, 3):
516 return AMD_RESET_METHOD_MODE2;
517 case IP_VERSION(11, 0, 7):
518 case IP_VERSION(11, 0, 11):
519 case IP_VERSION(11, 0, 12):
520 case IP_VERSION(11, 0, 13):

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1043
1044 adev->asic_funcs = &nv_asic_funcs;
1045
1046 adev->rev_id = nv_get_rev_id(adev);
1047 adev->external_rev_id = 0xff;
1048 /* TODO: split the GC and PG flags based on the relevant IP version for which
1049 * they are relevant.
1050 */
1051 switch (adev->ip_versions[GC_HWIP]) {
1051 switch (adev->ip_versions[GC_HWIP][0]) {
1052 case IP_VERSION(10, 1, 10):
1053 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1054 AMD_CG_SUPPORT_GFX_CGCG |
1055 AMD_CG_SUPPORT_IH_CG |
1056 AMD_CG_SUPPORT_HDP_MGCG |
1057 AMD_CG_SUPPORT_HDP_LS |
1058 AMD_CG_SUPPORT_SDMA_MGCG |
1059 AMD_CG_SUPPORT_SDMA_LS |

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1374static int nv_common_set_clockgating_state(void *handle,
1375 enum amd_clockgating_state state)
1376{
1377 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1378
1379 if (amdgpu_sriov_vf(adev))
1380 return 0;
1381
1052 case IP_VERSION(10, 1, 10):
1053 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1054 AMD_CG_SUPPORT_GFX_CGCG |
1055 AMD_CG_SUPPORT_IH_CG |
1056 AMD_CG_SUPPORT_HDP_MGCG |
1057 AMD_CG_SUPPORT_HDP_LS |
1058 AMD_CG_SUPPORT_SDMA_MGCG |
1059 AMD_CG_SUPPORT_SDMA_LS |

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1374static int nv_common_set_clockgating_state(void *handle,
1375 enum amd_clockgating_state state)
1376{
1377 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1378
1379 if (amdgpu_sriov_vf(adev))
1380 return 0;
1381
1382 switch (adev->ip_versions[NBIO_HWIP]) {
1382 switch (adev->ip_versions[NBIO_HWIP][0]) {
1383 case IP_VERSION(2, 3, 0):
1384 case IP_VERSION(2, 3, 1):
1385 case IP_VERSION(2, 3, 2):
1386 case IP_VERSION(3, 3, 0):
1387 case IP_VERSION(3, 3, 1):
1388 case IP_VERSION(3, 3, 2):
1389 case IP_VERSION(3, 3, 3):
1390 adev->nbio.funcs->update_medium_grain_clock_gating(adev,

--- 54 unchanged lines hidden --- 		1383 case IP_VERSION(2, 3, 0):
1384 case IP_VERSION(2, 3, 1):
1385 case IP_VERSION(2, 3, 2):
1386 case IP_VERSION(3, 3, 0):
1387 case IP_VERSION(3, 3, 1):
1388 case IP_VERSION(3, 3, 2):
1389 case IP_VERSION(3, 3, 3):
1390 adev->nbio.funcs->update_medium_grain_clock_gating(adev,

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