1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 102 { 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 111 }; 112 113 static const struct amdgpu_video_codecs sc_video_codecs_decode = 114 { 115 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 116 .codec_array = sc_video_codecs_decode_array, 117 }; 118 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121 { 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124 }; 125 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127 { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136 }; 137 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139 { 140 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141 .codec_array = sriov_sc_video_codecs_encode_array, 142 }; 143 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145 { 146 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147 .codec_array = sriov_sc_video_codecs_decode_array, 148 }; 149 150 /* Beige Goby*/ 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 153 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155 }; 156 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159 .codec_array = bg_video_codecs_decode_array, 160 }; 161 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163 .codec_count = 0, 164 .codec_array = NULL, 165 }; 166 167 /* Yellow Carp*/ 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 173 }; 174 175 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 176 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 177 .codec_array = yc_video_codecs_decode_array, 178 }; 179 180 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 181 const struct amdgpu_video_codecs **codecs) 182 { 183 switch (adev->ip_versions[UVD_HWIP][0]) { 184 case IP_VERSION(3, 0, 0): 185 if (amdgpu_sriov_vf(adev)) { 186 if (encode) 187 *codecs = &sriov_sc_video_codecs_encode; 188 else 189 *codecs = &sriov_sc_video_codecs_decode; 190 } else { 191 if (encode) 192 *codecs = &nv_video_codecs_encode; 193 else 194 *codecs = &sc_video_codecs_decode; 195 } 196 return 0; 197 case IP_VERSION(3, 0, 16): 198 case IP_VERSION(3, 0, 2): 199 if (encode) 200 *codecs = &nv_video_codecs_encode; 201 else 202 *codecs = &sc_video_codecs_decode; 203 return 0; 204 case IP_VERSION(3, 1, 1): 205 if (encode) 206 *codecs = &nv_video_codecs_encode; 207 else 208 *codecs = &yc_video_codecs_decode; 209 return 0; 210 case IP_VERSION(3, 0, 33): 211 if (encode) 212 *codecs = &bg_video_codecs_encode; 213 else 214 *codecs = &bg_video_codecs_decode; 215 return 0; 216 case IP_VERSION(2, 0, 0): 217 case IP_VERSION(2, 0, 2): 218 if (encode) 219 *codecs = &nv_video_codecs_encode; 220 else 221 *codecs = &nv_video_codecs_decode; 222 return 0; 223 default: 224 return -EINVAL; 225 } 226 } 227 228 /* 229 * Indirect registers accessor 230 */ 231 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 232 { 233 unsigned long address, data; 234 address = adev->nbio.funcs->get_pcie_index_offset(adev); 235 data = adev->nbio.funcs->get_pcie_data_offset(adev); 236 237 return amdgpu_device_indirect_rreg(adev, address, data, reg); 238 } 239 240 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 241 { 242 unsigned long address, data; 243 244 address = adev->nbio.funcs->get_pcie_index_offset(adev); 245 data = adev->nbio.funcs->get_pcie_data_offset(adev); 246 247 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 248 } 249 250 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 251 { 252 unsigned long address, data; 253 address = adev->nbio.funcs->get_pcie_index_offset(adev); 254 data = adev->nbio.funcs->get_pcie_data_offset(adev); 255 256 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 257 } 258 259 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 260 { 261 unsigned long flags, address, data; 262 u32 r; 263 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 264 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 265 266 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 267 WREG32(address, reg * 4); 268 (void)RREG32(address); 269 r = RREG32(data); 270 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 271 return r; 272 } 273 274 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 275 { 276 unsigned long address, data; 277 278 address = adev->nbio.funcs->get_pcie_index_offset(adev); 279 data = adev->nbio.funcs->get_pcie_data_offset(adev); 280 281 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 282 } 283 284 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 285 { 286 unsigned long flags, address, data; 287 288 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 289 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 290 291 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 292 WREG32(address, reg * 4); 293 (void)RREG32(address); 294 WREG32(data, v); 295 (void)RREG32(data); 296 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 297 } 298 299 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 300 { 301 unsigned long flags, address, data; 302 u32 r; 303 304 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 305 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 306 307 spin_lock_irqsave(&adev->didt_idx_lock, flags); 308 WREG32(address, (reg)); 309 r = RREG32(data); 310 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 311 return r; 312 } 313 314 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 315 { 316 unsigned long flags, address, data; 317 318 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 319 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 320 321 spin_lock_irqsave(&adev->didt_idx_lock, flags); 322 WREG32(address, (reg)); 323 WREG32(data, (v)); 324 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 325 } 326 327 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 328 { 329 return adev->nbio.funcs->get_memsize(adev); 330 } 331 332 static u32 nv_get_xclk(struct amdgpu_device *adev) 333 { 334 return adev->clock.spll.reference_freq; 335 } 336 337 338 void nv_grbm_select(struct amdgpu_device *adev, 339 u32 me, u32 pipe, u32 queue, u32 vmid) 340 { 341 u32 grbm_gfx_cntl = 0; 342 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 343 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 344 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 345 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 346 347 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 348 } 349 350 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 351 { 352 /* todo */ 353 } 354 355 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 356 { 357 /* todo */ 358 return false; 359 } 360 361 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 362 u8 *bios, u32 length_bytes) 363 { 364 u32 *dw_ptr; 365 u32 i, length_dw; 366 u32 rom_index_offset, rom_data_offset; 367 368 if (bios == NULL) 369 return false; 370 if (length_bytes == 0) 371 return false; 372 /* APU vbios image is part of sbios image */ 373 if (adev->flags & AMD_IS_APU) 374 return false; 375 376 dw_ptr = (u32 *)bios; 377 length_dw = ALIGN(length_bytes, 4) / 4; 378 379 rom_index_offset = 380 adev->smuio.funcs->get_rom_index_offset(adev); 381 rom_data_offset = 382 adev->smuio.funcs->get_rom_data_offset(adev); 383 384 /* set rom index to 0 */ 385 WREG32(rom_index_offset, 0); 386 /* read out the rom data */ 387 for (i = 0; i < length_dw; i++) 388 dw_ptr[i] = RREG32(rom_data_offset); 389 390 return true; 391 } 392 393 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 394 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 395 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 396 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 397 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 398 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 399 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 400 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 401 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 402 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 403 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 404 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 405 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 406 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 407 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 408 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 409 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 410 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 411 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 412 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 413 }; 414 415 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 416 u32 sh_num, u32 reg_offset) 417 { 418 uint32_t val; 419 420 mutex_lock(&adev->grbm_idx_mutex); 421 if (se_num != 0xffffffff || sh_num != 0xffffffff) 422 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 423 424 val = RREG32(reg_offset); 425 426 if (se_num != 0xffffffff || sh_num != 0xffffffff) 427 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 428 mutex_unlock(&adev->grbm_idx_mutex); 429 return val; 430 } 431 432 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 433 bool indexed, u32 se_num, 434 u32 sh_num, u32 reg_offset) 435 { 436 if (indexed) { 437 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 438 } else { 439 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 440 return adev->gfx.config.gb_addr_config; 441 return RREG32(reg_offset); 442 } 443 } 444 445 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 446 u32 sh_num, u32 reg_offset, u32 *value) 447 { 448 uint32_t i; 449 struct soc15_allowed_register_entry *en; 450 451 *value = 0; 452 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 453 en = &nv_allowed_read_registers[i]; 454 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 455 reg_offset != 456 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 457 continue; 458 459 *value = nv_get_register_value(adev, 460 nv_allowed_read_registers[i].grbm_indexed, 461 se_num, sh_num, reg_offset); 462 return 0; 463 } 464 return -EINVAL; 465 } 466 467 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 468 { 469 u32 i; 470 int ret = 0; 471 472 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 473 474 /* disable BM */ 475 pci_clear_master(adev->pdev); 476 477 amdgpu_device_cache_pci_state(adev->pdev); 478 479 ret = amdgpu_dpm_mode2_reset(adev); 480 if (ret) 481 dev_err(adev->dev, "GPU mode2 reset failed\n"); 482 483 amdgpu_device_load_pci_state(adev->pdev); 484 485 /* wait for asic to come out of reset */ 486 for (i = 0; i < adev->usec_timeout; i++) { 487 u32 memsize = adev->nbio.funcs->get_memsize(adev); 488 489 if (memsize != 0xffffffff) 490 break; 491 udelay(1); 492 } 493 494 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 495 496 return ret; 497 } 498 499 static enum amd_reset_method 500 nv_asic_reset_method(struct amdgpu_device *adev) 501 { 502 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 503 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 504 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 505 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 506 return amdgpu_reset_method; 507 508 if (amdgpu_reset_method != -1) 509 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 510 amdgpu_reset_method); 511 512 switch (adev->ip_versions[MP1_HWIP][0]) { 513 case IP_VERSION(11, 5, 0): 514 case IP_VERSION(13, 0, 1): 515 case IP_VERSION(13, 0, 3): 516 return AMD_RESET_METHOD_MODE2; 517 case IP_VERSION(11, 0, 7): 518 case IP_VERSION(11, 0, 11): 519 case IP_VERSION(11, 0, 12): 520 case IP_VERSION(11, 0, 13): 521 return AMD_RESET_METHOD_MODE1; 522 default: 523 if (amdgpu_dpm_is_baco_supported(adev)) 524 return AMD_RESET_METHOD_BACO; 525 else 526 return AMD_RESET_METHOD_MODE1; 527 } 528 } 529 530 static int nv_asic_reset(struct amdgpu_device *adev) 531 { 532 int ret = 0; 533 534 switch (nv_asic_reset_method(adev)) { 535 case AMD_RESET_METHOD_PCI: 536 dev_info(adev->dev, "PCI reset\n"); 537 ret = amdgpu_device_pci_reset(adev); 538 break; 539 case AMD_RESET_METHOD_BACO: 540 dev_info(adev->dev, "BACO reset\n"); 541 ret = amdgpu_dpm_baco_reset(adev); 542 break; 543 case AMD_RESET_METHOD_MODE2: 544 dev_info(adev->dev, "MODE2 reset\n"); 545 ret = nv_asic_mode2_reset(adev); 546 break; 547 default: 548 dev_info(adev->dev, "MODE1 reset\n"); 549 ret = amdgpu_device_mode1_reset(adev); 550 break; 551 } 552 553 return ret; 554 } 555 556 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 557 { 558 /* todo */ 559 return 0; 560 } 561 562 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 563 { 564 /* todo */ 565 return 0; 566 } 567 568 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 569 { 570 if (pci_is_root_bus(adev->pdev->bus)) 571 return; 572 573 if (amdgpu_pcie_gen2 == 0) 574 return; 575 576 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 577 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 578 return; 579 580 /* todo */ 581 } 582 583 static void nv_program_aspm(struct amdgpu_device *adev) 584 { 585 if (!amdgpu_aspm) 586 return; 587 588 if (!(adev->flags & AMD_IS_APU) && 589 (adev->nbio.funcs->program_aspm)) 590 adev->nbio.funcs->program_aspm(adev); 591 592 } 593 594 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 595 bool enable) 596 { 597 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 598 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 599 } 600 601 const struct amdgpu_ip_block_version nv_common_ip_block = 602 { 603 .type = AMD_IP_BLOCK_TYPE_COMMON, 604 .major = 1, 605 .minor = 0, 606 .rev = 0, 607 .funcs = &nv_common_ip_funcs, 608 }; 609 610 static int nv_reg_base_init(struct amdgpu_device *adev) 611 { 612 int r; 613 614 if (amdgpu_discovery) { 615 r = amdgpu_discovery_reg_base_init(adev); 616 if (r) { 617 DRM_WARN("failed to init reg base from ip discovery table, " 618 "fallback to legacy init method\n"); 619 goto legacy_init; 620 } 621 622 amdgpu_discovery_harvest_ip(adev); 623 624 return 0; 625 } 626 627 legacy_init: 628 switch (adev->asic_type) { 629 case CHIP_NAVI10: 630 navi10_reg_base_init(adev); 631 break; 632 case CHIP_NAVI14: 633 navi14_reg_base_init(adev); 634 break; 635 case CHIP_NAVI12: 636 navi12_reg_base_init(adev); 637 break; 638 case CHIP_SIENNA_CICHLID: 639 case CHIP_NAVY_FLOUNDER: 640 sienna_cichlid_reg_base_init(adev); 641 break; 642 case CHIP_VANGOGH: 643 vangogh_reg_base_init(adev); 644 break; 645 case CHIP_DIMGREY_CAVEFISH: 646 dimgrey_cavefish_reg_base_init(adev); 647 break; 648 case CHIP_BEIGE_GOBY: 649 beige_goby_reg_base_init(adev); 650 break; 651 case CHIP_YELLOW_CARP: 652 yellow_carp_reg_base_init(adev); 653 break; 654 case CHIP_CYAN_SKILLFISH: 655 cyan_skillfish_reg_base_init(adev); 656 break; 657 default: 658 return -EINVAL; 659 } 660 661 return 0; 662 } 663 664 void nv_set_virt_ops(struct amdgpu_device *adev) 665 { 666 adev->virt.ops = &xgpu_nv_virt_ops; 667 } 668 669 int nv_set_ip_blocks(struct amdgpu_device *adev) 670 { 671 int r; 672 673 if (adev->asic_type == CHIP_CYAN_SKILLFISH) { 674 adev->nbio.funcs = &nbio_v2_3_funcs; 675 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 676 } else if (adev->flags & AMD_IS_APU) { 677 adev->nbio.funcs = &nbio_v7_2_funcs; 678 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 679 } else { 680 adev->nbio.funcs = &nbio_v2_3_funcs; 681 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 682 } 683 adev->hdp.funcs = &hdp_v5_0_funcs; 684 685 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 686 adev->smuio.funcs = &smuio_v11_0_6_funcs; 687 else 688 adev->smuio.funcs = &smuio_v11_0_funcs; 689 690 if (adev->asic_type == CHIP_SIENNA_CICHLID) 691 adev->gmc.xgmi.supported = true; 692 693 /* Set IP register base before any HW register access */ 694 r = nv_reg_base_init(adev); 695 if (r) 696 return r; 697 698 switch (adev->asic_type) { 699 case CHIP_NAVI10: 700 case CHIP_NAVI14: 701 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 702 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 703 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 704 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 705 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 706 !amdgpu_sriov_vf(adev)) 707 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 708 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 709 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 710 #if defined(CONFIG_DRM_AMD_DC) 711 else if (amdgpu_device_has_dc_support(adev)) 712 amdgpu_device_ip_block_add(adev, &dm_ip_block); 713 #endif 714 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 715 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 716 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 717 !amdgpu_sriov_vf(adev)) 718 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 719 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 720 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 721 if (adev->enable_mes) 722 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 723 break; 724 case CHIP_NAVI12: 725 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 726 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 727 if (!amdgpu_sriov_vf(adev)) { 728 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 729 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 730 } else { 731 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 732 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 733 } 734 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 735 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 736 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 737 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 738 #if defined(CONFIG_DRM_AMD_DC) 739 else if (amdgpu_device_has_dc_support(adev)) 740 amdgpu_device_ip_block_add(adev, &dm_ip_block); 741 #endif 742 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 743 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 744 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 745 !amdgpu_sriov_vf(adev)) 746 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 747 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 748 if (!amdgpu_sriov_vf(adev)) 749 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 750 break; 751 case CHIP_SIENNA_CICHLID: 752 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 753 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 754 if (!amdgpu_sriov_vf(adev)) { 755 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 756 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 757 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 758 } else { 759 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 760 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 761 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 762 } 763 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 764 is_support_sw_smu(adev)) 765 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 766 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 767 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 768 #if defined(CONFIG_DRM_AMD_DC) 769 else if (amdgpu_device_has_dc_support(adev)) 770 amdgpu_device_ip_block_add(adev, &dm_ip_block); 771 #endif 772 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 773 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 774 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 775 if (!amdgpu_sriov_vf(adev)) 776 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 777 if (adev->enable_mes) 778 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 779 break; 780 case CHIP_NAVY_FLOUNDER: 781 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 782 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 783 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 784 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 785 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 786 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 787 is_support_sw_smu(adev)) 788 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 789 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 790 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 791 #if defined(CONFIG_DRM_AMD_DC) 792 else if (amdgpu_device_has_dc_support(adev)) 793 amdgpu_device_ip_block_add(adev, &dm_ip_block); 794 #endif 795 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 796 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 797 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 798 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 799 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 800 is_support_sw_smu(adev)) 801 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 802 break; 803 case CHIP_VANGOGH: 804 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 805 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 806 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 807 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 808 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 809 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 810 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 811 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 812 #if defined(CONFIG_DRM_AMD_DC) 813 else if (amdgpu_device_has_dc_support(adev)) 814 amdgpu_device_ip_block_add(adev, &dm_ip_block); 815 #endif 816 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 817 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 818 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 819 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 820 break; 821 case CHIP_DIMGREY_CAVEFISH: 822 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 823 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 824 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 825 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 826 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 827 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 828 is_support_sw_smu(adev)) 829 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 830 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 831 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 832 #if defined(CONFIG_DRM_AMD_DC) 833 else if (amdgpu_device_has_dc_support(adev)) 834 amdgpu_device_ip_block_add(adev, &dm_ip_block); 835 #endif 836 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 837 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 838 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 839 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 840 break; 841 case CHIP_BEIGE_GOBY: 842 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 843 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 844 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 845 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 846 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 847 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 848 is_support_sw_smu(adev)) 849 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 850 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 851 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 852 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 853 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 854 #if defined(CONFIG_DRM_AMD_DC) 855 else if (amdgpu_device_has_dc_support(adev)) 856 amdgpu_device_ip_block_add(adev, &dm_ip_block); 857 #endif 858 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 859 is_support_sw_smu(adev)) 860 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 861 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 862 break; 863 case CHIP_YELLOW_CARP: 864 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 865 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 866 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 867 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 868 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 869 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 870 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 871 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 872 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 873 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 874 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 875 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 876 #if defined(CONFIG_DRM_AMD_DC) 877 else if (amdgpu_device_has_dc_support(adev)) 878 amdgpu_device_ip_block_add(adev, &dm_ip_block); 879 #endif 880 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 881 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 882 break; 883 case CHIP_CYAN_SKILLFISH: 884 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 885 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 886 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 887 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 888 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 889 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 890 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 891 } 892 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 893 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 894 #if defined(CONFIG_DRM_AMD_DC) 895 else if (amdgpu_device_has_dc_support(adev)) 896 amdgpu_device_ip_block_add(adev, &dm_ip_block); 897 #endif 898 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 899 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 return 0; 906 } 907 908 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 909 { 910 return adev->nbio.funcs->get_rev_id(adev); 911 } 912 913 static bool nv_need_full_reset(struct amdgpu_device *adev) 914 { 915 return true; 916 } 917 918 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 919 { 920 u32 sol_reg; 921 922 if (adev->flags & AMD_IS_APU) 923 return false; 924 925 /* Check sOS sign of life register to confirm sys driver and sOS 926 * are already been loaded. 927 */ 928 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 929 if (sol_reg) 930 return true; 931 932 return false; 933 } 934 935 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 936 { 937 938 /* TODO 939 * dummy implement for pcie_replay_count sysfs interface 940 * */ 941 942 return 0; 943 } 944 945 static void nv_init_doorbell_index(struct amdgpu_device *adev) 946 { 947 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 948 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 949 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 950 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 951 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 952 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 953 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 954 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 955 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 956 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 957 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 958 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 959 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 960 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 961 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 962 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 963 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 964 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 965 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 966 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 967 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 968 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 969 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 970 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 971 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 972 973 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 974 adev->doorbell_index.sdma_doorbell_range = 20; 975 } 976 977 static void nv_pre_asic_init(struct amdgpu_device *adev) 978 { 979 } 980 981 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 982 bool enter) 983 { 984 if (enter) 985 amdgpu_gfx_rlc_enter_safe_mode(adev); 986 else 987 amdgpu_gfx_rlc_exit_safe_mode(adev); 988 989 if (adev->gfx.funcs->update_perfmon_mgcg) 990 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 991 992 if (!(adev->flags & AMD_IS_APU) && 993 (adev->nbio.funcs->enable_aspm)) 994 adev->nbio.funcs->enable_aspm(adev, !enter); 995 996 return 0; 997 } 998 999 static const struct amdgpu_asic_funcs nv_asic_funcs = 1000 { 1001 .read_disabled_bios = &nv_read_disabled_bios, 1002 .read_bios_from_rom = &nv_read_bios_from_rom, 1003 .read_register = &nv_read_register, 1004 .reset = &nv_asic_reset, 1005 .reset_method = &nv_asic_reset_method, 1006 .set_vga_state = &nv_vga_set_state, 1007 .get_xclk = &nv_get_xclk, 1008 .set_uvd_clocks = &nv_set_uvd_clocks, 1009 .set_vce_clocks = &nv_set_vce_clocks, 1010 .get_config_memsize = &nv_get_config_memsize, 1011 .init_doorbell_index = &nv_init_doorbell_index, 1012 .need_full_reset = &nv_need_full_reset, 1013 .need_reset_on_init = &nv_need_reset_on_init, 1014 .get_pcie_replay_count = &nv_get_pcie_replay_count, 1015 .supports_baco = &amdgpu_dpm_is_baco_supported, 1016 .pre_asic_init = &nv_pre_asic_init, 1017 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 1018 .query_video_codecs = &nv_query_video_codecs, 1019 }; 1020 1021 static int nv_common_early_init(void *handle) 1022 { 1023 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1025 1026 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1027 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1028 adev->smc_rreg = NULL; 1029 adev->smc_wreg = NULL; 1030 adev->pcie_rreg = &nv_pcie_rreg; 1031 adev->pcie_wreg = &nv_pcie_wreg; 1032 adev->pcie_rreg64 = &nv_pcie_rreg64; 1033 adev->pcie_wreg64 = &nv_pcie_wreg64; 1034 adev->pciep_rreg = &nv_pcie_port_rreg; 1035 adev->pciep_wreg = &nv_pcie_port_wreg; 1036 1037 /* TODO: will add them during VCN v2 implementation */ 1038 adev->uvd_ctx_rreg = NULL; 1039 adev->uvd_ctx_wreg = NULL; 1040 1041 adev->didt_rreg = &nv_didt_rreg; 1042 adev->didt_wreg = &nv_didt_wreg; 1043 1044 adev->asic_funcs = &nv_asic_funcs; 1045 1046 adev->rev_id = nv_get_rev_id(adev); 1047 adev->external_rev_id = 0xff; 1048 /* TODO: split the GC and PG flags based on the relevant IP version for which 1049 * they are relevant. 1050 */ 1051 switch (adev->ip_versions[GC_HWIP][0]) { 1052 case IP_VERSION(10, 1, 10): 1053 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1054 AMD_CG_SUPPORT_GFX_CGCG | 1055 AMD_CG_SUPPORT_IH_CG | 1056 AMD_CG_SUPPORT_HDP_MGCG | 1057 AMD_CG_SUPPORT_HDP_LS | 1058 AMD_CG_SUPPORT_SDMA_MGCG | 1059 AMD_CG_SUPPORT_SDMA_LS | 1060 AMD_CG_SUPPORT_MC_MGCG | 1061 AMD_CG_SUPPORT_MC_LS | 1062 AMD_CG_SUPPORT_ATHUB_MGCG | 1063 AMD_CG_SUPPORT_ATHUB_LS | 1064 AMD_CG_SUPPORT_VCN_MGCG | 1065 AMD_CG_SUPPORT_JPEG_MGCG | 1066 AMD_CG_SUPPORT_BIF_MGCG | 1067 AMD_CG_SUPPORT_BIF_LS; 1068 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1069 AMD_PG_SUPPORT_VCN_DPG | 1070 AMD_PG_SUPPORT_JPEG | 1071 AMD_PG_SUPPORT_ATHUB; 1072 adev->external_rev_id = adev->rev_id + 0x1; 1073 break; 1074 case IP_VERSION(10, 1, 1): 1075 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1076 AMD_CG_SUPPORT_GFX_CGCG | 1077 AMD_CG_SUPPORT_IH_CG | 1078 AMD_CG_SUPPORT_HDP_MGCG | 1079 AMD_CG_SUPPORT_HDP_LS | 1080 AMD_CG_SUPPORT_SDMA_MGCG | 1081 AMD_CG_SUPPORT_SDMA_LS | 1082 AMD_CG_SUPPORT_MC_MGCG | 1083 AMD_CG_SUPPORT_MC_LS | 1084 AMD_CG_SUPPORT_ATHUB_MGCG | 1085 AMD_CG_SUPPORT_ATHUB_LS | 1086 AMD_CG_SUPPORT_VCN_MGCG | 1087 AMD_CG_SUPPORT_JPEG_MGCG | 1088 AMD_CG_SUPPORT_BIF_MGCG | 1089 AMD_CG_SUPPORT_BIF_LS; 1090 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1091 AMD_PG_SUPPORT_JPEG | 1092 AMD_PG_SUPPORT_VCN_DPG; 1093 adev->external_rev_id = adev->rev_id + 20; 1094 break; 1095 case IP_VERSION(10, 1, 2): 1096 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1097 AMD_CG_SUPPORT_GFX_MGLS | 1098 AMD_CG_SUPPORT_GFX_CGCG | 1099 AMD_CG_SUPPORT_GFX_CP_LS | 1100 AMD_CG_SUPPORT_GFX_RLC_LS | 1101 AMD_CG_SUPPORT_IH_CG | 1102 AMD_CG_SUPPORT_HDP_MGCG | 1103 AMD_CG_SUPPORT_HDP_LS | 1104 AMD_CG_SUPPORT_SDMA_MGCG | 1105 AMD_CG_SUPPORT_SDMA_LS | 1106 AMD_CG_SUPPORT_MC_MGCG | 1107 AMD_CG_SUPPORT_MC_LS | 1108 AMD_CG_SUPPORT_ATHUB_MGCG | 1109 AMD_CG_SUPPORT_ATHUB_LS | 1110 AMD_CG_SUPPORT_VCN_MGCG | 1111 AMD_CG_SUPPORT_JPEG_MGCG; 1112 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1113 AMD_PG_SUPPORT_VCN_DPG | 1114 AMD_PG_SUPPORT_JPEG | 1115 AMD_PG_SUPPORT_ATHUB; 1116 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 1117 * as a consequence, the rev_id and external_rev_id are wrong. 1118 * workaround it by hardcoding rev_id to 0 (default value). 1119 */ 1120 if (amdgpu_sriov_vf(adev)) 1121 adev->rev_id = 0; 1122 adev->external_rev_id = adev->rev_id + 0xa; 1123 break; 1124 case IP_VERSION(10, 3, 0): 1125 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1126 AMD_CG_SUPPORT_GFX_CGCG | 1127 AMD_CG_SUPPORT_GFX_CGLS | 1128 AMD_CG_SUPPORT_GFX_3D_CGCG | 1129 AMD_CG_SUPPORT_MC_MGCG | 1130 AMD_CG_SUPPORT_VCN_MGCG | 1131 AMD_CG_SUPPORT_JPEG_MGCG | 1132 AMD_CG_SUPPORT_HDP_MGCG | 1133 AMD_CG_SUPPORT_HDP_LS | 1134 AMD_CG_SUPPORT_IH_CG | 1135 AMD_CG_SUPPORT_MC_LS; 1136 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1137 AMD_PG_SUPPORT_VCN_DPG | 1138 AMD_PG_SUPPORT_JPEG | 1139 AMD_PG_SUPPORT_ATHUB | 1140 AMD_PG_SUPPORT_MMHUB; 1141 if (amdgpu_sriov_vf(adev)) { 1142 /* hypervisor control CG and PG enablement */ 1143 adev->cg_flags = 0; 1144 adev->pg_flags = 0; 1145 } 1146 adev->external_rev_id = adev->rev_id + 0x28; 1147 break; 1148 case IP_VERSION(10, 3, 2): 1149 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1150 AMD_CG_SUPPORT_GFX_CGCG | 1151 AMD_CG_SUPPORT_GFX_CGLS | 1152 AMD_CG_SUPPORT_GFX_3D_CGCG | 1153 AMD_CG_SUPPORT_VCN_MGCG | 1154 AMD_CG_SUPPORT_JPEG_MGCG | 1155 AMD_CG_SUPPORT_MC_MGCG | 1156 AMD_CG_SUPPORT_MC_LS | 1157 AMD_CG_SUPPORT_HDP_MGCG | 1158 AMD_CG_SUPPORT_HDP_LS | 1159 AMD_CG_SUPPORT_IH_CG; 1160 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1161 AMD_PG_SUPPORT_VCN_DPG | 1162 AMD_PG_SUPPORT_JPEG | 1163 AMD_PG_SUPPORT_ATHUB | 1164 AMD_PG_SUPPORT_MMHUB; 1165 adev->external_rev_id = adev->rev_id + 0x32; 1166 break; 1167 case IP_VERSION(10, 3, 1): 1168 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1169 AMD_CG_SUPPORT_GFX_MGLS | 1170 AMD_CG_SUPPORT_GFX_CP_LS | 1171 AMD_CG_SUPPORT_GFX_RLC_LS | 1172 AMD_CG_SUPPORT_GFX_CGCG | 1173 AMD_CG_SUPPORT_GFX_CGLS | 1174 AMD_CG_SUPPORT_GFX_3D_CGCG | 1175 AMD_CG_SUPPORT_GFX_3D_CGLS | 1176 AMD_CG_SUPPORT_MC_MGCG | 1177 AMD_CG_SUPPORT_MC_LS | 1178 AMD_CG_SUPPORT_GFX_FGCG | 1179 AMD_CG_SUPPORT_VCN_MGCG | 1180 AMD_CG_SUPPORT_SDMA_MGCG | 1181 AMD_CG_SUPPORT_SDMA_LS | 1182 AMD_CG_SUPPORT_JPEG_MGCG; 1183 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1184 AMD_PG_SUPPORT_VCN | 1185 AMD_PG_SUPPORT_VCN_DPG | 1186 AMD_PG_SUPPORT_JPEG; 1187 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 1188 adev->external_rev_id = adev->rev_id + 0x01; 1189 break; 1190 case IP_VERSION(10, 3, 4): 1191 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1192 AMD_CG_SUPPORT_GFX_CGCG | 1193 AMD_CG_SUPPORT_GFX_CGLS | 1194 AMD_CG_SUPPORT_GFX_3D_CGCG | 1195 AMD_CG_SUPPORT_VCN_MGCG | 1196 AMD_CG_SUPPORT_JPEG_MGCG | 1197 AMD_CG_SUPPORT_MC_MGCG | 1198 AMD_CG_SUPPORT_MC_LS | 1199 AMD_CG_SUPPORT_HDP_MGCG | 1200 AMD_CG_SUPPORT_HDP_LS | 1201 AMD_CG_SUPPORT_IH_CG; 1202 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1203 AMD_PG_SUPPORT_VCN_DPG | 1204 AMD_PG_SUPPORT_JPEG | 1205 AMD_PG_SUPPORT_ATHUB | 1206 AMD_PG_SUPPORT_MMHUB; 1207 adev->external_rev_id = adev->rev_id + 0x3c; 1208 break; 1209 case IP_VERSION(10, 3, 5): 1210 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1211 AMD_CG_SUPPORT_GFX_CGCG | 1212 AMD_CG_SUPPORT_GFX_CGLS | 1213 AMD_CG_SUPPORT_GFX_3D_CGCG | 1214 AMD_CG_SUPPORT_MC_MGCG | 1215 AMD_CG_SUPPORT_MC_LS | 1216 AMD_CG_SUPPORT_HDP_MGCG | 1217 AMD_CG_SUPPORT_HDP_LS | 1218 AMD_CG_SUPPORT_IH_CG | 1219 AMD_CG_SUPPORT_VCN_MGCG; 1220 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1221 AMD_PG_SUPPORT_VCN_DPG | 1222 AMD_PG_SUPPORT_ATHUB | 1223 AMD_PG_SUPPORT_MMHUB; 1224 adev->external_rev_id = adev->rev_id + 0x46; 1225 break; 1226 case IP_VERSION(10, 3, 3): 1227 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1228 AMD_CG_SUPPORT_GFX_MGLS | 1229 AMD_CG_SUPPORT_GFX_CGCG | 1230 AMD_CG_SUPPORT_GFX_CGLS | 1231 AMD_CG_SUPPORT_GFX_3D_CGCG | 1232 AMD_CG_SUPPORT_GFX_3D_CGLS | 1233 AMD_CG_SUPPORT_GFX_RLC_LS | 1234 AMD_CG_SUPPORT_GFX_CP_LS | 1235 AMD_CG_SUPPORT_GFX_FGCG | 1236 AMD_CG_SUPPORT_MC_MGCG | 1237 AMD_CG_SUPPORT_MC_LS | 1238 AMD_CG_SUPPORT_SDMA_LS | 1239 AMD_CG_SUPPORT_HDP_MGCG | 1240 AMD_CG_SUPPORT_HDP_LS | 1241 AMD_CG_SUPPORT_ATHUB_MGCG | 1242 AMD_CG_SUPPORT_ATHUB_LS | 1243 AMD_CG_SUPPORT_IH_CG | 1244 AMD_CG_SUPPORT_VCN_MGCG | 1245 AMD_CG_SUPPORT_JPEG_MGCG; 1246 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1247 AMD_PG_SUPPORT_VCN | 1248 AMD_PG_SUPPORT_VCN_DPG | 1249 AMD_PG_SUPPORT_JPEG; 1250 if (adev->pdev->device == 0x1681) 1251 adev->external_rev_id = adev->rev_id + 0x19; 1252 else 1253 adev->external_rev_id = adev->rev_id + 0x01; 1254 break; 1255 case IP_VERSION(10, 1, 3): 1256 adev->cg_flags = 0; 1257 adev->pg_flags = 0; 1258 adev->external_rev_id = adev->rev_id + 0x82; 1259 break; 1260 default: 1261 /* FIXME: not supported yet */ 1262 return -EINVAL; 1263 } 1264 1265 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 1266 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 1267 AMD_PG_SUPPORT_VCN_DPG | 1268 AMD_PG_SUPPORT_JPEG); 1269 1270 if (amdgpu_sriov_vf(adev)) { 1271 amdgpu_virt_init_setting(adev); 1272 xgpu_nv_mailbox_set_irq_funcs(adev); 1273 } 1274 1275 return 0; 1276 } 1277 1278 static int nv_common_late_init(void *handle) 1279 { 1280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1281 1282 if (amdgpu_sriov_vf(adev)) { 1283 xgpu_nv_mailbox_get_irq(adev); 1284 amdgpu_virt_update_sriov_video_codec(adev, 1285 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 1286 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 1287 } 1288 1289 return 0; 1290 } 1291 1292 static int nv_common_sw_init(void *handle) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 1296 if (amdgpu_sriov_vf(adev)) 1297 xgpu_nv_mailbox_add_irq_id(adev); 1298 1299 return 0; 1300 } 1301 1302 static int nv_common_sw_fini(void *handle) 1303 { 1304 return 0; 1305 } 1306 1307 static int nv_common_hw_init(void *handle) 1308 { 1309 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1310 1311 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 1312 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 1313 1314 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1315 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1316 1317 /* enable pcie gen2/3 link */ 1318 nv_pcie_gen3_enable(adev); 1319 /* enable aspm */ 1320 nv_program_aspm(adev); 1321 /* setup nbio registers */ 1322 adev->nbio.funcs->init_registers(adev); 1323 /* remap HDP registers to a hole in mmio space, 1324 * for the purpose of expose those registers 1325 * to process space 1326 */ 1327 if (adev->nbio.funcs->remap_hdp_registers) 1328 adev->nbio.funcs->remap_hdp_registers(adev); 1329 /* enable the doorbell aperture */ 1330 nv_enable_doorbell_aperture(adev, true); 1331 1332 return 0; 1333 } 1334 1335 static int nv_common_hw_fini(void *handle) 1336 { 1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1338 1339 /* disable the doorbell aperture */ 1340 nv_enable_doorbell_aperture(adev, false); 1341 1342 return 0; 1343 } 1344 1345 static int nv_common_suspend(void *handle) 1346 { 1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1348 1349 return nv_common_hw_fini(adev); 1350 } 1351 1352 static int nv_common_resume(void *handle) 1353 { 1354 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1355 1356 return nv_common_hw_init(adev); 1357 } 1358 1359 static bool nv_common_is_idle(void *handle) 1360 { 1361 return true; 1362 } 1363 1364 static int nv_common_wait_for_idle(void *handle) 1365 { 1366 return 0; 1367 } 1368 1369 static int nv_common_soft_reset(void *handle) 1370 { 1371 return 0; 1372 } 1373 1374 static int nv_common_set_clockgating_state(void *handle, 1375 enum amd_clockgating_state state) 1376 { 1377 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1378 1379 if (amdgpu_sriov_vf(adev)) 1380 return 0; 1381 1382 switch (adev->ip_versions[NBIO_HWIP][0]) { 1383 case IP_VERSION(2, 3, 0): 1384 case IP_VERSION(2, 3, 1): 1385 case IP_VERSION(2, 3, 2): 1386 case IP_VERSION(3, 3, 0): 1387 case IP_VERSION(3, 3, 1): 1388 case IP_VERSION(3, 3, 2): 1389 case IP_VERSION(3, 3, 3): 1390 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1391 state == AMD_CG_STATE_GATE); 1392 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1393 state == AMD_CG_STATE_GATE); 1394 adev->hdp.funcs->update_clock_gating(adev, 1395 state == AMD_CG_STATE_GATE); 1396 adev->smuio.funcs->update_rom_clock_gating(adev, 1397 state == AMD_CG_STATE_GATE); 1398 break; 1399 default: 1400 break; 1401 } 1402 return 0; 1403 } 1404 1405 static int nv_common_set_powergating_state(void *handle, 1406 enum amd_powergating_state state) 1407 { 1408 /* TODO */ 1409 return 0; 1410 } 1411 1412 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1413 { 1414 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1415 1416 if (amdgpu_sriov_vf(adev)) 1417 *flags = 0; 1418 1419 adev->nbio.funcs->get_clockgating_state(adev, flags); 1420 1421 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1422 1423 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1424 1425 return; 1426 } 1427 1428 static const struct amd_ip_funcs nv_common_ip_funcs = { 1429 .name = "nv_common", 1430 .early_init = nv_common_early_init, 1431 .late_init = nv_common_late_init, 1432 .sw_init = nv_common_sw_init, 1433 .sw_fini = nv_common_sw_fini, 1434 .hw_init = nv_common_hw_init, 1435 .hw_fini = nv_common_hw_fini, 1436 .suspend = nv_common_suspend, 1437 .resume = nv_common_resume, 1438 .is_idle = nv_common_is_idle, 1439 .wait_for_idle = nv_common_wait_for_idle, 1440 .soft_reset = nv_common_soft_reset, 1441 .set_clockgating_state = nv_common_set_clockgating_state, 1442 .set_powergating_state = nv_common_set_powergating_state, 1443 .get_clockgating_state = nv_common_get_clockgating_state, 1444 }; 1445