clkc.c (58b0fb86260063f86afecaebf4056c876fff2a19) clkc.c (e605fa9c4a0c1218e5604b42bef59de0a3a4f813)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Zynq UltraScale+ MPSoC clock controller
4 *
5 * Copyright (C) 2016-2019 Xilinx
6 *
7 * Based on drivers/clk/zynq/clkc.c
8 */

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79};
80
81struct name_resp {
82 char name[CLK_GET_NAME_RESP_LEN];
83};
84
85struct topology_resp {
86#define CLK_TOPOLOGY_TYPE GENMASK(3, 0)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Zynq UltraScale+ MPSoC clock controller
4 *
5 * Copyright (C) 2016-2019 Xilinx
6 *
7 * Based on drivers/clk/zynq/clkc.c
8 */

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79};
80
81struct name_resp {
82 char name[CLK_GET_NAME_RESP_LEN];
83};
84
85struct topology_resp {
86#define CLK_TOPOLOGY_TYPE GENMASK(3, 0)
87#define CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS GENMASK(7, 4)
87#define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
88#define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24)
89 u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
90};
91
92struct parents_resp {
93#define NA_PARENT 0xFFFFFFFF
94#define DUMMY_PARENT 0xFFFFFFFE

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391 if (type == TYPE_INVALID)
392 return END_OF_TOPOLOGY_NODE;
393 topology[*nnodes].type = type;
394 topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS,
395 response->topology[i]);
396 topology[*nnodes].type_flag =
397 FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
398 response->topology[i]);
88#define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
89#define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24)
90 u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
91};
92
93struct parents_resp {
94#define NA_PARENT 0xFFFFFFFF
95#define DUMMY_PARENT 0xFFFFFFFE

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392 if (type == TYPE_INVALID)
393 return END_OF_TOPOLOGY_NODE;
394 topology[*nnodes].type = type;
395 topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS,
396 response->topology[i]);
397 topology[*nnodes].type_flag =
398 FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
399 response->topology[i]);
400 topology[*nnodes].custom_type_flag =
401 FIELD_GET(CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS,
402 response->topology[i]);
399 (*nnodes)++;
400 }
401
402 return 0;
403}
404
405/**
406 * zynqmp_clock_get_topology() - Get topology of clock from firmware using

--- 366 unchanged lines hidden --- 		403 (*nnodes)++;
404 }
405
406 return 0;
407}
408
409/**
410 * zynqmp_clock_get_topology() - Get topology of clock from firmware using

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