clk-hix5hd2.c (cc855dd9994cfd179891cf5b966ebc8051d95a9f) clk-hix5hd2.c (1463fba39c2e95803147e1d6e159ea402d965e6f)
1/*
2 * Copyright (c) 2014 Linaro Ltd.
3 * Copyright (c) 2014 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */

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90 CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
91 { HIX5HD2_MMC_CIU_RST, "rst_mmc_ciu", "clk_mmc_ciu",
92 CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, },
93 /* gsf */
94 { HIX5HD2_FWD_BUS_CLK, "clk_fwd_bus", NULL, 0, 0xcc, 0, 0, },
95 { HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, },
96 { HIX5HD2_MAC0_PHY_CLK, "clk_fephy", "clk_fwd_sys",
97 CLK_SET_RATE_PARENT, 0x120, 0, 0, },
1/*
2 * Copyright (c) 2014 Linaro Ltd.
3 * Copyright (c) 2014 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */

--- 81 unchanged lines hidden (view full) ---

90 CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
91 { HIX5HD2_MMC_CIU_RST, "rst_mmc_ciu", "clk_mmc_ciu",
92 CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, },
93 /* gsf */
94 { HIX5HD2_FWD_BUS_CLK, "clk_fwd_bus", NULL, 0, 0xcc, 0, 0, },
95 { HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, },
96 { HIX5HD2_MAC0_PHY_CLK, "clk_fephy", "clk_fwd_sys",
97 CLK_SET_RATE_PARENT, 0x120, 0, 0, },
98 /* wdg0 */
99 { HIX5HD2_WDG0_CLK, "clk_wdg0", "24m",
100 CLK_SET_RATE_PARENT, 0x178, 0, 0, },
101 { HIX5HD2_WDG0_RST, "rst_wdg0", "clk_wdg0",
102 CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, },
98};
99
100enum hix5hd2_clk_type {
101 TYPE_COMPLEX,
102 TYPE_ETHER,
103};
104
105struct hix5hd2_complex_clock {

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103};
104
105enum hix5hd2_clk_type {
106 TYPE_COMPLEX,
107 TYPE_ETHER,
108};
109
110struct hix5hd2_complex_clock {

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