1 /* 2 * Copyright (c) 2014 Linaro Ltd. 3 * Copyright (c) 2014 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 */ 9 10 #include <linux/of_address.h> 11 #include <dt-bindings/clock/hix5hd2-clock.h> 12 #include <linux/slab.h> 13 #include <linux/delay.h> 14 #include "clk.h" 15 16 static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = { 17 { HIX5HD2_FIXED_1200M, "1200m", NULL, CLK_IS_ROOT, 1200000000, }, 18 { HIX5HD2_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, }, 19 { HIX5HD2_FIXED_48M, "48m", NULL, CLK_IS_ROOT, 48000000, }, 20 { HIX5HD2_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, }, 21 { HIX5HD2_FIXED_600M, "600m", NULL, CLK_IS_ROOT, 600000000, }, 22 { HIX5HD2_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, }, 23 { HIX5HD2_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, }, 24 { HIX5HD2_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, }, 25 { HIX5HD2_FIXED_100M, "100m", NULL, CLK_IS_ROOT, 100000000, }, 26 { HIX5HD2_FIXED_40M, "40m", NULL, CLK_IS_ROOT, 40000000, }, 27 { HIX5HD2_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, }, 28 { HIX5HD2_FIXED_1728M, "1728m", NULL, CLK_IS_ROOT, 1728000000, }, 29 { HIX5HD2_FIXED_28P8M, "28p8m", NULL, CLK_IS_ROOT, 28000000, }, 30 { HIX5HD2_FIXED_432M, "432m", NULL, CLK_IS_ROOT, 432000000, }, 31 { HIX5HD2_FIXED_345P6M, "345p6m", NULL, CLK_IS_ROOT, 345000000, }, 32 { HIX5HD2_FIXED_288M, "288m", NULL, CLK_IS_ROOT, 288000000, }, 33 { HIX5HD2_FIXED_60M, "60m", NULL, CLK_IS_ROOT, 60000000, }, 34 { HIX5HD2_FIXED_750M, "750m", NULL, CLK_IS_ROOT, 750000000, }, 35 { HIX5HD2_FIXED_500M, "500m", NULL, CLK_IS_ROOT, 500000000, }, 36 { HIX5HD2_FIXED_54M, "54m", NULL, CLK_IS_ROOT, 54000000, }, 37 { HIX5HD2_FIXED_27M, "27m", NULL, CLK_IS_ROOT, 27000000, }, 38 { HIX5HD2_FIXED_1500M, "1500m", NULL, CLK_IS_ROOT, 1500000000, }, 39 { HIX5HD2_FIXED_375M, "375m", NULL, CLK_IS_ROOT, 375000000, }, 40 { HIX5HD2_FIXED_187M, "187m", NULL, CLK_IS_ROOT, 187000000, }, 41 { HIX5HD2_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, }, 42 { HIX5HD2_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, }, 43 { HIX5HD2_FIXED_2P02M, "2m", NULL, CLK_IS_ROOT, 2000000, }, 44 { HIX5HD2_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, }, 45 { HIX5HD2_FIXED_25M, "25m", NULL, CLK_IS_ROOT, 25000000, }, 46 { HIX5HD2_FIXED_83M, "83m", NULL, CLK_IS_ROOT, 83333333, }, 47 }; 48 49 static const char *sfc_mux_p[] __initconst = { 50 "24m", "150m", "200m", "100m", "75m", }; 51 static u32 sfc_mux_table[] = {0, 4, 5, 6, 7}; 52 53 static const char *sdio_mux_p[] __initconst = { 54 "75m", "100m", "50m", "15m", }; 55 static u32 sdio_mux_table[] = {0, 1, 2, 3}; 56 57 static const char *fephy_mux_p[] __initconst = { "25m", "125m"}; 58 static u32 fephy_mux_table[] = {0, 1}; 59 60 61 static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = { 62 { HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p), 63 CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, }, 64 { HIX5HD2_MMC_MUX, "mmc_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), 65 CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, }, 66 { HIX5HD2_SD_MUX, "sd_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), 67 CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, }, 68 { HIX5HD2_FEPHY_MUX, "fephy_mux", 69 fephy_mux_p, ARRAY_SIZE(fephy_mux_p), 70 CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, }, 71 }; 72 73 static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = { 74 /* sfc */ 75 { HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux", 76 CLK_SET_RATE_PARENT, 0x5c, 0, 0, }, 77 { HIX5HD2_SFC_RST, "rst_sfc", "clk_sfc", 78 CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, }, 79 /* sdio0 */ 80 { HIX5HD2_SD_BIU_CLK, "clk_sd_biu", "200m", 81 CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, 82 { HIX5HD2_SD_CIU_CLK, "clk_sd_ciu", "sd_mux", 83 CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, 84 { HIX5HD2_SD_CIU_RST, "rst_sd_ciu", "clk_sd_ciu", 85 CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, }, 86 /* sdio1 */ 87 { HIX5HD2_MMC_BIU_CLK, "clk_mmc_biu", "200m", 88 CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, 89 { HIX5HD2_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux", 90 CLK_SET_RATE_PARENT, 0xa0, 1, 0, }, 91 { HIX5HD2_MMC_CIU_RST, "rst_mmc_ciu", "clk_mmc_ciu", 92 CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, }, 93 /* gsf */ 94 { HIX5HD2_FWD_BUS_CLK, "clk_fwd_bus", NULL, 0, 0xcc, 0, 0, }, 95 { HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, }, 96 { HIX5HD2_MAC0_PHY_CLK, "clk_fephy", "clk_fwd_sys", 97 CLK_SET_RATE_PARENT, 0x120, 0, 0, }, 98 }; 99 100 enum hix5hd2_clk_type { 101 TYPE_COMPLEX, 102 TYPE_ETHER, 103 }; 104 105 struct hix5hd2_complex_clock { 106 const char *name; 107 const char *parent_name; 108 u32 id; 109 u32 ctrl_reg; 110 u32 ctrl_clk_mask; 111 u32 ctrl_rst_mask; 112 u32 phy_reg; 113 u32 phy_clk_mask; 114 u32 phy_rst_mask; 115 enum hix5hd2_clk_type type; 116 }; 117 118 struct hix5hd2_clk_complex { 119 struct clk_hw hw; 120 u32 id; 121 void __iomem *ctrl_reg; 122 u32 ctrl_clk_mask; 123 u32 ctrl_rst_mask; 124 void __iomem *phy_reg; 125 u32 phy_clk_mask; 126 u32 phy_rst_mask; 127 }; 128 129 static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata = { 130 {"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK, 131 0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER}, 132 {"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK, 133 0xcc, 0x14, 0xa00, 0x168, 0x2, 0, TYPE_ETHER}, 134 {"clk_sata", NULL, HIX5HD2_SATA_CLK, 135 0xa8, 0x1f, 0x300, 0xac, 0x1, 0x0, TYPE_COMPLEX}, 136 {"clk_usb", NULL, HIX5HD2_USB_CLK, 137 0xb8, 0xff, 0x3f000, 0xbc, 0x7, 0x3f00, TYPE_COMPLEX}, 138 }; 139 140 #define to_complex_clk(_hw) container_of(_hw, struct hix5hd2_clk_complex, hw) 141 142 static int clk_ether_prepare(struct clk_hw *hw) 143 { 144 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); 145 u32 val; 146 147 val = readl_relaxed(clk->ctrl_reg); 148 val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; 149 writel_relaxed(val, clk->ctrl_reg); 150 val &= ~(clk->ctrl_rst_mask); 151 writel_relaxed(val, clk->ctrl_reg); 152 153 val = readl_relaxed(clk->phy_reg); 154 val |= clk->phy_clk_mask; 155 val &= ~(clk->phy_rst_mask); 156 writel_relaxed(val, clk->phy_reg); 157 mdelay(10); 158 159 val &= ~(clk->phy_clk_mask); 160 val |= clk->phy_rst_mask; 161 writel_relaxed(val, clk->phy_reg); 162 mdelay(10); 163 164 val |= clk->phy_clk_mask; 165 val &= ~(clk->phy_rst_mask); 166 writel_relaxed(val, clk->phy_reg); 167 mdelay(30); 168 return 0; 169 } 170 171 static void clk_ether_unprepare(struct clk_hw *hw) 172 { 173 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); 174 u32 val; 175 176 val = readl_relaxed(clk->ctrl_reg); 177 val &= ~(clk->ctrl_clk_mask); 178 writel_relaxed(val, clk->ctrl_reg); 179 } 180 181 static struct clk_ops clk_ether_ops = { 182 .prepare = clk_ether_prepare, 183 .unprepare = clk_ether_unprepare, 184 }; 185 186 static int clk_complex_enable(struct clk_hw *hw) 187 { 188 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); 189 u32 val; 190 191 val = readl_relaxed(clk->ctrl_reg); 192 val |= clk->ctrl_clk_mask; 193 val &= ~(clk->ctrl_rst_mask); 194 writel_relaxed(val, clk->ctrl_reg); 195 196 val = readl_relaxed(clk->phy_reg); 197 val |= clk->phy_clk_mask; 198 val &= ~(clk->phy_rst_mask); 199 writel_relaxed(val, clk->phy_reg); 200 201 return 0; 202 } 203 204 static void clk_complex_disable(struct clk_hw *hw) 205 { 206 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); 207 u32 val; 208 209 val = readl_relaxed(clk->ctrl_reg); 210 val |= clk->ctrl_rst_mask; 211 val &= ~(clk->ctrl_clk_mask); 212 writel_relaxed(val, clk->ctrl_reg); 213 214 val = readl_relaxed(clk->phy_reg); 215 val |= clk->phy_rst_mask; 216 val &= ~(clk->phy_clk_mask); 217 writel_relaxed(val, clk->phy_reg); 218 } 219 220 static struct clk_ops clk_complex_ops = { 221 .enable = clk_complex_enable, 222 .disable = clk_complex_disable, 223 }; 224 225 void __init hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, 226 int nums, struct hisi_clock_data *data) 227 { 228 void __iomem *base = data->base; 229 int i; 230 231 for (i = 0; i < nums; i++) { 232 struct hix5hd2_clk_complex *p_clk; 233 struct clk *clk; 234 struct clk_init_data init; 235 236 p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL); 237 if (!p_clk) 238 return; 239 240 init.name = clks[i].name; 241 if (clks[i].type == TYPE_ETHER) 242 init.ops = &clk_ether_ops; 243 else 244 init.ops = &clk_complex_ops; 245 246 init.flags = CLK_IS_BASIC; 247 init.parent_names = 248 (clks[i].parent_name ? &clks[i].parent_name : NULL); 249 init.num_parents = (clks[i].parent_name ? 1 : 0); 250 251 p_clk->ctrl_reg = base + clks[i].ctrl_reg; 252 p_clk->ctrl_clk_mask = clks[i].ctrl_clk_mask; 253 p_clk->ctrl_rst_mask = clks[i].ctrl_rst_mask; 254 p_clk->phy_reg = base + clks[i].phy_reg; 255 p_clk->phy_clk_mask = clks[i].phy_clk_mask; 256 p_clk->phy_rst_mask = clks[i].phy_rst_mask; 257 p_clk->hw.init = &init; 258 259 clk = clk_register(NULL, &p_clk->hw); 260 if (IS_ERR(clk)) { 261 kfree(p_clk); 262 pr_err("%s: failed to register clock %s\n", 263 __func__, clks[i].name); 264 continue; 265 } 266 267 data->clk_data.clks[clks[i].id] = clk; 268 } 269 } 270 271 static void __init hix5hd2_clk_init(struct device_node *np) 272 { 273 struct hisi_clock_data *clk_data; 274 275 clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS); 276 if (!clk_data) 277 return; 278 279 hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks, 280 ARRAY_SIZE(hix5hd2_fixed_rate_clks), 281 clk_data); 282 hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks), 283 clk_data); 284 hisi_clk_register_gate(hix5hd2_gate_clks, 285 ARRAY_SIZE(hix5hd2_gate_clks), clk_data); 286 hix5hd2_clk_register_complex(hix5hd2_complex_clks, 287 ARRAY_SIZE(hix5hd2_complex_clks), 288 clk_data); 289 } 290 291 CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init); 292