smpboot.c (62b31a045757eac81fed94b19df47418a0818528) smpboot.c (e57d04e5fa00f7649d4c00796f8d12054799be4a)
1// SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *

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222 */
223 cr4_init();
224
225#ifdef CONFIG_X86_32
226 /* switch away from the initial page table */
227 load_cr3(swapper_pg_dir);
228 __flush_tlb_all();
229#endif
1// SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *

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222 */
223 cr4_init();
224
225#ifdef CONFIG_X86_32
226 /* switch away from the initial page table */
227 load_cr3(swapper_pg_dir);
228 __flush_tlb_all();
229#endif
230 load_current_idt();
230 cpu_init_exception_handling();
231 cpu_init();
232 x86_cpuinit.early_percpu_clock_init();
233 preempt_disable();
234 smp_callin();
235
236 enable_start_cpu0 = 0;
237
238 /* otherwise gcc will move up smp_processor_id before the cpu_init */

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742/*
743 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
744 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
745 * won't ... remember to clear down the APIC, etc later.
746 */
747int
748wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
749{
231 cpu_init();
232 x86_cpuinit.early_percpu_clock_init();
233 preempt_disable();
234 smp_callin();
235
236 enable_start_cpu0 = 0;
237
238 /* otherwise gcc will move up smp_processor_id before the cpu_init */

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742/*
743 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
744 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
745 * won't ... remember to clear down the APIC, etc later.
746 */
747int
748wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
749{
750 u32 dm = apic->irq_dest_mode ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
750 unsigned long send_status, accept_status = 0;
751 int maxlvt;
752
753 /* Target chip */
754 /* Boot on the stack */
755 /* Kick the second */
751 unsigned long send_status, accept_status = 0;
752 int maxlvt;
753
754 /* Target chip */
755 /* Boot on the stack */
756 /* Kick the second */
756 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
757 apic_icr_write(APIC_DM_NMI | dm, apicid);
757
758 pr_debug("Waiting for send to finish...\n");
759 send_status = safe_apic_wait_icr_idle();
760
761 /*
762 * Give the other CPU some time to accept the IPI.
763 */
764 udelay(200);

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975 * Register a NMI handler to help wake up CPU0.
976 */
977 boot_error = register_nmi_handler(NMI_LOCAL,
978 wakeup_cpu0_nmi, 0, "wake_cpu0");
979
980 if (!boot_error) {
981 enable_start_cpu0 = 1;
982 *cpu0_nmi_registered = 1;
758
759 pr_debug("Waiting for send to finish...\n");
760 send_status = safe_apic_wait_icr_idle();
761
762 /*
763 * Give the other CPU some time to accept the IPI.
764 */
765 udelay(200);

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976 * Register a NMI handler to help wake up CPU0.
977 */
978 boot_error = register_nmi_handler(NMI_LOCAL,
979 wakeup_cpu0_nmi, 0, "wake_cpu0");
980
981 if (!boot_error) {
982 enable_start_cpu0 = 1;
983 *cpu0_nmi_registered = 1;
983 if (apic->dest_logical == APIC_DEST_LOGICAL)
984 if (apic->irq_dest_mode)
984 id = cpu0_logical_apicid;
985 else
986 id = apicid;
987 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
988 }
989
990out:
991 preempt_enable();

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985 id = cpu0_logical_apicid;
986 else
987 id = apicid;
988 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
989 }
990
991out:
992 preempt_enable();

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