vcpu.c (e81af89baebf86938cda1a7c2bee51c676c04e21) vcpu.c (52ec4b695dbe0552bb994c4149e9122610a76668)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
4 *
5 * Authors:
6 * Anup Patel <anup.patel@wdc.com>
7 */
8

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16#include <linux/uaccess.h>
17#include <linux/vmalloc.h>
18#include <linux/sched/signal.h>
19#include <linux/fs.h>
20#include <linux/kvm_host.h>
21#include <asm/csr.h>
22#include <asm/cacheflush.h>
23#include <asm/hwcap.h>
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
4 *
5 * Authors:
6 * Anup Patel <anup.patel@wdc.com>
7 */
8

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16#include <linux/uaccess.h>
17#include <linux/vmalloc.h>
18#include <linux/sched/signal.h>
19#include <linux/fs.h>
20#include <linux/kvm_host.h>
21#include <asm/csr.h>
22#include <asm/cacheflush.h>
23#include <asm/hwcap.h>
24#include <asm/sbi.h>
24
25const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
26 KVM_GENERIC_VCPU_STATS(),
27 STATS_DESC_COUNTER(VCPU, ecall_exit_stat),
28 STATS_DESC_COUNTER(VCPU, wfi_exit_stat),
29 STATS_DESC_COUNTER(VCPU, mmio_exit_user),
30 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel),
31 STATS_DESC_COUNTER(VCPU, csr_exit_user),

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166 /* Setup ISA features available to VCPU */
167 for (i = 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) {
168 host_isa = kvm_isa_ext_arr[i];
169 if (__riscv_isa_extension_available(NULL, host_isa) &&
170 kvm_riscv_vcpu_isa_enable_allowed(i))
171 set_bit(host_isa, vcpu->arch.isa);
172 }
173
25
26const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
27 KVM_GENERIC_VCPU_STATS(),
28 STATS_DESC_COUNTER(VCPU, ecall_exit_stat),
29 STATS_DESC_COUNTER(VCPU, wfi_exit_stat),
30 STATS_DESC_COUNTER(VCPU, mmio_exit_user),
31 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel),
32 STATS_DESC_COUNTER(VCPU, csr_exit_user),

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167 /* Setup ISA features available to VCPU */
168 for (i = 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) {
169 host_isa = kvm_isa_ext_arr[i];
170 if (__riscv_isa_extension_available(NULL, host_isa) &&
171 kvm_riscv_vcpu_isa_enable_allowed(i))
172 set_bit(host_isa, vcpu->arch.isa);
173 }
174
175 /* Setup vendor, arch, and implementation details */
176 vcpu->arch.mvendorid = sbi_get_mvendorid();
177 vcpu->arch.marchid = sbi_get_marchid();
178 vcpu->arch.mimpid = sbi_get_mimpid();
179
174 /* Setup VCPU hfence queue */
175 spin_lock_init(&vcpu->arch.hfence_lock);
176
177 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */
178 cntx = &vcpu->arch.guest_reset_context;
179 cntx->sstatus = SR_SPP | SR_SPIE;
180 cntx->hstatus = 0;
181 cntx->hstatus |= HSTATUS_VTW;

--- 919 unchanged lines hidden --- 		180 /* Setup VCPU hfence queue */
181 spin_lock_init(&vcpu->arch.hfence_lock);
182
183 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */
184 cntx = &vcpu->arch.guest_reset_context;
185 cntx->sstatus = SR_SPP | SR_SPIE;
186 cntx->hstatus = 0;
187 cntx->hstatus |= HSTATUS_VTW;

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