1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/entry-kvm.h> 11 #include <linux/errno.h> 12 #include <linux/err.h> 13 #include <linux/kdebug.h> 14 #include <linux/module.h> 15 #include <linux/percpu.h> 16 #include <linux/uaccess.h> 17 #include <linux/vmalloc.h> 18 #include <linux/sched/signal.h> 19 #include <linux/fs.h> 20 #include <linux/kvm_host.h> 21 #include <asm/csr.h> 22 #include <asm/cacheflush.h> 23 #include <asm/hwcap.h> 24 #include <asm/sbi.h> 25 26 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 27 KVM_GENERIC_VCPU_STATS(), 28 STATS_DESC_COUNTER(VCPU, ecall_exit_stat), 29 STATS_DESC_COUNTER(VCPU, wfi_exit_stat), 30 STATS_DESC_COUNTER(VCPU, mmio_exit_user), 31 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel), 32 STATS_DESC_COUNTER(VCPU, csr_exit_user), 33 STATS_DESC_COUNTER(VCPU, csr_exit_kernel), 34 STATS_DESC_COUNTER(VCPU, signal_exits), 35 STATS_DESC_COUNTER(VCPU, exits) 36 }; 37 38 const struct kvm_stats_header kvm_vcpu_stats_header = { 39 .name_size = KVM_STATS_NAME_SIZE, 40 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 41 .id_offset = sizeof(struct kvm_stats_header), 42 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 43 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 44 sizeof(kvm_vcpu_stats_desc), 45 }; 46 47 #define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0) 48 49 #define KVM_ISA_EXT_ARR(ext) [KVM_RISCV_ISA_EXT_##ext] = RISCV_ISA_EXT_##ext 50 51 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */ 52 static const unsigned long kvm_isa_ext_arr[] = { 53 [KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_a, 54 [KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_c, 55 [KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_d, 56 [KVM_RISCV_ISA_EXT_F] = RISCV_ISA_EXT_f, 57 [KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h, 58 [KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i, 59 [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m, 60 61 KVM_ISA_EXT_ARR(SSTC), 62 KVM_ISA_EXT_ARR(SVINVAL), 63 KVM_ISA_EXT_ARR(SVPBMT), 64 KVM_ISA_EXT_ARR(ZIHINTPAUSE), 65 KVM_ISA_EXT_ARR(ZICBOM), 66 }; 67 68 static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext) 69 { 70 unsigned long i; 71 72 for (i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) { 73 if (kvm_isa_ext_arr[i] == base_ext) 74 return i; 75 } 76 77 return KVM_RISCV_ISA_EXT_MAX; 78 } 79 80 static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext) 81 { 82 switch (ext) { 83 case KVM_RISCV_ISA_EXT_H: 84 return false; 85 default: 86 break; 87 } 88 89 return true; 90 } 91 92 static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) 93 { 94 switch (ext) { 95 case KVM_RISCV_ISA_EXT_A: 96 case KVM_RISCV_ISA_EXT_C: 97 case KVM_RISCV_ISA_EXT_I: 98 case KVM_RISCV_ISA_EXT_M: 99 case KVM_RISCV_ISA_EXT_SSTC: 100 case KVM_RISCV_ISA_EXT_SVINVAL: 101 case KVM_RISCV_ISA_EXT_ZIHINTPAUSE: 102 return false; 103 default: 104 break; 105 } 106 107 return true; 108 } 109 110 static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) 111 { 112 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 113 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; 114 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 115 struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context; 116 bool loaded; 117 118 /** 119 * The preemption should be disabled here because it races with 120 * kvm_sched_out/kvm_sched_in(called from preempt notifiers) which 121 * also calls vcpu_load/put. 122 */ 123 get_cpu(); 124 loaded = (vcpu->cpu != -1); 125 if (loaded) 126 kvm_arch_vcpu_put(vcpu); 127 128 vcpu->arch.last_exit_cpu = -1; 129 130 memcpy(csr, reset_csr, sizeof(*csr)); 131 132 memcpy(cntx, reset_cntx, sizeof(*cntx)); 133 134 kvm_riscv_vcpu_fp_reset(vcpu); 135 136 kvm_riscv_vcpu_timer_reset(vcpu); 137 138 WRITE_ONCE(vcpu->arch.irqs_pending, 0); 139 WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); 140 141 vcpu->arch.hfence_head = 0; 142 vcpu->arch.hfence_tail = 0; 143 memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue)); 144 145 /* Reset the guest CSRs for hotplug usecase */ 146 if (loaded) 147 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 148 put_cpu(); 149 } 150 151 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 152 { 153 return 0; 154 } 155 156 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 157 { 158 struct kvm_cpu_context *cntx; 159 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; 160 unsigned long host_isa, i; 161 162 /* Mark this VCPU never ran */ 163 vcpu->arch.ran_atleast_once = false; 164 vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO; 165 bitmap_zero(vcpu->arch.isa, RISCV_ISA_EXT_MAX); 166 167 /* Setup ISA features available to VCPU */ 168 for (i = 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) { 169 host_isa = kvm_isa_ext_arr[i]; 170 if (__riscv_isa_extension_available(NULL, host_isa) && 171 kvm_riscv_vcpu_isa_enable_allowed(i)) 172 set_bit(host_isa, vcpu->arch.isa); 173 } 174 175 /* Setup vendor, arch, and implementation details */ 176 vcpu->arch.mvendorid = sbi_get_mvendorid(); 177 vcpu->arch.marchid = sbi_get_marchid(); 178 vcpu->arch.mimpid = sbi_get_mimpid(); 179 180 /* Setup VCPU hfence queue */ 181 spin_lock_init(&vcpu->arch.hfence_lock); 182 183 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ 184 cntx = &vcpu->arch.guest_reset_context; 185 cntx->sstatus = SR_SPP | SR_SPIE; 186 cntx->hstatus = 0; 187 cntx->hstatus |= HSTATUS_VTW; 188 cntx->hstatus |= HSTATUS_SPVP; 189 cntx->hstatus |= HSTATUS_SPV; 190 191 /* By default, make CY, TM, and IR counters accessible in VU mode */ 192 reset_csr->scounteren = 0x7; 193 194 /* Setup VCPU timer */ 195 kvm_riscv_vcpu_timer_init(vcpu); 196 197 /* Reset VCPU */ 198 kvm_riscv_reset_vcpu(vcpu); 199 200 return 0; 201 } 202 203 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 204 { 205 /** 206 * vcpu with id 0 is the designated boot cpu. 207 * Keep all vcpus with non-zero id in power-off state so that 208 * they can be brought up using SBI HSM extension. 209 */ 210 if (vcpu->vcpu_idx != 0) 211 kvm_riscv_vcpu_power_off(vcpu); 212 } 213 214 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 215 { 216 /* Cleanup VCPU timer */ 217 kvm_riscv_vcpu_timer_deinit(vcpu); 218 219 /* Free unused pages pre-allocated for G-stage page table mappings */ 220 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); 221 } 222 223 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 224 { 225 return kvm_riscv_vcpu_timer_pending(vcpu); 226 } 227 228 void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 229 { 230 } 231 232 void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 233 { 234 } 235 236 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 237 { 238 return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) && 239 !vcpu->arch.power_off && !vcpu->arch.pause); 240 } 241 242 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 243 { 244 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 245 } 246 247 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 248 { 249 return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false; 250 } 251 252 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 253 { 254 return VM_FAULT_SIGBUS; 255 } 256 257 static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, 258 const struct kvm_one_reg *reg) 259 { 260 unsigned long __user *uaddr = 261 (unsigned long __user *)(unsigned long)reg->addr; 262 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 263 KVM_REG_SIZE_MASK | 264 KVM_REG_RISCV_CONFIG); 265 unsigned long reg_val; 266 267 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 268 return -EINVAL; 269 270 switch (reg_num) { 271 case KVM_REG_RISCV_CONFIG_REG(isa): 272 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; 273 break; 274 case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): 275 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) 276 return -EINVAL; 277 reg_val = riscv_cbom_block_size; 278 break; 279 default: 280 return -EINVAL; 281 } 282 283 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) 284 return -EFAULT; 285 286 return 0; 287 } 288 289 static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, 290 const struct kvm_one_reg *reg) 291 { 292 unsigned long __user *uaddr = 293 (unsigned long __user *)(unsigned long)reg->addr; 294 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 295 KVM_REG_SIZE_MASK | 296 KVM_REG_RISCV_CONFIG); 297 unsigned long i, isa_ext, reg_val; 298 299 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 300 return -EINVAL; 301 302 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) 303 return -EFAULT; 304 305 switch (reg_num) { 306 case KVM_REG_RISCV_CONFIG_REG(isa): 307 /* 308 * This ONE REG interface is only defined for 309 * single letter extensions. 310 */ 311 if (fls(reg_val) >= RISCV_ISA_EXT_BASE) 312 return -EINVAL; 313 314 if (!vcpu->arch.ran_atleast_once) { 315 /* Ignore the enable/disable request for certain extensions */ 316 for (i = 0; i < RISCV_ISA_EXT_BASE; i++) { 317 isa_ext = kvm_riscv_vcpu_base2isa_ext(i); 318 if (isa_ext >= KVM_RISCV_ISA_EXT_MAX) { 319 reg_val &= ~BIT(i); 320 continue; 321 } 322 if (!kvm_riscv_vcpu_isa_enable_allowed(isa_ext)) 323 if (reg_val & BIT(i)) 324 reg_val &= ~BIT(i); 325 if (!kvm_riscv_vcpu_isa_disable_allowed(isa_ext)) 326 if (!(reg_val & BIT(i))) 327 reg_val |= BIT(i); 328 } 329 reg_val &= riscv_isa_extension_base(NULL); 330 /* Do not modify anything beyond single letter extensions */ 331 reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) | 332 (reg_val & KVM_RISCV_BASE_ISA_MASK); 333 vcpu->arch.isa[0] = reg_val; 334 kvm_riscv_vcpu_fp_reset(vcpu); 335 } else { 336 return -EOPNOTSUPP; 337 } 338 break; 339 case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): 340 return -EOPNOTSUPP; 341 default: 342 return -EINVAL; 343 } 344 345 return 0; 346 } 347 348 static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu, 349 const struct kvm_one_reg *reg) 350 { 351 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 352 unsigned long __user *uaddr = 353 (unsigned long __user *)(unsigned long)reg->addr; 354 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 355 KVM_REG_SIZE_MASK | 356 KVM_REG_RISCV_CORE); 357 unsigned long reg_val; 358 359 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 360 return -EINVAL; 361 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) 362 return -EINVAL; 363 364 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc)) 365 reg_val = cntx->sepc; 366 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num && 367 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6)) 368 reg_val = ((unsigned long *)cntx)[reg_num]; 369 else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) 370 reg_val = (cntx->sstatus & SR_SPP) ? 371 KVM_RISCV_MODE_S : KVM_RISCV_MODE_U; 372 else 373 return -EINVAL; 374 375 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) 376 return -EFAULT; 377 378 return 0; 379 } 380 381 static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu, 382 const struct kvm_one_reg *reg) 383 { 384 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 385 unsigned long __user *uaddr = 386 (unsigned long __user *)(unsigned long)reg->addr; 387 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 388 KVM_REG_SIZE_MASK | 389 KVM_REG_RISCV_CORE); 390 unsigned long reg_val; 391 392 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 393 return -EINVAL; 394 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) 395 return -EINVAL; 396 397 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) 398 return -EFAULT; 399 400 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc)) 401 cntx->sepc = reg_val; 402 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num && 403 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6)) 404 ((unsigned long *)cntx)[reg_num] = reg_val; 405 else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) { 406 if (reg_val == KVM_RISCV_MODE_S) 407 cntx->sstatus |= SR_SPP; 408 else 409 cntx->sstatus &= ~SR_SPP; 410 } else 411 return -EINVAL; 412 413 return 0; 414 } 415 416 static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu, 417 const struct kvm_one_reg *reg) 418 { 419 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 420 unsigned long __user *uaddr = 421 (unsigned long __user *)(unsigned long)reg->addr; 422 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 423 KVM_REG_SIZE_MASK | 424 KVM_REG_RISCV_CSR); 425 unsigned long reg_val; 426 427 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 428 return -EINVAL; 429 if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) 430 return -EINVAL; 431 432 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) { 433 kvm_riscv_vcpu_flush_interrupts(vcpu); 434 reg_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK; 435 } else 436 reg_val = ((unsigned long *)csr)[reg_num]; 437 438 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) 439 return -EFAULT; 440 441 return 0; 442 } 443 444 static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, 445 const struct kvm_one_reg *reg) 446 { 447 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 448 unsigned long __user *uaddr = 449 (unsigned long __user *)(unsigned long)reg->addr; 450 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 451 KVM_REG_SIZE_MASK | 452 KVM_REG_RISCV_CSR); 453 unsigned long reg_val; 454 455 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 456 return -EINVAL; 457 if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) 458 return -EINVAL; 459 460 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) 461 return -EFAULT; 462 463 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) { 464 reg_val &= VSIP_VALID_MASK; 465 reg_val <<= VSIP_TO_HVIP_SHIFT; 466 } 467 468 ((unsigned long *)csr)[reg_num] = reg_val; 469 470 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) 471 WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); 472 473 return 0; 474 } 475 476 static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu, 477 const struct kvm_one_reg *reg) 478 { 479 unsigned long __user *uaddr = 480 (unsigned long __user *)(unsigned long)reg->addr; 481 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 482 KVM_REG_SIZE_MASK | 483 KVM_REG_RISCV_ISA_EXT); 484 unsigned long reg_val = 0; 485 unsigned long host_isa_ext; 486 487 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 488 return -EINVAL; 489 490 if (reg_num >= KVM_RISCV_ISA_EXT_MAX || 491 reg_num >= ARRAY_SIZE(kvm_isa_ext_arr)) 492 return -EINVAL; 493 494 host_isa_ext = kvm_isa_ext_arr[reg_num]; 495 if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext)) 496 reg_val = 1; /* Mark the given extension as available */ 497 498 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) 499 return -EFAULT; 500 501 return 0; 502 } 503 504 static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu, 505 const struct kvm_one_reg *reg) 506 { 507 unsigned long __user *uaddr = 508 (unsigned long __user *)(unsigned long)reg->addr; 509 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | 510 KVM_REG_SIZE_MASK | 511 KVM_REG_RISCV_ISA_EXT); 512 unsigned long reg_val; 513 unsigned long host_isa_ext; 514 515 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) 516 return -EINVAL; 517 518 if (reg_num >= KVM_RISCV_ISA_EXT_MAX || 519 reg_num >= ARRAY_SIZE(kvm_isa_ext_arr)) 520 return -EINVAL; 521 522 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) 523 return -EFAULT; 524 525 host_isa_ext = kvm_isa_ext_arr[reg_num]; 526 if (!__riscv_isa_extension_available(NULL, host_isa_ext)) 527 return -EOPNOTSUPP; 528 529 if (!vcpu->arch.ran_atleast_once) { 530 /* 531 * All multi-letter extension and a few single letter 532 * extension can be disabled 533 */ 534 if (reg_val == 1 && 535 kvm_riscv_vcpu_isa_enable_allowed(reg_num)) 536 set_bit(host_isa_ext, vcpu->arch.isa); 537 else if (!reg_val && 538 kvm_riscv_vcpu_isa_disable_allowed(reg_num)) 539 clear_bit(host_isa_ext, vcpu->arch.isa); 540 else 541 return -EINVAL; 542 kvm_riscv_vcpu_fp_reset(vcpu); 543 } else { 544 return -EOPNOTSUPP; 545 } 546 547 return 0; 548 } 549 550 static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, 551 const struct kvm_one_reg *reg) 552 { 553 switch (reg->id & KVM_REG_RISCV_TYPE_MASK) { 554 case KVM_REG_RISCV_CONFIG: 555 return kvm_riscv_vcpu_set_reg_config(vcpu, reg); 556 case KVM_REG_RISCV_CORE: 557 return kvm_riscv_vcpu_set_reg_core(vcpu, reg); 558 case KVM_REG_RISCV_CSR: 559 return kvm_riscv_vcpu_set_reg_csr(vcpu, reg); 560 case KVM_REG_RISCV_TIMER: 561 return kvm_riscv_vcpu_set_reg_timer(vcpu, reg); 562 case KVM_REG_RISCV_FP_F: 563 return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, 564 KVM_REG_RISCV_FP_F); 565 case KVM_REG_RISCV_FP_D: 566 return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, 567 KVM_REG_RISCV_FP_D); 568 case KVM_REG_RISCV_ISA_EXT: 569 return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg); 570 default: 571 break; 572 } 573 574 return -EINVAL; 575 } 576 577 static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, 578 const struct kvm_one_reg *reg) 579 { 580 switch (reg->id & KVM_REG_RISCV_TYPE_MASK) { 581 case KVM_REG_RISCV_CONFIG: 582 return kvm_riscv_vcpu_get_reg_config(vcpu, reg); 583 case KVM_REG_RISCV_CORE: 584 return kvm_riscv_vcpu_get_reg_core(vcpu, reg); 585 case KVM_REG_RISCV_CSR: 586 return kvm_riscv_vcpu_get_reg_csr(vcpu, reg); 587 case KVM_REG_RISCV_TIMER: 588 return kvm_riscv_vcpu_get_reg_timer(vcpu, reg); 589 case KVM_REG_RISCV_FP_F: 590 return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, 591 KVM_REG_RISCV_FP_F); 592 case KVM_REG_RISCV_FP_D: 593 return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, 594 KVM_REG_RISCV_FP_D); 595 case KVM_REG_RISCV_ISA_EXT: 596 return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg); 597 default: 598 break; 599 } 600 601 return -EINVAL; 602 } 603 604 long kvm_arch_vcpu_async_ioctl(struct file *filp, 605 unsigned int ioctl, unsigned long arg) 606 { 607 struct kvm_vcpu *vcpu = filp->private_data; 608 void __user *argp = (void __user *)arg; 609 610 if (ioctl == KVM_INTERRUPT) { 611 struct kvm_interrupt irq; 612 613 if (copy_from_user(&irq, argp, sizeof(irq))) 614 return -EFAULT; 615 616 if (irq.irq == KVM_INTERRUPT_SET) 617 return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT); 618 else 619 return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT); 620 } 621 622 return -ENOIOCTLCMD; 623 } 624 625 long kvm_arch_vcpu_ioctl(struct file *filp, 626 unsigned int ioctl, unsigned long arg) 627 { 628 struct kvm_vcpu *vcpu = filp->private_data; 629 void __user *argp = (void __user *)arg; 630 long r = -EINVAL; 631 632 switch (ioctl) { 633 case KVM_SET_ONE_REG: 634 case KVM_GET_ONE_REG: { 635 struct kvm_one_reg reg; 636 637 r = -EFAULT; 638 if (copy_from_user(®, argp, sizeof(reg))) 639 break; 640 641 if (ioctl == KVM_SET_ONE_REG) 642 r = kvm_riscv_vcpu_set_reg(vcpu, ®); 643 else 644 r = kvm_riscv_vcpu_get_reg(vcpu, ®); 645 break; 646 } 647 default: 648 break; 649 } 650 651 return r; 652 } 653 654 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 655 struct kvm_sregs *sregs) 656 { 657 return -EINVAL; 658 } 659 660 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 661 struct kvm_sregs *sregs) 662 { 663 return -EINVAL; 664 } 665 666 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 667 { 668 return -EINVAL; 669 } 670 671 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 672 { 673 return -EINVAL; 674 } 675 676 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 677 struct kvm_translation *tr) 678 { 679 return -EINVAL; 680 } 681 682 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 683 { 684 return -EINVAL; 685 } 686 687 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 688 { 689 return -EINVAL; 690 } 691 692 void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu) 693 { 694 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 695 unsigned long mask, val; 696 697 if (READ_ONCE(vcpu->arch.irqs_pending_mask)) { 698 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask, 0); 699 val = READ_ONCE(vcpu->arch.irqs_pending) & mask; 700 701 csr->hvip &= ~mask; 702 csr->hvip |= val; 703 } 704 } 705 706 void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) 707 { 708 unsigned long hvip; 709 struct kvm_vcpu_arch *v = &vcpu->arch; 710 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 711 712 /* Read current HVIP and VSIE CSRs */ 713 csr->vsie = csr_read(CSR_VSIE); 714 715 /* Sync-up HVIP.VSSIP bit changes does by Guest */ 716 hvip = csr_read(CSR_HVIP); 717 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) { 718 if (hvip & (1UL << IRQ_VS_SOFT)) { 719 if (!test_and_set_bit(IRQ_VS_SOFT, 720 &v->irqs_pending_mask)) 721 set_bit(IRQ_VS_SOFT, &v->irqs_pending); 722 } else { 723 if (!test_and_set_bit(IRQ_VS_SOFT, 724 &v->irqs_pending_mask)) 725 clear_bit(IRQ_VS_SOFT, &v->irqs_pending); 726 } 727 } 728 729 /* Sync-up timer CSRs */ 730 kvm_riscv_vcpu_timer_sync(vcpu); 731 } 732 733 int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) 734 { 735 if (irq != IRQ_VS_SOFT && 736 irq != IRQ_VS_TIMER && 737 irq != IRQ_VS_EXT) 738 return -EINVAL; 739 740 set_bit(irq, &vcpu->arch.irqs_pending); 741 smp_mb__before_atomic(); 742 set_bit(irq, &vcpu->arch.irqs_pending_mask); 743 744 kvm_vcpu_kick(vcpu); 745 746 return 0; 747 } 748 749 int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) 750 { 751 if (irq != IRQ_VS_SOFT && 752 irq != IRQ_VS_TIMER && 753 irq != IRQ_VS_EXT) 754 return -EINVAL; 755 756 clear_bit(irq, &vcpu->arch.irqs_pending); 757 smp_mb__before_atomic(); 758 set_bit(irq, &vcpu->arch.irqs_pending_mask); 759 760 return 0; 761 } 762 763 bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask) 764 { 765 unsigned long ie = ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK) 766 << VSIP_TO_HVIP_SHIFT) & mask; 767 768 return (READ_ONCE(vcpu->arch.irqs_pending) & ie) ? true : false; 769 } 770 771 void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu) 772 { 773 vcpu->arch.power_off = true; 774 kvm_make_request(KVM_REQ_SLEEP, vcpu); 775 kvm_vcpu_kick(vcpu); 776 } 777 778 void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu) 779 { 780 vcpu->arch.power_off = false; 781 kvm_vcpu_wake_up(vcpu); 782 } 783 784 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 785 struct kvm_mp_state *mp_state) 786 { 787 if (vcpu->arch.power_off) 788 mp_state->mp_state = KVM_MP_STATE_STOPPED; 789 else 790 mp_state->mp_state = KVM_MP_STATE_RUNNABLE; 791 792 return 0; 793 } 794 795 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 796 struct kvm_mp_state *mp_state) 797 { 798 int ret = 0; 799 800 switch (mp_state->mp_state) { 801 case KVM_MP_STATE_RUNNABLE: 802 vcpu->arch.power_off = false; 803 break; 804 case KVM_MP_STATE_STOPPED: 805 kvm_riscv_vcpu_power_off(vcpu); 806 break; 807 default: 808 ret = -EINVAL; 809 } 810 811 return ret; 812 } 813 814 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 815 struct kvm_guest_debug *dbg) 816 { 817 /* TODO; To be implemented later. */ 818 return -EINVAL; 819 } 820 821 static void kvm_riscv_vcpu_update_config(const unsigned long *isa) 822 { 823 u64 henvcfg = 0; 824 825 if (riscv_isa_extension_available(isa, SVPBMT)) 826 henvcfg |= ENVCFG_PBMTE; 827 828 if (riscv_isa_extension_available(isa, SSTC)) 829 henvcfg |= ENVCFG_STCE; 830 831 if (riscv_isa_extension_available(isa, ZICBOM)) 832 henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); 833 834 csr_write(CSR_HENVCFG, henvcfg); 835 #ifdef CONFIG_32BIT 836 csr_write(CSR_HENVCFGH, henvcfg >> 32); 837 #endif 838 } 839 840 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 841 { 842 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 843 844 csr_write(CSR_VSSTATUS, csr->vsstatus); 845 csr_write(CSR_VSIE, csr->vsie); 846 csr_write(CSR_VSTVEC, csr->vstvec); 847 csr_write(CSR_VSSCRATCH, csr->vsscratch); 848 csr_write(CSR_VSEPC, csr->vsepc); 849 csr_write(CSR_VSCAUSE, csr->vscause); 850 csr_write(CSR_VSTVAL, csr->vstval); 851 csr_write(CSR_HVIP, csr->hvip); 852 csr_write(CSR_VSATP, csr->vsatp); 853 854 kvm_riscv_vcpu_update_config(vcpu->arch.isa); 855 856 kvm_riscv_gstage_update_hgatp(vcpu); 857 858 kvm_riscv_vcpu_timer_restore(vcpu); 859 860 kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); 861 kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, 862 vcpu->arch.isa); 863 864 vcpu->cpu = cpu; 865 } 866 867 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 868 { 869 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 870 871 vcpu->cpu = -1; 872 873 kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context, 874 vcpu->arch.isa); 875 kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); 876 877 kvm_riscv_vcpu_timer_save(vcpu); 878 879 csr->vsstatus = csr_read(CSR_VSSTATUS); 880 csr->vsie = csr_read(CSR_VSIE); 881 csr->vstvec = csr_read(CSR_VSTVEC); 882 csr->vsscratch = csr_read(CSR_VSSCRATCH); 883 csr->vsepc = csr_read(CSR_VSEPC); 884 csr->vscause = csr_read(CSR_VSCAUSE); 885 csr->vstval = csr_read(CSR_VSTVAL); 886 csr->hvip = csr_read(CSR_HVIP); 887 csr->vsatp = csr_read(CSR_VSATP); 888 } 889 890 static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) 891 { 892 struct rcuwait *wait = kvm_arch_vcpu_get_wait(vcpu); 893 894 if (kvm_request_pending(vcpu)) { 895 if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) { 896 kvm_vcpu_srcu_read_unlock(vcpu); 897 rcuwait_wait_event(wait, 898 (!vcpu->arch.power_off) && (!vcpu->arch.pause), 899 TASK_INTERRUPTIBLE); 900 kvm_vcpu_srcu_read_lock(vcpu); 901 902 if (vcpu->arch.power_off || vcpu->arch.pause) { 903 /* 904 * Awaken to handle a signal, request to 905 * sleep again later. 906 */ 907 kvm_make_request(KVM_REQ_SLEEP, vcpu); 908 } 909 } 910 911 if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu)) 912 kvm_riscv_reset_vcpu(vcpu); 913 914 if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu)) 915 kvm_riscv_gstage_update_hgatp(vcpu); 916 917 if (kvm_check_request(KVM_REQ_FENCE_I, vcpu)) 918 kvm_riscv_fence_i_process(vcpu); 919 920 /* 921 * The generic KVM_REQ_TLB_FLUSH is same as 922 * KVM_REQ_HFENCE_GVMA_VMID_ALL 923 */ 924 if (kvm_check_request(KVM_REQ_HFENCE_GVMA_VMID_ALL, vcpu)) 925 kvm_riscv_hfence_gvma_vmid_all_process(vcpu); 926 927 if (kvm_check_request(KVM_REQ_HFENCE_VVMA_ALL, vcpu)) 928 kvm_riscv_hfence_vvma_all_process(vcpu); 929 930 if (kvm_check_request(KVM_REQ_HFENCE, vcpu)) 931 kvm_riscv_hfence_process(vcpu); 932 } 933 } 934 935 static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) 936 { 937 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 938 939 csr_write(CSR_HVIP, csr->hvip); 940 } 941 942 /* 943 * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while 944 * the vCPU is running. 945 * 946 * This must be noinstr as instrumentation may make use of RCU, and this is not 947 * safe during the EQS. 948 */ 949 static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu) 950 { 951 guest_state_enter_irqoff(); 952 __kvm_riscv_switch_to(&vcpu->arch); 953 vcpu->arch.last_exit_cpu = vcpu->cpu; 954 guest_state_exit_irqoff(); 955 } 956 957 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 958 { 959 int ret; 960 struct kvm_cpu_trap trap; 961 struct kvm_run *run = vcpu->run; 962 963 /* Mark this VCPU ran at least once */ 964 vcpu->arch.ran_atleast_once = true; 965 966 kvm_vcpu_srcu_read_lock(vcpu); 967 968 switch (run->exit_reason) { 969 case KVM_EXIT_MMIO: 970 /* Process MMIO value returned from user-space */ 971 ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run); 972 break; 973 case KVM_EXIT_RISCV_SBI: 974 /* Process SBI value returned from user-space */ 975 ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run); 976 break; 977 case KVM_EXIT_RISCV_CSR: 978 /* Process CSR value returned from user-space */ 979 ret = kvm_riscv_vcpu_csr_return(vcpu, vcpu->run); 980 break; 981 default: 982 ret = 0; 983 break; 984 } 985 if (ret) { 986 kvm_vcpu_srcu_read_unlock(vcpu); 987 return ret; 988 } 989 990 if (run->immediate_exit) { 991 kvm_vcpu_srcu_read_unlock(vcpu); 992 return -EINTR; 993 } 994 995 vcpu_load(vcpu); 996 997 kvm_sigset_activate(vcpu); 998 999 ret = 1; 1000 run->exit_reason = KVM_EXIT_UNKNOWN; 1001 while (ret > 0) { 1002 /* Check conditions before entering the guest */ 1003 ret = xfer_to_guest_mode_handle_work(vcpu); 1004 if (ret) 1005 continue; 1006 ret = 1; 1007 1008 kvm_riscv_gstage_vmid_update(vcpu); 1009 1010 kvm_riscv_check_vcpu_requests(vcpu); 1011 1012 local_irq_disable(); 1013 1014 /* 1015 * Ensure we set mode to IN_GUEST_MODE after we disable 1016 * interrupts and before the final VCPU requests check. 1017 * See the comment in kvm_vcpu_exiting_guest_mode() and 1018 * Documentation/virt/kvm/vcpu-requests.rst 1019 */ 1020 vcpu->mode = IN_GUEST_MODE; 1021 1022 kvm_vcpu_srcu_read_unlock(vcpu); 1023 smp_mb__after_srcu_read_unlock(); 1024 1025 /* 1026 * We might have got VCPU interrupts updated asynchronously 1027 * so update it in HW. 1028 */ 1029 kvm_riscv_vcpu_flush_interrupts(vcpu); 1030 1031 /* Update HVIP CSR for current CPU */ 1032 kvm_riscv_update_hvip(vcpu); 1033 1034 if (ret <= 0 || 1035 kvm_riscv_gstage_vmid_ver_changed(&vcpu->kvm->arch.vmid) || 1036 kvm_request_pending(vcpu) || 1037 xfer_to_guest_mode_work_pending()) { 1038 vcpu->mode = OUTSIDE_GUEST_MODE; 1039 local_irq_enable(); 1040 kvm_vcpu_srcu_read_lock(vcpu); 1041 continue; 1042 } 1043 1044 /* 1045 * Cleanup stale TLB enteries 1046 * 1047 * Note: This should be done after G-stage VMID has been 1048 * updated using kvm_riscv_gstage_vmid_ver_changed() 1049 */ 1050 kvm_riscv_local_tlb_sanitize(vcpu); 1051 1052 guest_timing_enter_irqoff(); 1053 1054 kvm_riscv_vcpu_enter_exit(vcpu); 1055 1056 vcpu->mode = OUTSIDE_GUEST_MODE; 1057 vcpu->stat.exits++; 1058 1059 /* 1060 * Save SCAUSE, STVAL, HTVAL, and HTINST because we might 1061 * get an interrupt between __kvm_riscv_switch_to() and 1062 * local_irq_enable() which can potentially change CSRs. 1063 */ 1064 trap.sepc = vcpu->arch.guest_context.sepc; 1065 trap.scause = csr_read(CSR_SCAUSE); 1066 trap.stval = csr_read(CSR_STVAL); 1067 trap.htval = csr_read(CSR_HTVAL); 1068 trap.htinst = csr_read(CSR_HTINST); 1069 1070 /* Syncup interrupts state with HW */ 1071 kvm_riscv_vcpu_sync_interrupts(vcpu); 1072 1073 preempt_disable(); 1074 1075 /* 1076 * We must ensure that any pending interrupts are taken before 1077 * we exit guest timing so that timer ticks are accounted as 1078 * guest time. Transiently unmask interrupts so that any 1079 * pending interrupts are taken. 1080 * 1081 * There's no barrier which ensures that pending interrupts are 1082 * recognised, so we just hope that the CPU takes any pending 1083 * interrupts between the enable and disable. 1084 */ 1085 local_irq_enable(); 1086 local_irq_disable(); 1087 1088 guest_timing_exit_irqoff(); 1089 1090 local_irq_enable(); 1091 1092 preempt_enable(); 1093 1094 kvm_vcpu_srcu_read_lock(vcpu); 1095 1096 ret = kvm_riscv_vcpu_exit(vcpu, run, &trap); 1097 } 1098 1099 kvm_sigset_deactivate(vcpu); 1100 1101 vcpu_put(vcpu); 1102 1103 kvm_vcpu_srcu_read_unlock(vcpu); 1104 1105 return ret; 1106 } 1107