traps.c (ba797b28131b1f1367b662936ea370239d603cff) traps.c (fe04b1121511a97982a1fcdd38e44d2029304a6d)
1/*
2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
1/*
2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * and Paul Mackerras (paulus@samba.org)

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300
301#ifdef CONFIG_PPC_ADV_DEBUG_REGS
302/* On 4xx, the reason for the machine check or program exception
303 is in the ESR. */
304#define get_reason(regs) ((regs)->dsisr)
305#ifndef CONFIG_FSL_BOOKE
306#define get_mc_reason(regs) ((regs)->dsisr)
307#else
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)

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301
302#ifdef CONFIG_PPC_ADV_DEBUG_REGS
303/* On 4xx, the reason for the machine check or program exception
304 is in the ESR. */
305#define get_reason(regs) ((regs)->dsisr)
306#ifndef CONFIG_FSL_BOOKE
307#define get_mc_reason(regs) ((regs)->dsisr)
308#else
308#define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK)
309#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
309#endif
310#define REASON_FP ESR_FP
311#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
312#define REASON_PRIVILEGED ESR_PPR
313#define REASON_TRAP ESR_PTR
314
315/* single-step stuff */
316#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)

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375 if (mcsr & MCSR_IMPE)
376 printk("Machine Check exception is imprecise\n");
377
378 /* Clear MCSR */
379 mtspr(SPRN_MCSR, mcsr);
380 }
381 return 0;
382}
310#endif
311#define REASON_FP ESR_FP
312#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
313#define REASON_PRIVILEGED ESR_PPR
314#define REASON_TRAP ESR_PTR
315
316/* single-step stuff */
317#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)

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376 if (mcsr & MCSR_IMPE)
377 printk("Machine Check exception is imprecise\n");
378
379 /* Clear MCSR */
380 mtspr(SPRN_MCSR, mcsr);
381 }
382 return 0;
383}
384
385int machine_check_47x(struct pt_regs *regs)
386{
387 unsigned long reason = get_mc_reason(regs);
388 u32 mcsr;
389
390 printk(KERN_ERR "Machine check in kernel mode.\n");
391 if (reason & ESR_IMCP) {
392 printk(KERN_ERR
393 "Instruction Synchronous Machine Check exception\n");
394 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
395 return 0;
396 }
397 mcsr = mfspr(SPRN_MCSR);
398 if (mcsr & MCSR_IB)
399 printk(KERN_ERR "Instruction Read PLB Error\n");
400 if (mcsr & MCSR_DRB)
401 printk(KERN_ERR "Data Read PLB Error\n");
402 if (mcsr & MCSR_DWB)
403 printk(KERN_ERR "Data Write PLB Error\n");
404 if (mcsr & MCSR_TLBP)
405 printk(KERN_ERR "TLB Parity Error\n");
406 if (mcsr & MCSR_ICP) {
407 flush_instruction_cache();
408 printk(KERN_ERR "I-Cache Parity Error\n");
409 }
410 if (mcsr & MCSR_DCSP)
411 printk(KERN_ERR "D-Cache Search Parity Error\n");
412 if (mcsr & PPC47x_MCSR_GPR)
413 printk(KERN_ERR "GPR Parity Error\n");
414 if (mcsr & PPC47x_MCSR_FPR)
415 printk(KERN_ERR "FPR Parity Error\n");
416 if (mcsr & PPC47x_MCSR_IPR)
417 printk(KERN_ERR "Machine Check exception is imprecise\n");
418
419 /* Clear MCSR */
420 mtspr(SPRN_MCSR, mcsr);
421
422 return 0;
423}
383#elif defined(CONFIG_E500)
424#elif defined(CONFIG_E500)
425int machine_check_e500mc(struct pt_regs *regs)
426{
427 unsigned long mcsr = mfspr(SPRN_MCSR);
428 unsigned long reason = mcsr;
429 int recoverable = 1;
430
431 printk("Machine check in kernel mode.\n");
432 printk("Caused by (from MCSR=%lx): ", reason);
433
434 if (reason & MCSR_MCP)
435 printk("Machine Check Signal\n");
436
437 if (reason & MCSR_ICPERR) {
438 printk("Instruction Cache Parity Error\n");
439
440 /*
441 * This is recoverable by invalidating the i-cache.
442 */
443 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
444 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
445 ;
446
447 /*
448 * This will generally be accompanied by an instruction
449 * fetch error report -- only treat MCSR_IF as fatal
450 * if it wasn't due to an L1 parity error.
451 */
452 reason &= ~MCSR_IF;
453 }
454
455 if (reason & MCSR_DCPERR_MC) {
456 printk("Data Cache Parity Error\n");
457 recoverable = 0;
458 }
459
460 if (reason & MCSR_L2MMU_MHIT) {
461 printk("Hit on multiple TLB entries\n");
462 recoverable = 0;
463 }
464
465 if (reason & MCSR_NMI)
466 printk("Non-maskable interrupt\n");
467
468 if (reason & MCSR_IF) {
469 printk("Instruction Fetch Error Report\n");
470 recoverable = 0;
471 }
472
473 if (reason & MCSR_LD) {
474 printk("Load Error Report\n");
475 recoverable = 0;
476 }
477
478 if (reason & MCSR_ST) {
479 printk("Store Error Report\n");
480 recoverable = 0;
481 }
482
483 if (reason & MCSR_LDG) {
484 printk("Guarded Load Error Report\n");
485 recoverable = 0;
486 }
487
488 if (reason & MCSR_TLBSYNC)
489 printk("Simultaneous tlbsync operations\n");
490
491 if (reason & MCSR_BSL2_ERR) {
492 printk("Level 2 Cache Error\n");
493 recoverable = 0;
494 }
495
496 if (reason & MCSR_MAV) {
497 u64 addr;
498
499 addr = mfspr(SPRN_MCAR);
500 addr |= (u64)mfspr(SPRN_MCARU) << 32;
501
502 printk("Machine Check %s Address: %#llx\n",
503 reason & MCSR_MEA ? "Effective" : "Physical", addr);
504 }
505
506 mtspr(SPRN_MCSR, mcsr);
507 return mfspr(SPRN_MCSR) == 0 && recoverable;
508}
509
384int machine_check_e500(struct pt_regs *regs)
385{
386 unsigned long reason = get_mc_reason(regs);
387
388 printk("Machine check in kernel mode.\n");
389 printk("Caused by (from MCSR=%lx): ", reason);
390
391 if (reason & MCSR_MCP)

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810 * has no FPU, in that case the reason flags will be 0 */
811
812 if (reason & REASON_FP) {
813 /* IEEE FP exception */
814 parse_fpe(regs);
815 return;
816 }
817 if (reason & REASON_TRAP) {
510int machine_check_e500(struct pt_regs *regs)
511{
512 unsigned long reason = get_mc_reason(regs);
513
514 printk("Machine check in kernel mode.\n");
515 printk("Caused by (from MCSR=%lx): ", reason);
516
517 if (reason & MCSR_MCP)

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936 * has no FPU, in that case the reason flags will be 0 */
937
938 if (reason & REASON_FP) {
939 /* IEEE FP exception */
940 parse_fpe(regs);
941 return;
942 }
943 if (reason & REASON_TRAP) {
818 /* Debugger is first in line to stop recursive faults in
819 * rcu_lock, notify_die, or atomic_notifier_call_chain */
820 if (debugger_bpt(regs))
821 return;
822
823 /* trap exception */
824 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
825 == NOTIFY_STOP)
826 return;
944 /* trap exception */
945 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
946 == NOTIFY_STOP)
947 return;
948 if (debugger_bpt(regs))
949 return;
827
828 if (!(regs->msr & MSR_PR) && /* not user-mode */
829 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
830 regs->nip += 4;
831 return;
832 }
833 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
834 return;

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951 if (!(regs->msr & MSR_PR) && /* not user-mode */
952 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
953 regs->nip += 4;
954 return;
955 }
956 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
957 return;

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