process.c (5d43889c07bb38694742936aa70d1187c012e198) process.c (f5f972102d5c12729f0a35fce266b580aaa03f66)
1/*
2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
4 *
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
7 *
8 * PowerPC version

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334 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
335 */
336 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
337#else
338 thread->debug.dbcr1 = 0;
339#endif
340}
341
1/*
2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
4 *
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
7 *
8 * PowerPC version

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334 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
335 */
336 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
337#else
338 thread->debug.dbcr1 = 0;
339#endif
340}
341
342static void prime_debug_regs(struct thread_struct *thread)
342static void prime_debug_regs(struct debug_reg *debug)
343{
344 /*
345 * We could have inherited MSR_DE from userspace, since
346 * it doesn't get cleared on exception entry. Make sure
347 * MSR_DE is clear before we enable any debug events.
348 */
349 mtmsr(mfmsr() & ~MSR_DE);
350
343{
344 /*
345 * We could have inherited MSR_DE from userspace, since
346 * it doesn't get cleared on exception entry. Make sure
347 * MSR_DE is clear before we enable any debug events.
348 */
349 mtmsr(mfmsr() & ~MSR_DE);
350
351 mtspr(SPRN_IAC1, thread->debug.iac1);
352 mtspr(SPRN_IAC2, thread->debug.iac2);
351 mtspr(SPRN_IAC1, debug->iac1);
352 mtspr(SPRN_IAC2, debug->iac2);
353#if CONFIG_PPC_ADV_DEBUG_IACS > 2
353#if CONFIG_PPC_ADV_DEBUG_IACS > 2
354 mtspr(SPRN_IAC3, thread->debug.iac3);
355 mtspr(SPRN_IAC4, thread->debug.iac4);
354 mtspr(SPRN_IAC3, debug->iac3);
355 mtspr(SPRN_IAC4, debug->iac4);
356#endif
356#endif
357 mtspr(SPRN_DAC1, thread->debug.dac1);
358 mtspr(SPRN_DAC2, thread->debug.dac2);
357 mtspr(SPRN_DAC1, debug->dac1);
358 mtspr(SPRN_DAC2, debug->dac2);
359#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
359#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
360 mtspr(SPRN_DVC1, thread->debug.dvc1);
361 mtspr(SPRN_DVC2, thread->debug.dvc2);
360 mtspr(SPRN_DVC1, debug->dvc1);
361 mtspr(SPRN_DVC2, debug->dvc2);
362#endif
362#endif
363 mtspr(SPRN_DBCR0, thread->debug.dbcr0);
364 mtspr(SPRN_DBCR1, thread->debug.dbcr1);
363 mtspr(SPRN_DBCR0, debug->dbcr0);
364 mtspr(SPRN_DBCR1, debug->dbcr1);
365#ifdef CONFIG_BOOKE
365#ifdef CONFIG_BOOKE
366 mtspr(SPRN_DBCR2, thread->debug.dbcr2);
366 mtspr(SPRN_DBCR2, debug->dbcr2);
367#endif
368}
369/*
370 * Unless neither the old or new thread are making use of the
371 * debug registers, set the debug registers from the values
372 * stored in the new thread.
373 */
367#endif
368}
369/*
370 * Unless neither the old or new thread are making use of the
371 * debug registers, set the debug registers from the values
372 * stored in the new thread.
373 */
374void switch_booke_debug_regs(struct thread_struct *new_thread)
374void switch_booke_debug_regs(struct debug_reg *new_debug)
375{
376 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
375{
376 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
377 || (new_thread->debug.dbcr0 & DBCR0_IDM))
378 prime_debug_regs(new_thread);
377 || (new_debug->dbcr0 & DBCR0_IDM))
378 prime_debug_regs(new_debug);
379}
380EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
381#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
382#ifndef CONFIG_HAVE_HW_BREAKPOINT
383static void set_debug_reg_defaults(struct thread_struct *thread)
384{
385 thread->hw_brk.address = 0;
386 thread->hw_brk.type = 0;

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678 */
679 if (new->thread.regs && last_task_used_spe == new)
680 new->thread.regs->msr |= MSR_SPE;
681#endif /* CONFIG_SPE */
682
683#endif /* CONFIG_SMP */
684
685#ifdef CONFIG_PPC_ADV_DEBUG_REGS
379}
380EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
381#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
382#ifndef CONFIG_HAVE_HW_BREAKPOINT
383static void set_debug_reg_defaults(struct thread_struct *thread)
384{
385 thread->hw_brk.address = 0;
386 thread->hw_brk.type = 0;

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678 */
679 if (new->thread.regs && last_task_used_spe == new)
680 new->thread.regs->msr |= MSR_SPE;
681#endif /* CONFIG_SPE */
682
683#endif /* CONFIG_SMP */
684
685#ifdef CONFIG_PPC_ADV_DEBUG_REGS
686 switch_booke_debug_regs(&new->thread);
686 switch_booke_debug_regs(&new->thread.debug);
687#else
688/*
689 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
690 * schedule DABR
691 */
692#ifndef CONFIG_HAVE_HW_BREAKPOINT
693 if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
694 set_breakpoint(&new->thread.hw_brk);

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853
854 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
855 regs->nip, regs->link, regs->ctr);
856 printk("REGS: %p TRAP: %04lx %s (%s)\n",
857 regs, regs->trap, print_tainted(), init_utsname()->release);
858 printk("MSR: "REG" ", regs->msr);
859 printbits(regs->msr, msr_bits);
860 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
687#else
688/*
689 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
690 * schedule DABR
691 */
692#ifndef CONFIG_HAVE_HW_BREAKPOINT
693 if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk)))
694 set_breakpoint(&new->thread.hw_brk);

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853
854 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
855 regs->nip, regs->link, regs->ctr);
856 printk("REGS: %p TRAP: %04lx %s (%s)\n",
857 regs, regs->trap, print_tainted(), init_utsname()->release);
858 printk("MSR: "REG" ", regs->msr);
859 printbits(regs->msr, msr_bits);
860 printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
861#ifdef CONFIG_PPC64
862 printk("SOFTE: %ld\n", regs->softe);
863#endif
861 trap = TRAP(regs);
862 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
864 trap = TRAP(regs);
865 if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
863 printk("CFAR: "REG" ", regs->orig_gpr3);
864 if (trap == 0x200 || trap == 0x300 || trap == 0x600)
866 printk("CFAR: "REG"\n", regs->orig_gpr3);
867 if (trap == 0x300 || trap == 0x600)
865#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
868#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
866 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
869 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
867#else
870#else
868 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
871 printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr);
869#endif
872#endif
870#ifdef CONFIG_PPC64
871 printk("SOFTE: %ld ", regs->softe);
872#endif
873#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
874 if (MSR_TM_ACTIVE(regs->msr))
875 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
876#endif
877
878 for (i = 0; i < 32; i++) {
879 if ((i % REGS_PER_LINE) == 0)
880 printk("\nGPR%02d: ", i);
881 printk(REG " ", regs->gpr[i]);
882 if (i == LAST_VOLATILE && !FULL_REGS(regs))
883 break;
884 }
885 printk("\n");
886#ifdef CONFIG_KALLSYMS
887 /*
888 * Lookup NIP late so we have the best change of getting the
889 * above info out without failing
890 */
891 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
892 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
893#endif
873
874 for (i = 0; i < 32; i++) {
875 if ((i % REGS_PER_LINE) == 0)
876 printk("\nGPR%02d: ", i);
877 printk(REG " ", regs->gpr[i]);
878 if (i == LAST_VOLATILE && !FULL_REGS(regs))
879 break;
880 }
881 printk("\n");
882#ifdef CONFIG_KALLSYMS
883 /*
884 * Lookup NIP late so we have the best change of getting the
885 * above info out without failing
886 */
887 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
888 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
889#endif
890#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
891 printk("PACATMSCRATCH [%llx]\n", get_paca()->tm_scratch);
892#endif
894 show_stack(current, (unsigned long *) regs->gpr[1]);
895 if (!user_mode(regs))
896 show_instructions(regs);
897}
898
899void exit_thread(void)
900{
901 discard_lazy_cpu_state();

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1082 regs->trap &= ~1UL;
1083
1084#ifdef CONFIG_PPC32
1085 regs->mq = 0;
1086 regs->nip = start;
1087 regs->msr = MSR_USER;
1088#else
1089 if (!is_32bit_task()) {
893 show_stack(current, (unsigned long *) regs->gpr[1]);
894 if (!user_mode(regs))
895 show_instructions(regs);
896}
897
898void exit_thread(void)
899{
900 discard_lazy_cpu_state();

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1081 regs->trap &= ~1UL;
1082
1083#ifdef CONFIG_PPC32
1084 regs->mq = 0;
1085 regs->nip = start;
1086 regs->msr = MSR_USER;
1087#else
1088 if (!is_32bit_task()) {
1090 unsigned long entry;
1089 unsigned long entry, toc;
1091
1090
1092 if (is_elf2_task()) {
1093 /* Look ma, no function descriptors! */
1094 entry = start;
1091 /* start is a relocated pointer to the function descriptor for
1092 * the elf _start routine. The first entry in the function
1093 * descriptor is the entry address of _start and the second
1094 * entry is the TOC value we need to use.
1095 */
1096 __get_user(entry, (unsigned long __user *)start);
1097 __get_user(toc, (unsigned long __user *)start+1);
1095
1098
1096 /*
1097 * Ulrich says:
1098 * The latest iteration of the ABI requires that when
1099 * calling a function (at its global entry point),
1100 * the caller must ensure r12 holds the entry point
1101 * address (so that the function can quickly
1102 * establish addressability).
1103 */
1104 regs->gpr[12] = start;
1105 /* Make sure that's restored on entry to userspace. */
1106 set_thread_flag(TIF_RESTOREALL);
1107 } else {
1108 unsigned long toc;
1109
1110 /* start is a relocated pointer to the function
1111 * descriptor for the elf _start routine. The first
1112 * entry in the function descriptor is the entry
1113 * address of _start and the second entry is the TOC
1114 * value we need to use.
1115 */
1116 __get_user(entry, (unsigned long __user *)start);
1117 __get_user(toc, (unsigned long __user *)start+1);
1118
1119 /* Check whether the e_entry function descriptor entries
1120 * need to be relocated before we can use them.
1121 */
1122 if (load_addr != 0) {
1123 entry += load_addr;
1124 toc += load_addr;
1125 }
1126 regs->gpr[2] = toc;
1099 /* Check whether the e_entry function descriptor entries
1100 * need to be relocated before we can use them.
1101 */
1102 if (load_addr != 0) {
1103 entry += load_addr;
1104 toc += load_addr;
1127 }
1128 regs->nip = entry;
1105 }
1106 regs->nip = entry;
1107 regs->gpr[2] = toc;
1129 regs->msr = MSR_USER64;
1130 } else {
1131 regs->nip = start;
1132 regs->gpr[2] = 0;
1133 regs->msr = MSR_USER32;
1134 }
1135#endif
1136 discard_lazy_cpu_state();

--- 356 unchanged lines hidden --- 		1108 regs->msr = MSR_USER64;
1109 } else {
1110 regs->nip = start;
1111 regs->gpr[2] = 0;
1112 regs->msr = MSR_USER32;
1113 }
1114#endif
1115 discard_lazy_cpu_state();

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