pci-common.c (ecd740c6f2f092b90b95fa35f757973589eaaca2) pci-common.c (d92a208d086063ecc785b4588f74ab42268cbc4b)
1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM

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16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
1/*
2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM

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16 * 2 of the License, or (at your option) any later version.
17 */
18
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/of_address.h>
26#include <linux/of_pci.h>
27#include <linux/mm.h>
28#include <linux/list.h>
29#include <linux/syscalls.h>
30#include <linux/irq.h>
31#include <linux/vmalloc.h>

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115 /*
116 * PCI core will figure out the default
117 * alignment: 4KiB for I/O and 1MiB for
118 * memory window.
119 */
120 return 1;
121}
122
25#include <linux/export.h>
26#include <linux/of_address.h>
27#include <linux/of_pci.h>
28#include <linux/mm.h>
29#include <linux/list.h>
30#include <linux/syscalls.h>
31#include <linux/irq.h>
32#include <linux/vmalloc.h>

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116 /*
117 * PCI core will figure out the default
118 * alignment: 4KiB for I/O and 1MiB for
119 * memory window.
120 */
121 return 1;
122}
123
124void pcibios_reset_secondary_bus(struct pci_dev *dev)
125{
126 u16 ctrl;
127
128 if (ppc_md.pcibios_reset_secondary_bus) {
129 ppc_md.pcibios_reset_secondary_bus(dev);
130 return;
131 }
132
133 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
134 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
135 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
136 msleep(2);
137
138 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
139 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
140 ssleep(1);
141}
142
123static resource_size_t pcibios_io_size(const struct pci_controller *hose)
124{
125#ifdef CONFIG_PPC64
126 return hose->pci_io_size;
127#else
128 return resource_size(&hose->io_resource);
129#endif
130}

--- 1581 unchanged lines hidden --- 		143static resource_size_t pcibios_io_size(const struct pci_controller *hose)
144{
145#ifdef CONFIG_PPC64
146 return hose->pci_io_size;
147#else
148 return resource_size(&hose->io_resource);
149#endif
150}

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