1 /* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/pci.h> 21 #include <linux/string.h> 22 #include <linux/init.h> 23 #include <linux/bootmem.h> 24 #include <linux/delay.h> 25 #include <linux/export.h> 26 #include <linux/of_address.h> 27 #include <linux/of_pci.h> 28 #include <linux/mm.h> 29 #include <linux/list.h> 30 #include <linux/syscalls.h> 31 #include <linux/irq.h> 32 #include <linux/vmalloc.h> 33 #include <linux/slab.h> 34 #include <linux/vgaarb.h> 35 36 #include <asm/processor.h> 37 #include <asm/io.h> 38 #include <asm/prom.h> 39 #include <asm/pci-bridge.h> 40 #include <asm/byteorder.h> 41 #include <asm/machdep.h> 42 #include <asm/ppc-pci.h> 43 #include <asm/eeh.h> 44 45 static DEFINE_SPINLOCK(hose_spinlock); 46 LIST_HEAD(hose_list); 47 48 /* XXX kill that some day ... */ 49 static int global_phb_number; /* Global phb counter */ 50 51 /* ISA Memory physical address */ 52 resource_size_t isa_mem_base; 53 54 55 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 56 57 void set_pci_dma_ops(struct dma_map_ops *dma_ops) 58 { 59 pci_dma_ops = dma_ops; 60 } 61 62 struct dma_map_ops *get_pci_dma_ops(void) 63 { 64 return pci_dma_ops; 65 } 66 EXPORT_SYMBOL(get_pci_dma_ops); 67 68 struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 69 { 70 struct pci_controller *phb; 71 72 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 73 if (phb == NULL) 74 return NULL; 75 spin_lock(&hose_spinlock); 76 phb->global_number = global_phb_number++; 77 list_add_tail(&phb->list_node, &hose_list); 78 spin_unlock(&hose_spinlock); 79 phb->dn = dev; 80 phb->is_dynamic = mem_init_done; 81 #ifdef CONFIG_PPC64 82 if (dev) { 83 int nid = of_node_to_nid(dev); 84 85 if (nid < 0 || !node_online(nid)) 86 nid = -1; 87 88 PHB_SET_NODE(phb, nid); 89 } 90 #endif 91 return phb; 92 } 93 94 void pcibios_free_controller(struct pci_controller *phb) 95 { 96 spin_lock(&hose_spinlock); 97 list_del(&phb->list_node); 98 spin_unlock(&hose_spinlock); 99 100 if (phb->is_dynamic) 101 kfree(phb); 102 } 103 104 /* 105 * The function is used to return the minimal alignment 106 * for memory or I/O windows of the associated P2P bridge. 107 * By default, 4KiB alignment for I/O windows and 1MiB for 108 * memory windows. 109 */ 110 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 111 unsigned long type) 112 { 113 if (ppc_md.pcibios_window_alignment) 114 return ppc_md.pcibios_window_alignment(bus, type); 115 116 /* 117 * PCI core will figure out the default 118 * alignment: 4KiB for I/O and 1MiB for 119 * memory window. 120 */ 121 return 1; 122 } 123 124 void pcibios_reset_secondary_bus(struct pci_dev *dev) 125 { 126 u16 ctrl; 127 128 if (ppc_md.pcibios_reset_secondary_bus) { 129 ppc_md.pcibios_reset_secondary_bus(dev); 130 return; 131 } 132 133 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); 134 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 135 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 136 msleep(2); 137 138 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 139 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 140 ssleep(1); 141 } 142 143 static resource_size_t pcibios_io_size(const struct pci_controller *hose) 144 { 145 #ifdef CONFIG_PPC64 146 return hose->pci_io_size; 147 #else 148 return resource_size(&hose->io_resource); 149 #endif 150 } 151 152 int pcibios_vaddr_is_ioport(void __iomem *address) 153 { 154 int ret = 0; 155 struct pci_controller *hose; 156 resource_size_t size; 157 158 spin_lock(&hose_spinlock); 159 list_for_each_entry(hose, &hose_list, list_node) { 160 size = pcibios_io_size(hose); 161 if (address >= hose->io_base_virt && 162 address < (hose->io_base_virt + size)) { 163 ret = 1; 164 break; 165 } 166 } 167 spin_unlock(&hose_spinlock); 168 return ret; 169 } 170 171 unsigned long pci_address_to_pio(phys_addr_t address) 172 { 173 struct pci_controller *hose; 174 resource_size_t size; 175 unsigned long ret = ~0; 176 177 spin_lock(&hose_spinlock); 178 list_for_each_entry(hose, &hose_list, list_node) { 179 size = pcibios_io_size(hose); 180 if (address >= hose->io_base_phys && 181 address < (hose->io_base_phys + size)) { 182 unsigned long base = 183 (unsigned long)hose->io_base_virt - _IO_BASE; 184 ret = base + (address - hose->io_base_phys); 185 break; 186 } 187 } 188 spin_unlock(&hose_spinlock); 189 190 return ret; 191 } 192 EXPORT_SYMBOL_GPL(pci_address_to_pio); 193 194 /* 195 * Return the domain number for this bus. 196 */ 197 int pci_domain_nr(struct pci_bus *bus) 198 { 199 struct pci_controller *hose = pci_bus_to_host(bus); 200 201 return hose->global_number; 202 } 203 EXPORT_SYMBOL(pci_domain_nr); 204 205 /* This routine is meant to be used early during boot, when the 206 * PCI bus numbers have not yet been assigned, and you need to 207 * issue PCI config cycles to an OF device. 208 * It could also be used to "fix" RTAS config cycles if you want 209 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 210 * config cycles. 211 */ 212 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 213 { 214 while(node) { 215 struct pci_controller *hose, *tmp; 216 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 217 if (hose->dn == node) 218 return hose; 219 node = node->parent; 220 } 221 return NULL; 222 } 223 224 static ssize_t pci_show_devspec(struct device *dev, 225 struct device_attribute *attr, char *buf) 226 { 227 struct pci_dev *pdev; 228 struct device_node *np; 229 230 pdev = to_pci_dev (dev); 231 np = pci_device_to_OF_node(pdev); 232 if (np == NULL || np->full_name == NULL) 233 return 0; 234 return sprintf(buf, "%s", np->full_name); 235 } 236 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 237 238 /* Add sysfs properties */ 239 int pcibios_add_platform_entries(struct pci_dev *pdev) 240 { 241 return device_create_file(&pdev->dev, &dev_attr_devspec); 242 } 243 244 /* 245 * Reads the interrupt pin to determine if interrupt is use by card. 246 * If the interrupt is used, then gets the interrupt line from the 247 * openfirmware and sets it in the pci_dev and pci_config line. 248 */ 249 static int pci_read_irq_line(struct pci_dev *pci_dev) 250 { 251 struct of_phandle_args oirq; 252 unsigned int virq; 253 254 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 255 256 #ifdef DEBUG 257 memset(&oirq, 0xff, sizeof(oirq)); 258 #endif 259 /* Try to get a mapping from the device-tree */ 260 if (of_irq_parse_pci(pci_dev, &oirq)) { 261 u8 line, pin; 262 263 /* If that fails, lets fallback to what is in the config 264 * space and map that through the default controller. We 265 * also set the type to level low since that's what PCI 266 * interrupts are. If your platform does differently, then 267 * either provide a proper interrupt tree or don't use this 268 * function. 269 */ 270 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 271 return -1; 272 if (pin == 0) 273 return -1; 274 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 275 line == 0xff || line == 0) { 276 return -1; 277 } 278 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 279 line, pin); 280 281 virq = irq_create_mapping(NULL, line); 282 if (virq != NO_IRQ) 283 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 284 } else { 285 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 286 oirq.args_count, oirq.args[0], oirq.args[1], 287 of_node_full_name(oirq.np)); 288 289 virq = irq_create_of_mapping(&oirq); 290 } 291 if(virq == NO_IRQ) { 292 pr_debug(" Failed to map !\n"); 293 return -1; 294 } 295 296 pr_debug(" Mapped to linux irq %d\n", virq); 297 298 pci_dev->irq = virq; 299 300 return 0; 301 } 302 303 /* 304 * Platform support for /proc/bus/pci/X/Y mmap()s, 305 * modelled on the sparc64 implementation by Dave Miller. 306 * -- paulus. 307 */ 308 309 /* 310 * Adjust vm_pgoff of VMA such that it is the physical page offset 311 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 312 * 313 * Basically, the user finds the base address for his device which he wishes 314 * to mmap. They read the 32-bit value from the config space base register, 315 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 316 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 317 * 318 * Returns negative error code on failure, zero on success. 319 */ 320 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 321 resource_size_t *offset, 322 enum pci_mmap_state mmap_state) 323 { 324 struct pci_controller *hose = pci_bus_to_host(dev->bus); 325 unsigned long io_offset = 0; 326 int i, res_bit; 327 328 if (hose == NULL) 329 return NULL; /* should never happen */ 330 331 /* If memory, add on the PCI bridge address offset */ 332 if (mmap_state == pci_mmap_mem) { 333 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 334 *offset += hose->pci_mem_offset; 335 #endif 336 res_bit = IORESOURCE_MEM; 337 } else { 338 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 339 *offset += io_offset; 340 res_bit = IORESOURCE_IO; 341 } 342 343 /* 344 * Check that the offset requested corresponds to one of the 345 * resources of the device. 346 */ 347 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 348 struct resource *rp = &dev->resource[i]; 349 int flags = rp->flags; 350 351 /* treat ROM as memory (should be already) */ 352 if (i == PCI_ROM_RESOURCE) 353 flags |= IORESOURCE_MEM; 354 355 /* Active and same type? */ 356 if ((flags & res_bit) == 0) 357 continue; 358 359 /* In the range of this resource? */ 360 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 361 continue; 362 363 /* found it! construct the final physical address */ 364 if (mmap_state == pci_mmap_io) 365 *offset += hose->io_base_phys - io_offset; 366 return rp; 367 } 368 369 return NULL; 370 } 371 372 /* 373 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 374 * device mapping. 375 */ 376 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 377 pgprot_t protection, 378 enum pci_mmap_state mmap_state, 379 int write_combine) 380 { 381 382 /* Write combine is always 0 on non-memory space mappings. On 383 * memory space, if the user didn't pass 1, we check for a 384 * "prefetchable" resource. This is a bit hackish, but we use 385 * this to workaround the inability of /sysfs to provide a write 386 * combine bit 387 */ 388 if (mmap_state != pci_mmap_mem) 389 write_combine = 0; 390 else if (write_combine == 0) { 391 if (rp->flags & IORESOURCE_PREFETCH) 392 write_combine = 1; 393 } 394 395 /* XXX would be nice to have a way to ask for write-through */ 396 if (write_combine) 397 return pgprot_noncached_wc(protection); 398 else 399 return pgprot_noncached(protection); 400 } 401 402 /* 403 * This one is used by /dev/mem and fbdev who have no clue about the 404 * PCI device, it tries to find the PCI device first and calls the 405 * above routine 406 */ 407 pgprot_t pci_phys_mem_access_prot(struct file *file, 408 unsigned long pfn, 409 unsigned long size, 410 pgprot_t prot) 411 { 412 struct pci_dev *pdev = NULL; 413 struct resource *found = NULL; 414 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 415 int i; 416 417 if (page_is_ram(pfn)) 418 return prot; 419 420 prot = pgprot_noncached(prot); 421 for_each_pci_dev(pdev) { 422 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 423 struct resource *rp = &pdev->resource[i]; 424 int flags = rp->flags; 425 426 /* Active and same type? */ 427 if ((flags & IORESOURCE_MEM) == 0) 428 continue; 429 /* In the range of this resource? */ 430 if (offset < (rp->start & PAGE_MASK) || 431 offset > rp->end) 432 continue; 433 found = rp; 434 break; 435 } 436 if (found) 437 break; 438 } 439 if (found) { 440 if (found->flags & IORESOURCE_PREFETCH) 441 prot = pgprot_noncached_wc(prot); 442 pci_dev_put(pdev); 443 } 444 445 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 446 (unsigned long long)offset, pgprot_val(prot)); 447 448 return prot; 449 } 450 451 452 /* 453 * Perform the actual remap of the pages for a PCI device mapping, as 454 * appropriate for this architecture. The region in the process to map 455 * is described by vm_start and vm_end members of VMA, the base physical 456 * address is found in vm_pgoff. 457 * The pci device structure is provided so that architectures may make mapping 458 * decisions on a per-device or per-bus basis. 459 * 460 * Returns a negative error code on failure, zero on success. 461 */ 462 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 463 enum pci_mmap_state mmap_state, int write_combine) 464 { 465 resource_size_t offset = 466 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 467 struct resource *rp; 468 int ret; 469 470 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 471 if (rp == NULL) 472 return -EINVAL; 473 474 vma->vm_pgoff = offset >> PAGE_SHIFT; 475 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 476 vma->vm_page_prot, 477 mmap_state, write_combine); 478 479 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 480 vma->vm_end - vma->vm_start, vma->vm_page_prot); 481 482 return ret; 483 } 484 485 /* This provides legacy IO read access on a bus */ 486 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 487 { 488 unsigned long offset; 489 struct pci_controller *hose = pci_bus_to_host(bus); 490 struct resource *rp = &hose->io_resource; 491 void __iomem *addr; 492 493 /* Check if port can be supported by that bus. We only check 494 * the ranges of the PHB though, not the bus itself as the rules 495 * for forwarding legacy cycles down bridges are not our problem 496 * here. So if the host bridge supports it, we do it. 497 */ 498 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 499 offset += port; 500 501 if (!(rp->flags & IORESOURCE_IO)) 502 return -ENXIO; 503 if (offset < rp->start || (offset + size) > rp->end) 504 return -ENXIO; 505 addr = hose->io_base_virt + port; 506 507 switch(size) { 508 case 1: 509 *((u8 *)val) = in_8(addr); 510 return 1; 511 case 2: 512 if (port & 1) 513 return -EINVAL; 514 *((u16 *)val) = in_le16(addr); 515 return 2; 516 case 4: 517 if (port & 3) 518 return -EINVAL; 519 *((u32 *)val) = in_le32(addr); 520 return 4; 521 } 522 return -EINVAL; 523 } 524 525 /* This provides legacy IO write access on a bus */ 526 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 527 { 528 unsigned long offset; 529 struct pci_controller *hose = pci_bus_to_host(bus); 530 struct resource *rp = &hose->io_resource; 531 void __iomem *addr; 532 533 /* Check if port can be supported by that bus. We only check 534 * the ranges of the PHB though, not the bus itself as the rules 535 * for forwarding legacy cycles down bridges are not our problem 536 * here. So if the host bridge supports it, we do it. 537 */ 538 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 539 offset += port; 540 541 if (!(rp->flags & IORESOURCE_IO)) 542 return -ENXIO; 543 if (offset < rp->start || (offset + size) > rp->end) 544 return -ENXIO; 545 addr = hose->io_base_virt + port; 546 547 /* WARNING: The generic code is idiotic. It gets passed a pointer 548 * to what can be a 1, 2 or 4 byte quantity and always reads that 549 * as a u32, which means that we have to correct the location of 550 * the data read within those 32 bits for size 1 and 2 551 */ 552 switch(size) { 553 case 1: 554 out_8(addr, val >> 24); 555 return 1; 556 case 2: 557 if (port & 1) 558 return -EINVAL; 559 out_le16(addr, val >> 16); 560 return 2; 561 case 4: 562 if (port & 3) 563 return -EINVAL; 564 out_le32(addr, val); 565 return 4; 566 } 567 return -EINVAL; 568 } 569 570 /* This provides legacy IO or memory mmap access on a bus */ 571 int pci_mmap_legacy_page_range(struct pci_bus *bus, 572 struct vm_area_struct *vma, 573 enum pci_mmap_state mmap_state) 574 { 575 struct pci_controller *hose = pci_bus_to_host(bus); 576 resource_size_t offset = 577 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 578 resource_size_t size = vma->vm_end - vma->vm_start; 579 struct resource *rp; 580 581 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 582 pci_domain_nr(bus), bus->number, 583 mmap_state == pci_mmap_mem ? "MEM" : "IO", 584 (unsigned long long)offset, 585 (unsigned long long)(offset + size - 1)); 586 587 if (mmap_state == pci_mmap_mem) { 588 /* Hack alert ! 589 * 590 * Because X is lame and can fail starting if it gets an error trying 591 * to mmap legacy_mem (instead of just moving on without legacy memory 592 * access) we fake it here by giving it anonymous memory, effectively 593 * behaving just like /dev/zero 594 */ 595 if ((offset + size) > hose->isa_mem_size) { 596 printk(KERN_DEBUG 597 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 598 current->comm, current->pid, pci_domain_nr(bus), bus->number); 599 if (vma->vm_flags & VM_SHARED) 600 return shmem_zero_setup(vma); 601 return 0; 602 } 603 offset += hose->isa_mem_phys; 604 } else { 605 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 606 unsigned long roffset = offset + io_offset; 607 rp = &hose->io_resource; 608 if (!(rp->flags & IORESOURCE_IO)) 609 return -ENXIO; 610 if (roffset < rp->start || (roffset + size) > rp->end) 611 return -ENXIO; 612 offset += hose->io_base_phys; 613 } 614 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 615 616 vma->vm_pgoff = offset >> PAGE_SHIFT; 617 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 618 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 619 vma->vm_end - vma->vm_start, 620 vma->vm_page_prot); 621 } 622 623 void pci_resource_to_user(const struct pci_dev *dev, int bar, 624 const struct resource *rsrc, 625 resource_size_t *start, resource_size_t *end) 626 { 627 struct pci_controller *hose = pci_bus_to_host(dev->bus); 628 resource_size_t offset = 0; 629 630 if (hose == NULL) 631 return; 632 633 if (rsrc->flags & IORESOURCE_IO) 634 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 635 636 /* We pass a fully fixed up address to userland for MMIO instead of 637 * a BAR value because X is lame and expects to be able to use that 638 * to pass to /dev/mem ! 639 * 640 * That means that we'll have potentially 64 bits values where some 641 * userland apps only expect 32 (like X itself since it thinks only 642 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 643 * 32 bits CHRPs :-( 644 * 645 * Hopefully, the sysfs insterface is immune to that gunk. Once X 646 * has been fixed (and the fix spread enough), we can re-enable the 647 * 2 lines below and pass down a BAR value to userland. In that case 648 * we'll also have to re-enable the matching code in 649 * __pci_mmap_make_offset(). 650 * 651 * BenH. 652 */ 653 #if 0 654 else if (rsrc->flags & IORESOURCE_MEM) 655 offset = hose->pci_mem_offset; 656 #endif 657 658 *start = rsrc->start - offset; 659 *end = rsrc->end - offset; 660 } 661 662 /** 663 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 664 * @hose: newly allocated pci_controller to be setup 665 * @dev: device node of the host bridge 666 * @primary: set if primary bus (32 bits only, soon to be deprecated) 667 * 668 * This function will parse the "ranges" property of a PCI host bridge device 669 * node and setup the resource mapping of a pci controller based on its 670 * content. 671 * 672 * Life would be boring if it wasn't for a few issues that we have to deal 673 * with here: 674 * 675 * - We can only cope with one IO space range and up to 3 Memory space 676 * ranges. However, some machines (thanks Apple !) tend to split their 677 * space into lots of small contiguous ranges. So we have to coalesce. 678 * 679 * - Some busses have IO space not starting at 0, which causes trouble with 680 * the way we do our IO resource renumbering. The code somewhat deals with 681 * it for 64 bits but I would expect problems on 32 bits. 682 * 683 * - Some 32 bits platforms such as 4xx can have physical space larger than 684 * 32 bits so we need to use 64 bits values for the parsing 685 */ 686 void pci_process_bridge_OF_ranges(struct pci_controller *hose, 687 struct device_node *dev, int primary) 688 { 689 const __be32 *ranges; 690 int rlen; 691 int pna = of_n_addr_cells(dev); 692 int np = pna + 5; 693 int memno = 0; 694 u32 pci_space; 695 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 696 struct resource *res; 697 698 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 699 dev->full_name, primary ? "(primary)" : ""); 700 701 /* Get ranges property */ 702 ranges = of_get_property(dev, "ranges", &rlen); 703 if (ranges == NULL) 704 return; 705 706 /* Parse it */ 707 while ((rlen -= np * 4) >= 0) { 708 /* Read next ranges element */ 709 pci_space = of_read_number(ranges, 1); 710 pci_addr = of_read_number(ranges + 1, 2); 711 cpu_addr = of_translate_address(dev, ranges + 3); 712 size = of_read_number(ranges + pna + 3, 2); 713 ranges += np; 714 715 /* If we failed translation or got a zero-sized region 716 * (some FW try to feed us with non sensical zero sized regions 717 * such as power3 which look like some kind of attempt at exposing 718 * the VGA memory hole) 719 */ 720 if (cpu_addr == OF_BAD_ADDR || size == 0) 721 continue; 722 723 /* Now consume following elements while they are contiguous */ 724 for (; rlen >= np * sizeof(u32); 725 ranges += np, rlen -= np * 4) { 726 if (of_read_number(ranges, 1) != pci_space) 727 break; 728 pci_next = of_read_number(ranges + 1, 2); 729 cpu_next = of_translate_address(dev, ranges + 3); 730 if (pci_next != pci_addr + size || 731 cpu_next != cpu_addr + size) 732 break; 733 size += of_read_number(ranges + pna + 3, 2); 734 } 735 736 /* Act based on address space type */ 737 res = NULL; 738 switch ((pci_space >> 24) & 0x3) { 739 case 1: /* PCI IO space */ 740 printk(KERN_INFO 741 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 742 cpu_addr, cpu_addr + size - 1, pci_addr); 743 744 /* We support only one IO range */ 745 if (hose->pci_io_size) { 746 printk(KERN_INFO 747 " \\--> Skipped (too many) !\n"); 748 continue; 749 } 750 #ifdef CONFIG_PPC32 751 /* On 32 bits, limit I/O space to 16MB */ 752 if (size > 0x01000000) 753 size = 0x01000000; 754 755 /* 32 bits needs to map IOs here */ 756 hose->io_base_virt = ioremap(cpu_addr, size); 757 758 /* Expect trouble if pci_addr is not 0 */ 759 if (primary) 760 isa_io_base = 761 (unsigned long)hose->io_base_virt; 762 #endif /* CONFIG_PPC32 */ 763 /* pci_io_size and io_base_phys always represent IO 764 * space starting at 0 so we factor in pci_addr 765 */ 766 hose->pci_io_size = pci_addr + size; 767 hose->io_base_phys = cpu_addr - pci_addr; 768 769 /* Build resource */ 770 res = &hose->io_resource; 771 res->flags = IORESOURCE_IO; 772 res->start = pci_addr; 773 break; 774 case 2: /* PCI Memory space */ 775 case 3: /* PCI 64 bits Memory space */ 776 printk(KERN_INFO 777 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 778 cpu_addr, cpu_addr + size - 1, pci_addr, 779 (pci_space & 0x40000000) ? "Prefetch" : ""); 780 781 /* We support only 3 memory ranges */ 782 if (memno >= 3) { 783 printk(KERN_INFO 784 " \\--> Skipped (too many) !\n"); 785 continue; 786 } 787 /* Handles ISA memory hole space here */ 788 if (pci_addr == 0) { 789 if (primary || isa_mem_base == 0) 790 isa_mem_base = cpu_addr; 791 hose->isa_mem_phys = cpu_addr; 792 hose->isa_mem_size = size; 793 } 794 795 /* Build resource */ 796 hose->mem_offset[memno] = cpu_addr - pci_addr; 797 res = &hose->mem_resources[memno++]; 798 res->flags = IORESOURCE_MEM; 799 if (pci_space & 0x40000000) 800 res->flags |= IORESOURCE_PREFETCH; 801 res->start = cpu_addr; 802 break; 803 } 804 if (res != NULL) { 805 res->name = dev->full_name; 806 res->end = res->start + size - 1; 807 res->parent = NULL; 808 res->sibling = NULL; 809 res->child = NULL; 810 } 811 } 812 } 813 814 /* Decide whether to display the domain number in /proc */ 815 int pci_proc_domain(struct pci_bus *bus) 816 { 817 struct pci_controller *hose = pci_bus_to_host(bus); 818 819 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 820 return 0; 821 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 822 return hose->global_number != 0; 823 return 1; 824 } 825 826 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 827 { 828 if (ppc_md.pcibios_root_bridge_prepare) 829 return ppc_md.pcibios_root_bridge_prepare(bridge); 830 831 return 0; 832 } 833 834 /* This header fixup will do the resource fixup for all devices as they are 835 * probed, but not for bridge ranges 836 */ 837 static void pcibios_fixup_resources(struct pci_dev *dev) 838 { 839 struct pci_controller *hose = pci_bus_to_host(dev->bus); 840 int i; 841 842 if (!hose) { 843 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 844 pci_name(dev)); 845 return; 846 } 847 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 848 struct resource *res = dev->resource + i; 849 struct pci_bus_region reg; 850 if (!res->flags) 851 continue; 852 853 /* If we're going to re-assign everything, we mark all resources 854 * as unset (and 0-base them). In addition, we mark BARs starting 855 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 856 * since in that case, we don't want to re-assign anything 857 */ 858 pcibios_resource_to_bus(dev->bus, ®, res); 859 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 860 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 861 /* Only print message if not re-assigning */ 862 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 863 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " 864 "is unassigned\n", 865 pci_name(dev), i, 866 (unsigned long long)res->start, 867 (unsigned long long)res->end, 868 (unsigned int)res->flags); 869 res->end -= res->start; 870 res->start = 0; 871 res->flags |= IORESOURCE_UNSET; 872 continue; 873 } 874 875 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", 876 pci_name(dev), i, 877 (unsigned long long)res->start,\ 878 (unsigned long long)res->end, 879 (unsigned int)res->flags); 880 } 881 882 /* Call machine specific resource fixup */ 883 if (ppc_md.pcibios_fixup_resources) 884 ppc_md.pcibios_fixup_resources(dev); 885 } 886 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 887 888 /* This function tries to figure out if a bridge resource has been initialized 889 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 890 * things go more smoothly when it gets it right. It should covers cases such 891 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 892 */ 893 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 894 struct resource *res) 895 { 896 struct pci_controller *hose = pci_bus_to_host(bus); 897 struct pci_dev *dev = bus->self; 898 resource_size_t offset; 899 struct pci_bus_region region; 900 u16 command; 901 int i; 902 903 /* We don't do anything if PCI_PROBE_ONLY is set */ 904 if (pci_has_flag(PCI_PROBE_ONLY)) 905 return 0; 906 907 /* Job is a bit different between memory and IO */ 908 if (res->flags & IORESOURCE_MEM) { 909 pcibios_resource_to_bus(dev->bus, ®ion, res); 910 911 /* If the BAR is non-0 then it's probably been initialized */ 912 if (region.start != 0) 913 return 0; 914 915 /* The BAR is 0, let's check if memory decoding is enabled on 916 * the bridge. If not, we consider it unassigned 917 */ 918 pci_read_config_word(dev, PCI_COMMAND, &command); 919 if ((command & PCI_COMMAND_MEMORY) == 0) 920 return 1; 921 922 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 923 * resources covers that starting address (0 then it's good enough for 924 * us for memory space) 925 */ 926 for (i = 0; i < 3; i++) { 927 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 928 hose->mem_resources[i].start == hose->mem_offset[i]) 929 return 0; 930 } 931 932 /* Well, it starts at 0 and we know it will collide so we may as 933 * well consider it as unassigned. That covers the Apple case. 934 */ 935 return 1; 936 } else { 937 /* If the BAR is non-0, then we consider it assigned */ 938 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 939 if (((res->start - offset) & 0xfffffffful) != 0) 940 return 0; 941 942 /* Here, we are a bit different than memory as typically IO space 943 * starting at low addresses -is- valid. What we do instead if that 944 * we consider as unassigned anything that doesn't have IO enabled 945 * in the PCI command register, and that's it. 946 */ 947 pci_read_config_word(dev, PCI_COMMAND, &command); 948 if (command & PCI_COMMAND_IO) 949 return 0; 950 951 /* It's starting at 0 and IO is disabled in the bridge, consider 952 * it unassigned 953 */ 954 return 1; 955 } 956 } 957 958 /* Fixup resources of a PCI<->PCI bridge */ 959 static void pcibios_fixup_bridge(struct pci_bus *bus) 960 { 961 struct resource *res; 962 int i; 963 964 struct pci_dev *dev = bus->self; 965 966 pci_bus_for_each_resource(bus, res, i) { 967 if (!res || !res->flags) 968 continue; 969 if (i >= 3 && bus->self->transparent) 970 continue; 971 972 /* If we're going to reassign everything, we can 973 * shrink the P2P resource to have size as being 974 * of 0 in order to save space. 975 */ 976 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 977 res->flags |= IORESOURCE_UNSET; 978 res->start = 0; 979 res->end = -1; 980 continue; 981 } 982 983 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", 984 pci_name(dev), i, 985 (unsigned long long)res->start,\ 986 (unsigned long long)res->end, 987 (unsigned int)res->flags); 988 989 /* Try to detect uninitialized P2P bridge resources, 990 * and clear them out so they get re-assigned later 991 */ 992 if (pcibios_uninitialized_bridge_resource(bus, res)) { 993 res->flags = 0; 994 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 995 } 996 } 997 } 998 999 void pcibios_setup_bus_self(struct pci_bus *bus) 1000 { 1001 /* Fix up the bus resources for P2P bridges */ 1002 if (bus->self != NULL) 1003 pcibios_fixup_bridge(bus); 1004 1005 /* Platform specific bus fixups. This is currently only used 1006 * by fsl_pci and I'm hoping to get rid of it at some point 1007 */ 1008 if (ppc_md.pcibios_fixup_bus) 1009 ppc_md.pcibios_fixup_bus(bus); 1010 1011 /* Setup bus DMA mappings */ 1012 if (ppc_md.pci_dma_bus_setup) 1013 ppc_md.pci_dma_bus_setup(bus); 1014 } 1015 1016 static void pcibios_setup_device(struct pci_dev *dev) 1017 { 1018 /* Fixup NUMA node as it may not be setup yet by the generic 1019 * code and is needed by the DMA init 1020 */ 1021 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1022 1023 /* Hook up default DMA ops */ 1024 set_dma_ops(&dev->dev, pci_dma_ops); 1025 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 1026 1027 /* Additional platform DMA/iommu setup */ 1028 if (ppc_md.pci_dma_dev_setup) 1029 ppc_md.pci_dma_dev_setup(dev); 1030 1031 /* Read default IRQs and fixup if necessary */ 1032 pci_read_irq_line(dev); 1033 if (ppc_md.pci_irq_fixup) 1034 ppc_md.pci_irq_fixup(dev); 1035 } 1036 1037 int pcibios_add_device(struct pci_dev *dev) 1038 { 1039 /* 1040 * We can only call pcibios_setup_device() after bus setup is complete, 1041 * since some of the platform specific DMA setup code depends on it. 1042 */ 1043 if (dev->bus->is_added) 1044 pcibios_setup_device(dev); 1045 return 0; 1046 } 1047 1048 void pcibios_setup_bus_devices(struct pci_bus *bus) 1049 { 1050 struct pci_dev *dev; 1051 1052 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1053 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1054 1055 list_for_each_entry(dev, &bus->devices, bus_list) { 1056 /* Cardbus can call us to add new devices to a bus, so ignore 1057 * those who are already fully discovered 1058 */ 1059 if (dev->is_added) 1060 continue; 1061 1062 pcibios_setup_device(dev); 1063 } 1064 } 1065 1066 void pcibios_set_master(struct pci_dev *dev) 1067 { 1068 /* No special bus mastering setup handling */ 1069 } 1070 1071 void pcibios_fixup_bus(struct pci_bus *bus) 1072 { 1073 /* When called from the generic PCI probe, read PCI<->PCI bridge 1074 * bases. This is -not- called when generating the PCI tree from 1075 * the OF device-tree. 1076 */ 1077 pci_read_bridge_bases(bus); 1078 1079 /* Now fixup the bus bus */ 1080 pcibios_setup_bus_self(bus); 1081 1082 /* Now fixup devices on that bus */ 1083 pcibios_setup_bus_devices(bus); 1084 } 1085 EXPORT_SYMBOL(pcibios_fixup_bus); 1086 1087 void pci_fixup_cardbus(struct pci_bus *bus) 1088 { 1089 /* Now fixup devices on that bus */ 1090 pcibios_setup_bus_devices(bus); 1091 } 1092 1093 1094 static int skip_isa_ioresource_align(struct pci_dev *dev) 1095 { 1096 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1097 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1098 return 1; 1099 return 0; 1100 } 1101 1102 /* 1103 * We need to avoid collisions with `mirrored' VGA ports 1104 * and other strange ISA hardware, so we always want the 1105 * addresses to be allocated in the 0x000-0x0ff region 1106 * modulo 0x400. 1107 * 1108 * Why? Because some silly external IO cards only decode 1109 * the low 10 bits of the IO address. The 0x00-0xff region 1110 * is reserved for motherboard devices that decode all 16 1111 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1112 * but we want to try to avoid allocating at 0x2900-0x2bff 1113 * which might have be mirrored at 0x0100-0x03ff.. 1114 */ 1115 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1116 resource_size_t size, resource_size_t align) 1117 { 1118 struct pci_dev *dev = data; 1119 resource_size_t start = res->start; 1120 1121 if (res->flags & IORESOURCE_IO) { 1122 if (skip_isa_ioresource_align(dev)) 1123 return start; 1124 if (start & 0x300) 1125 start = (start + 0x3ff) & ~0x3ff; 1126 } 1127 1128 return start; 1129 } 1130 EXPORT_SYMBOL(pcibios_align_resource); 1131 1132 /* 1133 * Reparent resource children of pr that conflict with res 1134 * under res, and make res replace those children. 1135 */ 1136 static int reparent_resources(struct resource *parent, 1137 struct resource *res) 1138 { 1139 struct resource *p, **pp; 1140 struct resource **firstpp = NULL; 1141 1142 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1143 if (p->end < res->start) 1144 continue; 1145 if (res->end < p->start) 1146 break; 1147 if (p->start < res->start || p->end > res->end) 1148 return -1; /* not completely contained */ 1149 if (firstpp == NULL) 1150 firstpp = pp; 1151 } 1152 if (firstpp == NULL) 1153 return -1; /* didn't find any conflicting entries? */ 1154 res->parent = parent; 1155 res->child = *firstpp; 1156 res->sibling = *pp; 1157 *firstpp = res; 1158 *pp = NULL; 1159 for (p = res->child; p != NULL; p = p->sibling) { 1160 p->parent = res; 1161 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1162 p->name, 1163 (unsigned long long)p->start, 1164 (unsigned long long)p->end, res->name); 1165 } 1166 return 0; 1167 } 1168 1169 /* 1170 * Handle resources of PCI devices. If the world were perfect, we could 1171 * just allocate all the resource regions and do nothing more. It isn't. 1172 * On the other hand, we cannot just re-allocate all devices, as it would 1173 * require us to know lots of host bridge internals. So we attempt to 1174 * keep as much of the original configuration as possible, but tweak it 1175 * when it's found to be wrong. 1176 * 1177 * Known BIOS problems we have to work around: 1178 * - I/O or memory regions not configured 1179 * - regions configured, but not enabled in the command register 1180 * - bogus I/O addresses above 64K used 1181 * - expansion ROMs left enabled (this may sound harmless, but given 1182 * the fact the PCI specs explicitly allow address decoders to be 1183 * shared between expansion ROMs and other resource regions, it's 1184 * at least dangerous) 1185 * 1186 * Our solution: 1187 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1188 * This gives us fixed barriers on where we can allocate. 1189 * (2) Allocate resources for all enabled devices. If there is 1190 * a collision, just mark the resource as unallocated. Also 1191 * disable expansion ROMs during this step. 1192 * (3) Try to allocate resources for disabled devices. If the 1193 * resources were assigned correctly, everything goes well, 1194 * if they weren't, they won't disturb allocation of other 1195 * resources. 1196 * (4) Assign new addresses to resources which were either 1197 * not configured at all or misconfigured. If explicitly 1198 * requested by the user, configure expansion ROM address 1199 * as well. 1200 */ 1201 1202 void pcibios_allocate_bus_resources(struct pci_bus *bus) 1203 { 1204 struct pci_bus *b; 1205 int i; 1206 struct resource *res, *pr; 1207 1208 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1209 pci_domain_nr(bus), bus->number); 1210 1211 pci_bus_for_each_resource(bus, res, i) { 1212 if (!res || !res->flags || res->start > res->end || res->parent) 1213 continue; 1214 1215 /* If the resource was left unset at this point, we clear it */ 1216 if (res->flags & IORESOURCE_UNSET) 1217 goto clear_resource; 1218 1219 if (bus->parent == NULL) 1220 pr = (res->flags & IORESOURCE_IO) ? 1221 &ioport_resource : &iomem_resource; 1222 else { 1223 pr = pci_find_parent_resource(bus->self, res); 1224 if (pr == res) { 1225 /* this happens when the generic PCI 1226 * code (wrongly) decides that this 1227 * bridge is transparent -- paulus 1228 */ 1229 continue; 1230 } 1231 } 1232 1233 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1234 "[0x%x], parent %p (%s)\n", 1235 bus->self ? pci_name(bus->self) : "PHB", 1236 bus->number, i, 1237 (unsigned long long)res->start, 1238 (unsigned long long)res->end, 1239 (unsigned int)res->flags, 1240 pr, (pr && pr->name) ? pr->name : "nil"); 1241 1242 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1243 if (request_resource(pr, res) == 0) 1244 continue; 1245 /* 1246 * Must be a conflict with an existing entry. 1247 * Move that entry (or entries) under the 1248 * bridge resource and try again. 1249 */ 1250 if (reparent_resources(pr, res) == 0) 1251 continue; 1252 } 1253 pr_warning("PCI: Cannot allocate resource region " 1254 "%d of PCI bridge %d, will remap\n", i, bus->number); 1255 clear_resource: 1256 /* The resource might be figured out when doing 1257 * reassignment based on the resources required 1258 * by the downstream PCI devices. Here we set 1259 * the size of the resource to be 0 in order to 1260 * save more space. 1261 */ 1262 res->start = 0; 1263 res->end = -1; 1264 res->flags = 0; 1265 } 1266 1267 list_for_each_entry(b, &bus->children, node) 1268 pcibios_allocate_bus_resources(b); 1269 } 1270 1271 static inline void alloc_resource(struct pci_dev *dev, int idx) 1272 { 1273 struct resource *pr, *r = &dev->resource[idx]; 1274 1275 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1276 pci_name(dev), idx, 1277 (unsigned long long)r->start, 1278 (unsigned long long)r->end, 1279 (unsigned int)r->flags); 1280 1281 pr = pci_find_parent_resource(dev, r); 1282 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1283 request_resource(pr, r) < 0) { 1284 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1285 " of device %s, will remap\n", idx, pci_name(dev)); 1286 if (pr) 1287 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1288 pr, 1289 (unsigned long long)pr->start, 1290 (unsigned long long)pr->end, 1291 (unsigned int)pr->flags); 1292 /* We'll assign a new address later */ 1293 r->flags |= IORESOURCE_UNSET; 1294 r->end -= r->start; 1295 r->start = 0; 1296 } 1297 } 1298 1299 static void __init pcibios_allocate_resources(int pass) 1300 { 1301 struct pci_dev *dev = NULL; 1302 int idx, disabled; 1303 u16 command; 1304 struct resource *r; 1305 1306 for_each_pci_dev(dev) { 1307 pci_read_config_word(dev, PCI_COMMAND, &command); 1308 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1309 r = &dev->resource[idx]; 1310 if (r->parent) /* Already allocated */ 1311 continue; 1312 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1313 continue; /* Not assigned at all */ 1314 /* We only allocate ROMs on pass 1 just in case they 1315 * have been screwed up by firmware 1316 */ 1317 if (idx == PCI_ROM_RESOURCE ) 1318 disabled = 1; 1319 if (r->flags & IORESOURCE_IO) 1320 disabled = !(command & PCI_COMMAND_IO); 1321 else 1322 disabled = !(command & PCI_COMMAND_MEMORY); 1323 if (pass == disabled) 1324 alloc_resource(dev, idx); 1325 } 1326 if (pass) 1327 continue; 1328 r = &dev->resource[PCI_ROM_RESOURCE]; 1329 if (r->flags) { 1330 /* Turn the ROM off, leave the resource region, 1331 * but keep it unregistered. 1332 */ 1333 u32 reg; 1334 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1335 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1336 pr_debug("PCI: Switching off ROM of %s\n", 1337 pci_name(dev)); 1338 r->flags &= ~IORESOURCE_ROM_ENABLE; 1339 pci_write_config_dword(dev, dev->rom_base_reg, 1340 reg & ~PCI_ROM_ADDRESS_ENABLE); 1341 } 1342 } 1343 } 1344 } 1345 1346 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1347 { 1348 struct pci_controller *hose = pci_bus_to_host(bus); 1349 resource_size_t offset; 1350 struct resource *res, *pres; 1351 int i; 1352 1353 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1354 1355 /* Check for IO */ 1356 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1357 goto no_io; 1358 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1359 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1360 BUG_ON(res == NULL); 1361 res->name = "Legacy IO"; 1362 res->flags = IORESOURCE_IO; 1363 res->start = offset; 1364 res->end = (offset + 0xfff) & 0xfffffffful; 1365 pr_debug("Candidate legacy IO: %pR\n", res); 1366 if (request_resource(&hose->io_resource, res)) { 1367 printk(KERN_DEBUG 1368 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1369 pci_domain_nr(bus), bus->number, res); 1370 kfree(res); 1371 } 1372 1373 no_io: 1374 /* Check for memory */ 1375 for (i = 0; i < 3; i++) { 1376 pres = &hose->mem_resources[i]; 1377 offset = hose->mem_offset[i]; 1378 if (!(pres->flags & IORESOURCE_MEM)) 1379 continue; 1380 pr_debug("hose mem res: %pR\n", pres); 1381 if ((pres->start - offset) <= 0xa0000 && 1382 (pres->end - offset) >= 0xbffff) 1383 break; 1384 } 1385 if (i >= 3) 1386 return; 1387 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1388 BUG_ON(res == NULL); 1389 res->name = "Legacy VGA memory"; 1390 res->flags = IORESOURCE_MEM; 1391 res->start = 0xa0000 + offset; 1392 res->end = 0xbffff + offset; 1393 pr_debug("Candidate VGA memory: %pR\n", res); 1394 if (request_resource(pres, res)) { 1395 printk(KERN_DEBUG 1396 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1397 pci_domain_nr(bus), bus->number, res); 1398 kfree(res); 1399 } 1400 } 1401 1402 void __init pcibios_resource_survey(void) 1403 { 1404 struct pci_bus *b; 1405 1406 /* Allocate and assign resources */ 1407 list_for_each_entry(b, &pci_root_buses, node) 1408 pcibios_allocate_bus_resources(b); 1409 pcibios_allocate_resources(0); 1410 pcibios_allocate_resources(1); 1411 1412 /* Before we start assigning unassigned resource, we try to reserve 1413 * the low IO area and the VGA memory area if they intersect the 1414 * bus available resources to avoid allocating things on top of them 1415 */ 1416 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1417 list_for_each_entry(b, &pci_root_buses, node) 1418 pcibios_reserve_legacy_regions(b); 1419 } 1420 1421 /* Now, if the platform didn't decide to blindly trust the firmware, 1422 * we proceed to assigning things that were left unassigned 1423 */ 1424 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1425 pr_debug("PCI: Assigning unassigned resources...\n"); 1426 pci_assign_unassigned_resources(); 1427 } 1428 1429 /* Call machine dependent fixup */ 1430 if (ppc_md.pcibios_fixup) 1431 ppc_md.pcibios_fixup(); 1432 } 1433 1434 /* This is used by the PCI hotplug driver to allocate resource 1435 * of newly plugged busses. We can try to consolidate with the 1436 * rest of the code later, for now, keep it as-is as our main 1437 * resource allocation function doesn't deal with sub-trees yet. 1438 */ 1439 void pcibios_claim_one_bus(struct pci_bus *bus) 1440 { 1441 struct pci_dev *dev; 1442 struct pci_bus *child_bus; 1443 1444 list_for_each_entry(dev, &bus->devices, bus_list) { 1445 int i; 1446 1447 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1448 struct resource *r = &dev->resource[i]; 1449 1450 if (r->parent || !r->start || !r->flags) 1451 continue; 1452 1453 pr_debug("PCI: Claiming %s: " 1454 "Resource %d: %016llx..%016llx [%x]\n", 1455 pci_name(dev), i, 1456 (unsigned long long)r->start, 1457 (unsigned long long)r->end, 1458 (unsigned int)r->flags); 1459 1460 pci_claim_resource(dev, i); 1461 } 1462 } 1463 1464 list_for_each_entry(child_bus, &bus->children, node) 1465 pcibios_claim_one_bus(child_bus); 1466 } 1467 1468 1469 /* pcibios_finish_adding_to_bus 1470 * 1471 * This is to be called by the hotplug code after devices have been 1472 * added to a bus, this include calling it for a PHB that is just 1473 * being added 1474 */ 1475 void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1476 { 1477 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1478 pci_domain_nr(bus), bus->number); 1479 1480 /* Allocate bus and devices resources */ 1481 pcibios_allocate_bus_resources(bus); 1482 pcibios_claim_one_bus(bus); 1483 if (!pci_has_flag(PCI_PROBE_ONLY)) 1484 pci_assign_unassigned_bus_resources(bus); 1485 1486 /* Fixup EEH */ 1487 eeh_add_device_tree_late(bus); 1488 1489 /* Add new devices to global lists. Register in proc, sysfs. */ 1490 pci_bus_add_devices(bus); 1491 1492 /* sysfs files should only be added after devices are added */ 1493 eeh_add_sysfs_files(bus); 1494 } 1495 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1496 1497 int pcibios_enable_device(struct pci_dev *dev, int mask) 1498 { 1499 if (ppc_md.pcibios_enable_device_hook) 1500 if (ppc_md.pcibios_enable_device_hook(dev)) 1501 return -EINVAL; 1502 1503 return pci_enable_resources(dev, mask); 1504 } 1505 1506 resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1507 { 1508 return (unsigned long) hose->io_base_virt - _IO_BASE; 1509 } 1510 1511 static void pcibios_setup_phb_resources(struct pci_controller *hose, 1512 struct list_head *resources) 1513 { 1514 struct resource *res; 1515 resource_size_t offset; 1516 int i; 1517 1518 /* Hookup PHB IO resource */ 1519 res = &hose->io_resource; 1520 1521 if (!res->flags) { 1522 printk(KERN_WARNING "PCI: I/O resource not set for host" 1523 " bridge %s (domain %d)\n", 1524 hose->dn->full_name, hose->global_number); 1525 } else { 1526 offset = pcibios_io_space_offset(hose); 1527 1528 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n", 1529 (unsigned long long)res->start, 1530 (unsigned long long)res->end, 1531 (unsigned long)res->flags, 1532 (unsigned long long)offset); 1533 pci_add_resource_offset(resources, res, offset); 1534 } 1535 1536 /* Hookup PHB Memory resources */ 1537 for (i = 0; i < 3; ++i) { 1538 res = &hose->mem_resources[i]; 1539 if (!res->flags) { 1540 if (i == 0) 1541 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1542 "host bridge %s (domain %d)\n", 1543 hose->dn->full_name, hose->global_number); 1544 continue; 1545 } 1546 offset = hose->mem_offset[i]; 1547 1548 1549 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i, 1550 (unsigned long long)res->start, 1551 (unsigned long long)res->end, 1552 (unsigned long)res->flags, 1553 (unsigned long long)offset); 1554 1555 pci_add_resource_offset(resources, res, offset); 1556 } 1557 } 1558 1559 /* 1560 * Null PCI config access functions, for the case when we can't 1561 * find a hose. 1562 */ 1563 #define NULL_PCI_OP(rw, size, type) \ 1564 static int \ 1565 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1566 { \ 1567 return PCIBIOS_DEVICE_NOT_FOUND; \ 1568 } 1569 1570 static int 1571 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1572 int len, u32 *val) 1573 { 1574 return PCIBIOS_DEVICE_NOT_FOUND; 1575 } 1576 1577 static int 1578 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1579 int len, u32 val) 1580 { 1581 return PCIBIOS_DEVICE_NOT_FOUND; 1582 } 1583 1584 static struct pci_ops null_pci_ops = 1585 { 1586 .read = null_read_config, 1587 .write = null_write_config, 1588 }; 1589 1590 /* 1591 * These functions are used early on before PCI scanning is done 1592 * and all of the pci_dev and pci_bus structures have been created. 1593 */ 1594 static struct pci_bus * 1595 fake_pci_bus(struct pci_controller *hose, int busnr) 1596 { 1597 static struct pci_bus bus; 1598 1599 if (hose == NULL) { 1600 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1601 } 1602 bus.number = busnr; 1603 bus.sysdata = hose; 1604 bus.ops = hose? hose->ops: &null_pci_ops; 1605 return &bus; 1606 } 1607 1608 #define EARLY_PCI_OP(rw, size, type) \ 1609 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1610 int devfn, int offset, type value) \ 1611 { \ 1612 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1613 devfn, offset, value); \ 1614 } 1615 1616 EARLY_PCI_OP(read, byte, u8 *) 1617 EARLY_PCI_OP(read, word, u16 *) 1618 EARLY_PCI_OP(read, dword, u32 *) 1619 EARLY_PCI_OP(write, byte, u8) 1620 EARLY_PCI_OP(write, word, u16) 1621 EARLY_PCI_OP(write, dword, u32) 1622 1623 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); 1624 int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1625 int cap) 1626 { 1627 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1628 } 1629 1630 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1631 { 1632 struct pci_controller *hose = bus->sysdata; 1633 1634 return of_node_get(hose->dn); 1635 } 1636 1637 /** 1638 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1639 * @hose: Pointer to the PCI host controller instance structure 1640 */ 1641 void pcibios_scan_phb(struct pci_controller *hose) 1642 { 1643 LIST_HEAD(resources); 1644 struct pci_bus *bus; 1645 struct device_node *node = hose->dn; 1646 int mode; 1647 1648 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); 1649 1650 /* Get some IO space for the new PHB */ 1651 pcibios_setup_phb_io_space(hose); 1652 1653 /* Wire up PHB bus resources */ 1654 pcibios_setup_phb_resources(hose, &resources); 1655 1656 hose->busn.start = hose->first_busno; 1657 hose->busn.end = hose->last_busno; 1658 hose->busn.flags = IORESOURCE_BUS; 1659 pci_add_resource(&resources, &hose->busn); 1660 1661 /* Create an empty bus for the toplevel */ 1662 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1663 hose->ops, hose, &resources); 1664 if (bus == NULL) { 1665 pr_err("Failed to create bus for PCI domain %04x\n", 1666 hose->global_number); 1667 pci_free_resource_list(&resources); 1668 return; 1669 } 1670 hose->bus = bus; 1671 1672 /* Get probe mode and perform scan */ 1673 mode = PCI_PROBE_NORMAL; 1674 if (node && ppc_md.pci_probe_mode) 1675 mode = ppc_md.pci_probe_mode(bus); 1676 pr_debug(" probe mode: %d\n", mode); 1677 if (mode == PCI_PROBE_DEVTREE) 1678 of_scan_bus(node, bus); 1679 1680 if (mode == PCI_PROBE_NORMAL) { 1681 pci_bus_update_busn_res_end(bus, 255); 1682 hose->last_busno = pci_scan_child_bus(bus); 1683 pci_bus_update_busn_res_end(bus, hose->last_busno); 1684 } 1685 1686 /* Platform gets a chance to do some global fixups before 1687 * we proceed to resource allocation 1688 */ 1689 if (ppc_md.pcibios_fixup_phb) 1690 ppc_md.pcibios_fixup_phb(hose); 1691 1692 /* Configure PCI Express settings */ 1693 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1694 struct pci_bus *child; 1695 list_for_each_entry(child, &bus->children, node) 1696 pcie_bus_configure_settings(child); 1697 } 1698 } 1699 1700 static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1701 { 1702 int i, class = dev->class >> 8; 1703 /* When configured as agent, programing interface = 1 */ 1704 int prog_if = dev->class & 0xf; 1705 1706 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1707 class == PCI_CLASS_BRIDGE_OTHER) && 1708 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1709 (prog_if == 0) && 1710 (dev->bus->parent == NULL)) { 1711 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1712 dev->resource[i].start = 0; 1713 dev->resource[i].end = 0; 1714 dev->resource[i].flags = 0; 1715 } 1716 } 1717 } 1718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1720 1721 static void fixup_vga(struct pci_dev *pdev) 1722 { 1723 u16 cmd; 1724 1725 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1726 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) 1727 vga_set_default_device(pdev); 1728 1729 } 1730 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1731 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); 1732