io.h (27eb2c4b3d3e13f376a359e293c212a2e9407af5) io.h (ecd73cc5c9e137559f4625b347f20cf9ed0de3d5)
1#ifndef _ASM_POWERPC_IO_H
2#define _ASM_POWERPC_IO_H
3#ifdef __KERNEL__
4
5#define ARCH_HAS_IOREMAP_WC
6
7/*
8 * This program is free software; you can redistribute it and/or

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64#endif
65
66extern unsigned long isa_io_base;
67extern unsigned long pci_io_base;
68extern unsigned long pci_dram_offset;
69
70extern resource_size_t isa_mem_base;
71
1#ifndef _ASM_POWERPC_IO_H
2#define _ASM_POWERPC_IO_H
3#ifdef __KERNEL__
4
5#define ARCH_HAS_IOREMAP_WC
6
7/*
8 * This program is free software; you can redistribute it and/or

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64#endif
65
66extern unsigned long isa_io_base;
67extern unsigned long pci_io_base;
68extern unsigned long pci_dram_offset;
69
70extern resource_size_t isa_mem_base;
71
72#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
73#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
72#ifdef CONFIG_PPC32
73#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
74#error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
74#endif
75#endif
76#endif
75
76/*
77 *
78 * Low level MMIO accessors
79 *
80 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
81 * specific and thus shouldn't be used in generic code. The accessors
82 * provided here are:

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217 *
218 * PCI and standard ISA accessors
219 *
220 * Those are globally defined linux accessors for devices on PCI or ISA
221 * busses. They follow the Linux defined semantics. The current implementation
222 * for PowerPC is as close as possible to the x86 version of these, and thus
223 * provides fairly heavy weight barriers for the non-raw versions
224 *
77
78/*
79 *
80 * Low level MMIO accessors
81 *
82 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
83 * specific and thus shouldn't be used in generic code. The accessors
84 * provided here are:

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219 *
220 * PCI and standard ISA accessors
221 *
222 * Those are globally defined linux accessors for devices on PCI or ISA
223 * busses. They follow the Linux defined semantics. The current implementation
224 * for PowerPC is as close as possible to the x86 version of these, and thus
225 * provides fairly heavy weight barriers for the non-raw versions
226 *
225 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
226 * allowing the platform to provide its own implementation of some or all
227 * of the accessors.
227 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
228 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
229 * own implementation of some or all of the accessors.
228 */
229
230/*
231 * Include the EEH definitions when EEH is enabled only so they don't get
232 * in the way when building for 32 bits
233 */
234#ifdef CONFIG_EEH
235#include <asm/eeh.h>
236#endif
237
238/* Shortcut to the MMIO argument pointer */
239#define PCI_IO_ADDR volatile void __iomem *
240
241/* Indirect IO address tokens:
242 *
230 */
231
232/*
233 * Include the EEH definitions when EEH is enabled only so they don't get
234 * in the way when building for 32 bits
235 */
236#ifdef CONFIG_EEH
237#include <asm/eeh.h>
238#endif
239
240/* Shortcut to the MMIO argument pointer */
241#define PCI_IO_ADDR volatile void __iomem *
242
243/* Indirect IO address tokens:
244 *
243 * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
244 * on all IOs. (Note that this is all 64 bits only for now)
245 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
246 * on all MMIOs. (Note that this is all 64 bits only for now)
245 *
246 * To help platforms who may need to differenciate MMIO addresses in
247 * their hooks, a bitfield is reserved for use by the platform near the
248 * top of MMIO addresses (not PIO, those have to cope the hard way).
249 *
250 * This bit field is 12 bits and is at the top of the IO virtual
251 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
252 *

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258 * 0xD0000fffffffffff : end of ioremap region
259 *
260 * Since the top 4 bits are reserved as the region ID, we use thus
261 * the next 12 bits and keep 4 bits available for the future if the
262 * virtual address space is ever to be extended.
263 *
264 * The direct IO mapping operations will then mask off those bits
265 * before doing the actual access, though that only happen when
247 *
248 * To help platforms who may need to differenciate MMIO addresses in
249 * their hooks, a bitfield is reserved for use by the platform near the
250 * top of MMIO addresses (not PIO, those have to cope the hard way).
251 *
252 * This bit field is 12 bits and is at the top of the IO virtual
253 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
254 *

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260 * 0xD0000fffffffffff : end of ioremap region
261 *
262 * Since the top 4 bits are reserved as the region ID, we use thus
263 * the next 12 bits and keep 4 bits available for the future if the
264 * virtual address space is ever to be extended.
265 *
266 * The direct IO mapping operations will then mask off those bits
267 * before doing the actual access, though that only happen when
266 * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
268 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
267 * mechanism
269 * mechanism
270 *
271 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
272 * all PIO functions call through a hook.
268 */
269
273 */
274
270#ifdef CONFIG_PPC_INDIRECT_IO
275#ifdef CONFIG_PPC_INDIRECT_MMIO
271#define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
272#define PCI_IO_IND_TOKEN_SHIFT 48
273#define PCI_FIX_ADDR(addr) \
274 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
275#define PCI_GET_ADDR_TOKEN(addr) \
276 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
277 PCI_IO_IND_TOKEN_SHIFT)
278#define PCI_SET_ADDR_TOKEN(addr, token) \

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667
668extern void __iounmap(volatile void __iomem *addr);
669
670extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
671 unsigned long size, unsigned long flags);
672extern void __iounmap_at(void *ea, unsigned long size);
673
674/*
276#define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
277#define PCI_IO_IND_TOKEN_SHIFT 48
278#define PCI_FIX_ADDR(addr) \
279 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
280#define PCI_GET_ADDR_TOKEN(addr) \
281 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
282 PCI_IO_IND_TOKEN_SHIFT)
283#define PCI_SET_ADDR_TOKEN(addr, token) \

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672
673extern void __iounmap(volatile void __iomem *addr);
674
675extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
676 unsigned long size, unsigned long flags);
677extern void __iounmap_at(void *ea, unsigned long size);
678
679/*
675 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
680 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
676 * which needs some additional definitions here. They basically allow PIO
677 * space overall to be 1GB. This will work as long as we never try to use
678 * iomap to map MMIO below 1GB which should be fine on ppc64
679 */
680#define HAVE_ARCH_PIO_SIZE 1
681#define PIO_OFFSET 0x00000000UL
682#define PIO_MASK (FULL_IO_SIZE - 1)
683#define PIO_RESERVED (FULL_IO_SIZE)

--- 116 unchanged lines hidden --- 		681 * which needs some additional definitions here. They basically allow PIO
682 * space overall to be 1GB. This will work as long as we never try to use
683 * iomap to map MMIO below 1GB which should be fine on ppc64
684 */
685#define HAVE_ARCH_PIO_SIZE 1
686#define PIO_OFFSET 0x00000000UL
687#define PIO_MASK (FULL_IO_SIZE - 1)
688#define PIO_RESERVED (FULL_IO_SIZE)

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