1 #ifndef _ASM_POWERPC_IO_H 2 #define _ASM_POWERPC_IO_H 3 #ifdef __KERNEL__ 4 5 #define ARCH_HAS_IOREMAP_WC 6 7 /* 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 /* Check of existence of legacy devices */ 15 extern int check_legacy_ioport(unsigned long base_port); 16 #define I8042_DATA_REG 0x60 17 #define FDC_BASE 0x3f0 18 19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI) 20 extern struct pci_dev *isa_bridge_pcidev; 21 /* 22 * has legacy ISA devices ? 23 */ 24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL) 25 #endif 26 27 #include <linux/device.h> 28 #include <linux/io.h> 29 30 #include <linux/compiler.h> 31 #include <asm/page.h> 32 #include <asm/byteorder.h> 33 #include <asm/synch.h> 34 #include <asm/delay.h> 35 #include <asm/mmu.h> 36 37 #include <asm-generic/iomap.h> 38 39 #ifdef CONFIG_PPC64 40 #include <asm/paca.h> 41 #endif 42 43 #define SIO_CONFIG_RA 0x398 44 #define SIO_CONFIG_RD 0x399 45 46 #define SLOW_DOWN_IO 47 48 /* 32 bits uses slightly different variables for the various IO 49 * bases. Most of this file only uses _IO_BASE though which we 50 * define properly based on the platform 51 */ 52 #ifndef CONFIG_PCI 53 #define _IO_BASE 0 54 #define _ISA_MEM_BASE 0 55 #define PCI_DRAM_OFFSET 0 56 #elif defined(CONFIG_PPC32) 57 #define _IO_BASE isa_io_base 58 #define _ISA_MEM_BASE isa_mem_base 59 #define PCI_DRAM_OFFSET pci_dram_offset 60 #else 61 #define _IO_BASE pci_io_base 62 #define _ISA_MEM_BASE isa_mem_base 63 #define PCI_DRAM_OFFSET 0 64 #endif 65 66 extern unsigned long isa_io_base; 67 extern unsigned long pci_io_base; 68 extern unsigned long pci_dram_offset; 69 70 extern resource_size_t isa_mem_base; 71 72 #ifdef CONFIG_PPC32 73 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 74 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits 75 #endif 76 #endif 77 78 /* 79 * 80 * Low level MMIO accessors 81 * 82 * This provides the non-bus specific accessors to MMIO. Those are PowerPC 83 * specific and thus shouldn't be used in generic code. The accessors 84 * provided here are: 85 * 86 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 87 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 88 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns 89 * 90 * Those operate directly on a kernel virtual address. Note that the prototype 91 * for the out_* accessors has the arguments in opposite order from the usual 92 * linux PCI accessors. Unlike those, they take the address first and the value 93 * next. 94 * 95 * Note: I might drop the _ns suffix on the stream operations soon as it is 96 * simply normal for stream operations to not swap in the first place. 97 * 98 */ 99 100 #ifdef CONFIG_PPC64 101 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0) 102 #else 103 #define IO_SET_SYNC_FLAG() 104 #endif 105 106 /* gcc 4.0 and older doesn't have 'Z' constraint */ 107 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0) 108 #define DEF_MMIO_IN_LE(name, size, insn) \ 109 static inline u##size name(const volatile u##size __iomem *addr) \ 110 { \ 111 u##size ret; \ 112 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \ 113 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \ 114 return ret; \ 115 } 116 117 #define DEF_MMIO_OUT_LE(name, size, insn) \ 118 static inline void name(volatile u##size __iomem *addr, u##size val) \ 119 { \ 120 __asm__ __volatile__("sync;"#insn" %1,0,%2" \ 121 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \ 122 IO_SET_SYNC_FLAG(); \ 123 } 124 #else /* newer gcc */ 125 #define DEF_MMIO_IN_LE(name, size, insn) \ 126 static inline u##size name(const volatile u##size __iomem *addr) \ 127 { \ 128 u##size ret; \ 129 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ 130 : "=r" (ret) : "Z" (*addr) : "memory"); \ 131 return ret; \ 132 } 133 134 #define DEF_MMIO_OUT_LE(name, size, insn) \ 135 static inline void name(volatile u##size __iomem *addr, u##size val) \ 136 { \ 137 __asm__ __volatile__("sync;"#insn" %1,%y0" \ 138 : "=Z" (*addr) : "r" (val) : "memory"); \ 139 IO_SET_SYNC_FLAG(); \ 140 } 141 #endif 142 143 #define DEF_MMIO_IN_BE(name, size, insn) \ 144 static inline u##size name(const volatile u##size __iomem *addr) \ 145 { \ 146 u##size ret; \ 147 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ 148 : "=r" (ret) : "m" (*addr) : "memory"); \ 149 return ret; \ 150 } 151 152 #define DEF_MMIO_OUT_BE(name, size, insn) \ 153 static inline void name(volatile u##size __iomem *addr, u##size val) \ 154 { \ 155 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ 156 : "=m" (*addr) : "r" (val) : "memory"); \ 157 IO_SET_SYNC_FLAG(); \ 158 } 159 160 161 DEF_MMIO_IN_BE(in_8, 8, lbz); 162 DEF_MMIO_IN_BE(in_be16, 16, lhz); 163 DEF_MMIO_IN_BE(in_be32, 32, lwz); 164 DEF_MMIO_IN_LE(in_le16, 16, lhbrx); 165 DEF_MMIO_IN_LE(in_le32, 32, lwbrx); 166 167 DEF_MMIO_OUT_BE(out_8, 8, stb); 168 DEF_MMIO_OUT_BE(out_be16, 16, sth); 169 DEF_MMIO_OUT_BE(out_be32, 32, stw); 170 DEF_MMIO_OUT_LE(out_le16, 16, sthbrx); 171 DEF_MMIO_OUT_LE(out_le32, 32, stwbrx); 172 173 #ifdef __powerpc64__ 174 DEF_MMIO_OUT_BE(out_be64, 64, std); 175 DEF_MMIO_IN_BE(in_be64, 64, ld); 176 177 /* There is no asm instructions for 64 bits reverse loads and stores */ 178 static inline u64 in_le64(const volatile u64 __iomem *addr) 179 { 180 return swab64(in_be64(addr)); 181 } 182 183 static inline void out_le64(volatile u64 __iomem *addr, u64 val) 184 { 185 out_be64(addr, swab64(val)); 186 } 187 #endif /* __powerpc64__ */ 188 189 /* 190 * Low level IO stream instructions are defined out of line for now 191 */ 192 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); 193 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); 194 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); 195 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); 196 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); 197 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); 198 199 /* The _ns naming is historical and will be removed. For now, just #define 200 * the non _ns equivalent names 201 */ 202 #define _insw _insw_ns 203 #define _insl _insl_ns 204 #define _outsw _outsw_ns 205 #define _outsl _outsl_ns 206 207 208 /* 209 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line 210 */ 211 212 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); 213 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, 214 unsigned long n); 215 extern void _memcpy_toio(volatile void __iomem *dest, const void *src, 216 unsigned long n); 217 218 /* 219 * 220 * PCI and standard ISA accessors 221 * 222 * Those are globally defined linux accessors for devices on PCI or ISA 223 * busses. They follow the Linux defined semantics. The current implementation 224 * for PowerPC is as close as possible to the x86 version of these, and thus 225 * provides fairly heavy weight barriers for the non-raw versions 226 * 227 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO 228 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its 229 * own implementation of some or all of the accessors. 230 */ 231 232 /* 233 * Include the EEH definitions when EEH is enabled only so they don't get 234 * in the way when building for 32 bits 235 */ 236 #ifdef CONFIG_EEH 237 #include <asm/eeh.h> 238 #endif 239 240 /* Shortcut to the MMIO argument pointer */ 241 #define PCI_IO_ADDR volatile void __iomem * 242 243 /* Indirect IO address tokens: 244 * 245 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks 246 * on all MMIOs. (Note that this is all 64 bits only for now) 247 * 248 * To help platforms who may need to differenciate MMIO addresses in 249 * their hooks, a bitfield is reserved for use by the platform near the 250 * top of MMIO addresses (not PIO, those have to cope the hard way). 251 * 252 * This bit field is 12 bits and is at the top of the IO virtual 253 * addresses PCI_IO_INDIRECT_TOKEN_MASK. 254 * 255 * The kernel virtual space is thus: 256 * 257 * 0xD000000000000000 : vmalloc 258 * 0xD000080000000000 : PCI PHB IO space 259 * 0xD000080080000000 : ioremap 260 * 0xD0000fffffffffff : end of ioremap region 261 * 262 * Since the top 4 bits are reserved as the region ID, we use thus 263 * the next 12 bits and keep 4 bits available for the future if the 264 * virtual address space is ever to be extended. 265 * 266 * The direct IO mapping operations will then mask off those bits 267 * before doing the actual access, though that only happen when 268 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that 269 * mechanism 270 * 271 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes 272 * all PIO functions call through a hook. 273 */ 274 275 #ifdef CONFIG_PPC_INDIRECT_MMIO 276 #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul 277 #define PCI_IO_IND_TOKEN_SHIFT 48 278 #define PCI_FIX_ADDR(addr) \ 279 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) 280 #define PCI_GET_ADDR_TOKEN(addr) \ 281 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ 282 PCI_IO_IND_TOKEN_SHIFT) 283 #define PCI_SET_ADDR_TOKEN(addr, token) \ 284 do { \ 285 unsigned long __a = (unsigned long)(addr); \ 286 __a &= ~PCI_IO_IND_TOKEN_MASK; \ 287 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ 288 (addr) = (void __iomem *)__a; \ 289 } while(0) 290 #else 291 #define PCI_FIX_ADDR(addr) (addr) 292 #endif 293 294 295 /* 296 * Non ordered and non-swapping "raw" accessors 297 */ 298 299 static inline unsigned char __raw_readb(const volatile void __iomem *addr) 300 { 301 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); 302 } 303 static inline unsigned short __raw_readw(const volatile void __iomem *addr) 304 { 305 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); 306 } 307 static inline unsigned int __raw_readl(const volatile void __iomem *addr) 308 { 309 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); 310 } 311 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 312 { 313 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; 314 } 315 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 316 { 317 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; 318 } 319 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 320 { 321 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; 322 } 323 324 #ifdef __powerpc64__ 325 static inline unsigned long __raw_readq(const volatile void __iomem *addr) 326 { 327 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); 328 } 329 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 330 { 331 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; 332 } 333 #endif /* __powerpc64__ */ 334 335 /* 336 * 337 * PCI PIO and MMIO accessors. 338 * 339 * 340 * On 32 bits, PIO operations have a recovery mechanism in case they trigger 341 * machine checks (which they occasionally do when probing non existing 342 * IO ports on some platforms, like PowerMac and 8xx). 343 * I always found it to be of dubious reliability and I am tempted to get 344 * rid of it one of these days. So if you think it's important to keep it, 345 * please voice up asap. We never had it for 64 bits and I do not intend 346 * to port it over 347 */ 348 349 #ifdef CONFIG_PPC32 350 351 #define __do_in_asm(name, op) \ 352 static inline unsigned int name(unsigned int port) \ 353 { \ 354 unsigned int x; \ 355 __asm__ __volatile__( \ 356 "sync\n" \ 357 "0:" op " %0,0,%1\n" \ 358 "1: twi 0,%0,0\n" \ 359 "2: isync\n" \ 360 "3: nop\n" \ 361 "4:\n" \ 362 ".section .fixup,\"ax\"\n" \ 363 "5: li %0,-1\n" \ 364 " b 4b\n" \ 365 ".previous\n" \ 366 ".section __ex_table,\"a\"\n" \ 367 " .align 2\n" \ 368 " .long 0b,5b\n" \ 369 " .long 1b,5b\n" \ 370 " .long 2b,5b\n" \ 371 " .long 3b,5b\n" \ 372 ".previous" \ 373 : "=&r" (x) \ 374 : "r" (port + _IO_BASE) \ 375 : "memory"); \ 376 return x; \ 377 } 378 379 #define __do_out_asm(name, op) \ 380 static inline void name(unsigned int val, unsigned int port) \ 381 { \ 382 __asm__ __volatile__( \ 383 "sync\n" \ 384 "0:" op " %0,0,%1\n" \ 385 "1: sync\n" \ 386 "2:\n" \ 387 ".section __ex_table,\"a\"\n" \ 388 " .align 2\n" \ 389 " .long 0b,2b\n" \ 390 " .long 1b,2b\n" \ 391 ".previous" \ 392 : : "r" (val), "r" (port + _IO_BASE) \ 393 : "memory"); \ 394 } 395 396 __do_in_asm(_rec_inb, "lbzx") 397 __do_in_asm(_rec_inw, "lhbrx") 398 __do_in_asm(_rec_inl, "lwbrx") 399 __do_out_asm(_rec_outb, "stbx") 400 __do_out_asm(_rec_outw, "sthbrx") 401 __do_out_asm(_rec_outl, "stwbrx") 402 403 #endif /* CONFIG_PPC32 */ 404 405 /* The "__do_*" operations below provide the actual "base" implementation 406 * for each of the defined accessors. Some of them use the out_* functions 407 * directly, some of them still use EEH, though we might change that in the 408 * future. Those macros below provide the necessary argument swapping and 409 * handling of the IO base for PIO. 410 * 411 * They are themselves used by the macros that define the actual accessors 412 * and can be used by the hooks if any. 413 * 414 * Note that PIO operations are always defined in terms of their corresonding 415 * MMIO operations. That allows platforms like iSeries who want to modify the 416 * behaviour of both to only hook on the MMIO version and get both. It's also 417 * possible to hook directly at the toplevel PIO operation if they have to 418 * be handled differently 419 */ 420 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) 421 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) 422 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) 423 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) 424 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) 425 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) 426 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) 427 428 #ifdef CONFIG_EEH 429 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) 430 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) 431 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) 432 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) 433 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) 434 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) 435 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) 436 #else /* CONFIG_EEH */ 437 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) 438 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) 439 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) 440 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) 441 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) 442 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) 443 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) 444 #endif /* !defined(CONFIG_EEH) */ 445 446 #ifdef CONFIG_PPC32 447 #define __do_outb(val, port) _rec_outb(val, port) 448 #define __do_outw(val, port) _rec_outw(val, port) 449 #define __do_outl(val, port) _rec_outl(val, port) 450 #define __do_inb(port) _rec_inb(port) 451 #define __do_inw(port) _rec_inw(port) 452 #define __do_inl(port) _rec_inl(port) 453 #else /* CONFIG_PPC32 */ 454 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); 455 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); 456 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); 457 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); 458 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); 459 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); 460 #endif /* !CONFIG_PPC32 */ 461 462 #ifdef CONFIG_EEH 463 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) 464 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) 465 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) 466 #else /* CONFIG_EEH */ 467 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) 468 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) 469 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) 470 #endif /* !CONFIG_EEH */ 471 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) 472 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) 473 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) 474 475 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 476 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 477 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 478 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 479 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 480 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 481 482 #define __do_memset_io(addr, c, n) \ 483 _memset_io(PCI_FIX_ADDR(addr), c, n) 484 #define __do_memcpy_toio(dst, src, n) \ 485 _memcpy_toio(PCI_FIX_ADDR(dst), src, n) 486 487 #ifdef CONFIG_EEH 488 #define __do_memcpy_fromio(dst, src, n) \ 489 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) 490 #else /* CONFIG_EEH */ 491 #define __do_memcpy_fromio(dst, src, n) \ 492 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) 493 #endif /* !CONFIG_EEH */ 494 495 #ifdef CONFIG_PPC_INDIRECT_PIO 496 #define DEF_PCI_HOOK_pio(x) x 497 #else 498 #define DEF_PCI_HOOK_pio(x) NULL 499 #endif 500 501 #ifdef CONFIG_PPC_INDIRECT_MMIO 502 #define DEF_PCI_HOOK_mem(x) x 503 #else 504 #define DEF_PCI_HOOK_mem(x) NULL 505 #endif 506 507 /* Structure containing all the hooks */ 508 extern struct ppc_pci_io { 509 510 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at; 511 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at; 512 513 #include <asm/io-defs.h> 514 515 #undef DEF_PCI_AC_RET 516 #undef DEF_PCI_AC_NORET 517 518 } ppc_pci_io; 519 520 /* The inline wrappers */ 521 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ 522 static inline ret name at \ 523 { \ 524 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 525 return ppc_pci_io.name al; \ 526 return __do_##name al; \ 527 } 528 529 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \ 530 static inline void name at \ 531 { \ 532 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 533 ppc_pci_io.name al; \ 534 else \ 535 __do_##name al; \ 536 } 537 538 #include <asm/io-defs.h> 539 540 #undef DEF_PCI_AC_RET 541 #undef DEF_PCI_AC_NORET 542 543 /* Some drivers check for the presence of readq & writeq with 544 * a #ifdef, so we make them happy here. 545 */ 546 #ifdef __powerpc64__ 547 #define readq readq 548 #define writeq writeq 549 #endif 550 551 /* 552 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 553 * access 554 */ 555 #define xlate_dev_mem_ptr(p) __va(p) 556 557 /* 558 * Convert a virtual cached pointer to an uncached pointer 559 */ 560 #define xlate_dev_kmem_ptr(p) p 561 562 /* 563 * We don't do relaxed operations yet, at least not with this semantic 564 */ 565 #define readb_relaxed(addr) readb(addr) 566 #define readw_relaxed(addr) readw(addr) 567 #define readl_relaxed(addr) readl(addr) 568 #define readq_relaxed(addr) readq(addr) 569 570 #ifdef CONFIG_PPC32 571 #define mmiowb() 572 #else 573 /* 574 * Enforce synchronisation of stores vs. spin_unlock 575 * (this does it explicitly, though our implementation of spin_unlock 576 * does it implicitely too) 577 */ 578 static inline void mmiowb(void) 579 { 580 unsigned long tmp; 581 582 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)" 583 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) 584 : "memory"); 585 } 586 #endif /* !CONFIG_PPC32 */ 587 588 static inline void iosync(void) 589 { 590 __asm__ __volatile__ ("sync" : : : "memory"); 591 } 592 593 /* Enforce in-order execution of data I/O. 594 * No distinction between read/write on PPC; use eieio for all three. 595 * Those are fairly week though. They don't provide a barrier between 596 * MMIO and cacheable storage nor do they provide a barrier vs. locks, 597 * they only provide barriers between 2 __raw MMIO operations and 598 * possibly break write combining. 599 */ 600 #define iobarrier_rw() eieio() 601 #define iobarrier_r() eieio() 602 #define iobarrier_w() eieio() 603 604 605 /* 606 * output pause versions need a delay at least for the 607 * w83c105 ide controller in a p610. 608 */ 609 #define inb_p(port) inb(port) 610 #define outb_p(val, port) (udelay(1), outb((val), (port))) 611 #define inw_p(port) inw(port) 612 #define outw_p(val, port) (udelay(1), outw((val), (port))) 613 #define inl_p(port) inl(port) 614 #define outl_p(val, port) (udelay(1), outl((val), (port))) 615 616 617 #define IO_SPACE_LIMIT ~(0UL) 618 619 620 /** 621 * ioremap - map bus memory into CPU space 622 * @address: bus address of the memory 623 * @size: size of the resource to map 624 * 625 * ioremap performs a platform specific sequence of operations to 626 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 627 * writew/writel functions and the other mmio helpers. The returned 628 * address is not guaranteed to be usable directly as a virtual 629 * address. 630 * 631 * We provide a few variations of it: 632 * 633 * * ioremap is the standard one and provides non-cacheable guarded mappings 634 * and can be hooked by the platform via ppc_md 635 * 636 * * ioremap_prot allows to specify the page flags as an argument and can 637 * also be hooked by the platform via ppc_md. 638 * 639 * * ioremap_nocache is identical to ioremap 640 * 641 * * ioremap_wc enables write combining 642 * 643 * * iounmap undoes such a mapping and can be hooked 644 * 645 * * __ioremap_at (and the pending __iounmap_at) are low level functions to 646 * create hand-made mappings for use only by the PCI code and cannot 647 * currently be hooked. Must be page aligned. 648 * 649 * * __ioremap is the low level implementation used by ioremap and 650 * ioremap_prot and cannot be hooked (but can be used by a hook on one 651 * of the previous ones) 652 * 653 * * __ioremap_caller is the same as above but takes an explicit caller 654 * reference rather than using __builtin_return_address(0) 655 * 656 * * __iounmap, is the low level implementation used by iounmap and cannot 657 * be hooked (but can be used by a hook on iounmap) 658 * 659 */ 660 extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 661 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size, 662 unsigned long flags); 663 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size); 664 #define ioremap_nocache(addr, size) ioremap((addr), (size)) 665 666 extern void iounmap(volatile void __iomem *addr); 667 668 extern void __iomem *__ioremap(phys_addr_t, unsigned long size, 669 unsigned long flags); 670 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size, 671 unsigned long flags, void *caller); 672 673 extern void __iounmap(volatile void __iomem *addr); 674 675 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea, 676 unsigned long size, unsigned long flags); 677 extern void __iounmap_at(void *ea, unsigned long size); 678 679 /* 680 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation 681 * which needs some additional definitions here. They basically allow PIO 682 * space overall to be 1GB. This will work as long as we never try to use 683 * iomap to map MMIO below 1GB which should be fine on ppc64 684 */ 685 #define HAVE_ARCH_PIO_SIZE 1 686 #define PIO_OFFSET 0x00000000UL 687 #define PIO_MASK (FULL_IO_SIZE - 1) 688 #define PIO_RESERVED (FULL_IO_SIZE) 689 690 #define mmio_read16be(addr) readw_be(addr) 691 #define mmio_read32be(addr) readl_be(addr) 692 #define mmio_write16be(val, addr) writew_be(val, addr) 693 #define mmio_write32be(val, addr) writel_be(val, addr) 694 #define mmio_insb(addr, dst, count) readsb(addr, dst, count) 695 #define mmio_insw(addr, dst, count) readsw(addr, dst, count) 696 #define mmio_insl(addr, dst, count) readsl(addr, dst, count) 697 #define mmio_outsb(addr, src, count) writesb(addr, src, count) 698 #define mmio_outsw(addr, src, count) writesw(addr, src, count) 699 #define mmio_outsl(addr, src, count) writesl(addr, src, count) 700 701 /** 702 * virt_to_phys - map virtual addresses to physical 703 * @address: address to remap 704 * 705 * The returned physical address is the physical (CPU) mapping for 706 * the memory address given. It is only valid to use this function on 707 * addresses directly mapped or allocated via kmalloc. 708 * 709 * This function does not give bus mappings for DMA transfers. In 710 * almost all conceivable cases a device driver should not be using 711 * this function 712 */ 713 static inline unsigned long virt_to_phys(volatile void * address) 714 { 715 return __pa((unsigned long)address); 716 } 717 718 /** 719 * phys_to_virt - map physical address to virtual 720 * @address: address to remap 721 * 722 * The returned virtual address is a current CPU mapping for 723 * the memory address given. It is only valid to use this function on 724 * addresses that have a kernel mapping 725 * 726 * This function does not handle bus mappings for DMA transfers. In 727 * almost all conceivable cases a device driver should not be using 728 * this function 729 */ 730 static inline void * phys_to_virt(unsigned long address) 731 { 732 return (void *)__va(address); 733 } 734 735 /* 736 * Change "struct page" to physical address. 737 */ 738 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT) 739 740 /* 741 * 32 bits still uses virt_to_bus() for it's implementation of DMA 742 * mappings se we have to keep it defined here. We also have some old 743 * drivers (shame shame shame) that use bus_to_virt() and haven't been 744 * fixed yet so I need to define it here. 745 */ 746 #ifdef CONFIG_PPC32 747 748 static inline unsigned long virt_to_bus(volatile void * address) 749 { 750 if (address == NULL) 751 return 0; 752 return __pa(address) + PCI_DRAM_OFFSET; 753 } 754 755 static inline void * bus_to_virt(unsigned long address) 756 { 757 if (address == 0) 758 return NULL; 759 return __va(address - PCI_DRAM_OFFSET); 760 } 761 762 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) 763 764 #endif /* CONFIG_PPC32 */ 765 766 /* access ports */ 767 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) 768 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) 769 770 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) 771 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) 772 773 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) 774 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) 775 776 /* Clear and set bits in one shot. These macros can be used to clear and 777 * set multiple bits in a register using a single read-modify-write. These 778 * macros can also be used to set a multiple-bit bit pattern using a mask, 779 * by specifying the mask in the 'clear' parameter and the new bit pattern 780 * in the 'set' parameter. 781 */ 782 783 #define clrsetbits(type, addr, clear, set) \ 784 out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) 785 786 #ifdef __powerpc64__ 787 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) 788 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) 789 #endif 790 791 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) 792 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) 793 794 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) 795 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) 796 797 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) 798 799 void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset, 800 size_t size, unsigned long flags); 801 802 #endif /* __KERNEL__ */ 803 804 #endif /* _ASM_POWERPC_IO_H */ 805