jz4740.dtsi (36ba3eae036242fdc36eb8e89d5001a219a7fb1d) jz4740.dtsi (36aafdbd52881eda9073c4d03d65438a16b87a92)
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/jz4740-cgu.h>
3
4/ {
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "ingenic,jz4740";
8

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48 watchdog: watchdog@10002000 {
49 compatible = "ingenic,jz4740-watchdog";
50 reg = <0x10002000 0x10>;
51
52 clocks = <&cgu JZ4740_CLK_RTC>;
53 clock-names = "rtc";
54 };
55
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/jz4740-cgu.h>
3
4/ {
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "ingenic,jz4740";
8

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48 watchdog: watchdog@10002000 {
49 compatible = "ingenic,jz4740-watchdog";
50 reg = <0x10002000 0x10>;
51
52 clocks = <&cgu JZ4740_CLK_RTC>;
53 clock-names = "rtc";
54 };
55
56 tcu: timer@10002000 {
57 compatible = "ingenic,jz4740-tcu", "simple-mfd";
58 reg = <0x10002000 0x1000>;
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges = <0x0 0x10002000 0x1000>;
62
63 #clock-cells = <1>;
64
65 clocks = <&cgu JZ4740_CLK_RTC
66 &cgu JZ4740_CLK_EXT
67 &cgu JZ4740_CLK_PCLK
68 &cgu JZ4740_CLK_TCU>;
69 clock-names = "rtc", "ext", "pclk", "tcu";
70
71 interrupt-controller;
72 #interrupt-cells = <1>;
73
74 interrupt-parent = <&intc>;
75 interrupts = <23 22 21>;
76 };
77
56 rtc_dev: rtc@10003000 {
57 compatible = "ingenic,jz4740-rtc";
58 reg = <0x10003000 0x40>;
59
60 interrupt-parent = <&intc>;
61 interrupts = <15>;
62
63 clocks = <&cgu JZ4740_CLK_RTC>;

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127 interrupt-controller;
128 #interrupt-cells = <2>;
129
130 interrupt-parent = <&intc>;
131 interrupts = <25>;
132 };
133 };
134
78 rtc_dev: rtc@10003000 {
79 compatible = "ingenic,jz4740-rtc";
80 reg = <0x10003000 0x40>;
81
82 interrupt-parent = <&intc>;
83 interrupts = <15>;
84
85 clocks = <&cgu JZ4740_CLK_RTC>;

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149 interrupt-controller;
150 #interrupt-cells = <2>;
151
152 interrupt-parent = <&intc>;
153 interrupts = <25>;
154 };
155 };
156
135 aic: audio-controller@10020000 {
136 compatible = "ingenic,jz4740-i2s";
137 reg = <0x10020000 0x38>;
138
139 #sound-dai-cells = <0>;
140
141 interrupt-parent = <&intc>;
142 interrupts = <18>;
143
144 clocks = <&cgu JZ4740_CLK_AIC>,
145 <&cgu JZ4740_CLK_I2S>,
146 <&cgu JZ4740_CLK_EXT>,
147 <&cgu JZ4740_CLK_PLL_HALF>;
148 clock-names = "aic", "i2s", "ext", "pll half";
149
150 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
151 dma-names = "rx", "tx";
152 };
153
154 codec: audio-codec@100200a4 {
155 compatible = "ingenic,jz4740-codec";
156 reg = <0x10020080 0x8>;
157
158 #sound-dai-cells = <0>;
159
160 clocks = <&cgu JZ4740_CLK_AIC>;
161 clock-names = "aic";
162 };
163
164 mmc: mmc@10021000 {
165 compatible = "ingenic,jz4740-mmc";
166 reg = <0x10021000 0x1000>;
167
168 clocks = <&cgu JZ4740_CLK_MMC>;
169 clock-names = "mmc";
170
171 interrupt-parent = <&intc>;
172 interrupts = <14>;
173
174 dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
175 dma-names = "rx", "tx";
176
177 cap-sd-highspeed;
178 cap-mmc-highspeed;
179 cap-sdio-irq;
180 };
181
182 uart0: serial@10030000 {
183 compatible = "ingenic,jz4740-uart";
184 reg = <0x10030000 0x100>;
185
186 interrupt-parent = <&intc>;
187 interrupts = <9>;
188
189 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;

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196
197 interrupt-parent = <&intc>;
198 interrupts = <8>;
199
200 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
201 clock-names = "baud", "module";
202 };
203
157 uart0: serial@10030000 {
158 compatible = "ingenic,jz4740-uart";
159 reg = <0x10030000 0x100>;
160
161 interrupt-parent = <&intc>;
162 interrupts = <9>;
163
164 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;

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171
172 interrupt-parent = <&intc>;
173 interrupts = <8>;
174
175 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
176 clock-names = "baud", "module";
177 };
178
204 adc: adc@10070000 {
205 compatible = "ingenic,jz4740-adc";
206 reg = <0x10070000 0x30>;
207 #io-channel-cells = <1>;
208
209 clocks = <&cgu JZ4740_CLK_ADC>;
210 clock-names = "adc";
211
212 interrupt-parent = <&intc>;
213 interrupts = <12>;
214 };
215
216 nemc: memory-controller@13010000 {
217 compatible = "ingenic,jz4740-nemc";
218 reg = <0x13010000 0x54>;
219 #address-cells = <2>;
220 #size-cells = <1>;
221 ranges = <1 0 0x18000000 0x4000000
222 2 0 0x14000000 0x4000000
223 3 0 0x0c000000 0x4000000
224 4 0 0x08000000 0x4000000>;
225
226 clocks = <&cgu JZ4740_CLK_MCLK>;
227 };
228
229 ecc: ecc-controller@13010100 {
230 compatible = "ingenic,jz4740-ecc";
231 reg = <0x13010100 0x2C>;
232
233 clocks = <&cgu JZ4740_CLK_MCLK>;
234 };
235
236 dmac: dma-controller@13020000 {
237 compatible = "ingenic,jz4740-dma";
238 reg = <0x13020000 0xbc
239 0x13020300 0x14>;
240 #dma-cells = <2>;
241
242 interrupt-parent = <&intc>;
243 interrupts = <20>;
244
245 clocks = <&cgu JZ4740_CLK_DMA>;
179 dmac: dma-controller@13020000 {
180 compatible = "ingenic,jz4740-dma";
181 reg = <0x13020000 0xbc
182 0x13020300 0x14>;
183 #dma-cells = <2>;
184
185 interrupt-parent = <&intc>;
186 interrupts = <20>;
187
188 clocks = <&cgu JZ4740_CLK_DMA>;
189
190 /* Disable dmac until we have something that uses it */
191 status = "disabled";
246 };
247
248 uhc: uhc@13030000 {
249 compatible = "ingenic,jz4740-ohci", "generic-ohci";
250 reg = <0x13030000 0x1000>;
251
252 clocks = <&cgu JZ4740_CLK_UHC>;
253 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
254 assigned-clock-rates = <48000000>;
255
256 interrupt-parent = <&intc>;
257 interrupts = <3>;
258
259 status = "disabled";
260 };
192 };
193
194 uhc: uhc@13030000 {
195 compatible = "ingenic,jz4740-ohci", "generic-ohci";
196 reg = <0x13030000 0x1000>;
197
198 clocks = <&cgu JZ4740_CLK_UHC>;
199 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
200 assigned-clock-rates = <48000000>;
201
202 interrupt-parent = <&intc>;
203 interrupts = <3>;
204
205 status = "disabled";
206 };
261
262 udc: usb@13040000 {
263 compatible = "ingenic,jz4740-musb";
264 reg = <0x13040000 0x10000>;
265
266 interrupt-parent = <&intc>;
267 interrupts = <24>;
268 interrupt-names = "mc";
269
270 clocks = <&cgu JZ4740_CLK_UDC>;
271 clock-names = "udc";
272 };
273
274 lcd: lcd-controller@13050000 {
275 compatible = "ingenic,jz4740-lcd";
276 reg = <0x13050000 0x1000>;
277
278 interrupt-parent = <&intc>;
279 interrupts = <30>;
280
281 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
282 clock-names = "lcd_pclk", "lcd";
283 };
284};
207};