1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/jz4740-cgu.h> 3 4/ { 5 #address-cells = <1>; 6 #size-cells = <1>; 7 compatible = "ingenic,jz4740"; 8 9 cpuintc: interrupt-controller { 10 #address-cells = <0>; 11 #interrupt-cells = <1>; 12 interrupt-controller; 13 compatible = "mti,cpu-interrupt-controller"; 14 }; 15 16 intc: interrupt-controller@10001000 { 17 compatible = "ingenic,jz4740-intc"; 18 reg = <0x10001000 0x14>; 19 20 interrupt-controller; 21 #interrupt-cells = <1>; 22 23 interrupt-parent = <&cpuintc>; 24 interrupts = <2>; 25 }; 26 27 ext: ext { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 }; 31 32 rtc: rtc { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32768>; 36 }; 37 38 cgu: jz4740-cgu@10000000 { 39 compatible = "ingenic,jz4740-cgu"; 40 reg = <0x10000000 0x100>; 41 42 clocks = <&ext>, <&rtc>; 43 clock-names = "ext", "rtc"; 44 45 #clock-cells = <1>; 46 }; 47 48 watchdog: watchdog@10002000 { 49 compatible = "ingenic,jz4740-watchdog"; 50 reg = <0x10002000 0x10>; 51 52 clocks = <&cgu JZ4740_CLK_RTC>; 53 clock-names = "rtc"; 54 }; 55 56 tcu: timer@10002000 { 57 compatible = "ingenic,jz4740-tcu", "simple-mfd"; 58 reg = <0x10002000 0x1000>; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges = <0x0 0x10002000 0x1000>; 62 63 #clock-cells = <1>; 64 65 clocks = <&cgu JZ4740_CLK_RTC 66 &cgu JZ4740_CLK_EXT 67 &cgu JZ4740_CLK_PCLK 68 &cgu JZ4740_CLK_TCU>; 69 clock-names = "rtc", "ext", "pclk", "tcu"; 70 71 interrupt-controller; 72 #interrupt-cells = <1>; 73 74 interrupt-parent = <&intc>; 75 interrupts = <23 22 21>; 76 }; 77 78 rtc_dev: rtc@10003000 { 79 compatible = "ingenic,jz4740-rtc"; 80 reg = <0x10003000 0x40>; 81 82 interrupt-parent = <&intc>; 83 interrupts = <15>; 84 85 clocks = <&cgu JZ4740_CLK_RTC>; 86 clock-names = "rtc"; 87 }; 88 89 pinctrl: pin-controller@10010000 { 90 compatible = "ingenic,jz4740-pinctrl"; 91 reg = <0x10010000 0x400>; 92 93 #address-cells = <1>; 94 #size-cells = <0>; 95 96 gpa: gpio@0 { 97 compatible = "ingenic,jz4740-gpio"; 98 reg = <0>; 99 100 gpio-controller; 101 gpio-ranges = <&pinctrl 0 0 32>; 102 #gpio-cells = <2>; 103 104 interrupt-controller; 105 #interrupt-cells = <2>; 106 107 interrupt-parent = <&intc>; 108 interrupts = <28>; 109 }; 110 111 gpb: gpio@1 { 112 compatible = "ingenic,jz4740-gpio"; 113 reg = <1>; 114 115 gpio-controller; 116 gpio-ranges = <&pinctrl 0 32 32>; 117 #gpio-cells = <2>; 118 119 interrupt-controller; 120 #interrupt-cells = <2>; 121 122 interrupt-parent = <&intc>; 123 interrupts = <27>; 124 }; 125 126 gpc: gpio@2 { 127 compatible = "ingenic,jz4740-gpio"; 128 reg = <2>; 129 130 gpio-controller; 131 gpio-ranges = <&pinctrl 0 64 32>; 132 #gpio-cells = <2>; 133 134 interrupt-controller; 135 #interrupt-cells = <2>; 136 137 interrupt-parent = <&intc>; 138 interrupts = <26>; 139 }; 140 141 gpd: gpio@3 { 142 compatible = "ingenic,jz4740-gpio"; 143 reg = <3>; 144 145 gpio-controller; 146 gpio-ranges = <&pinctrl 0 96 32>; 147 #gpio-cells = <2>; 148 149 interrupt-controller; 150 #interrupt-cells = <2>; 151 152 interrupt-parent = <&intc>; 153 interrupts = <25>; 154 }; 155 }; 156 157 uart0: serial@10030000 { 158 compatible = "ingenic,jz4740-uart"; 159 reg = <0x10030000 0x100>; 160 161 interrupt-parent = <&intc>; 162 interrupts = <9>; 163 164 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>; 165 clock-names = "baud", "module"; 166 }; 167 168 uart1: serial@10031000 { 169 compatible = "ingenic,jz4740-uart"; 170 reg = <0x10031000 0x100>; 171 172 interrupt-parent = <&intc>; 173 interrupts = <8>; 174 175 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>; 176 clock-names = "baud", "module"; 177 }; 178 179 dmac: dma-controller@13020000 { 180 compatible = "ingenic,jz4740-dma"; 181 reg = <0x13020000 0xbc 182 0x13020300 0x14>; 183 #dma-cells = <2>; 184 185 interrupt-parent = <&intc>; 186 interrupts = <20>; 187 188 clocks = <&cgu JZ4740_CLK_DMA>; 189 190 /* Disable dmac until we have something that uses it */ 191 status = "disabled"; 192 }; 193 194 uhc: uhc@13030000 { 195 compatible = "ingenic,jz4740-ohci", "generic-ohci"; 196 reg = <0x13030000 0x1000>; 197 198 clocks = <&cgu JZ4740_CLK_UHC>; 199 assigned-clocks = <&cgu JZ4740_CLK_UHC>; 200 assigned-clock-rates = <48000000>; 201 202 interrupt-parent = <&intc>; 203 interrupts = <3>; 204 205 status = "disabled"; 206 }; 207}; 208