entry.h (bf241682936293291dcf40fd93cdd0f5e6222902) entry.h (f62e31623d718a7c20d9da98de48361624d7360a)
1/* SPDX-License-Identifier: GPL-2.0 */
2// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
3
4#ifndef __ASM_CSKY_ENTRY_H
5#define __ASM_CSKY_ENTRY_H
6
7#include <asm/setup.h>
8#include <abi/regdef.h>

--- 149 unchanged lines hidden (view full) ---

158 mtcr \rx, cr<4, 15>
159.endm
160
161.macro WR_MCIR rx
162 mtcr \rx, cr<8, 15>
163.endm
164
165.macro SETUP_MMU rx
1/* SPDX-License-Identifier: GPL-2.0 */
2// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
3
4#ifndef __ASM_CSKY_ENTRY_H
5#define __ASM_CSKY_ENTRY_H
6
7#include <asm/setup.h>
8#include <abi/regdef.h>

--- 149 unchanged lines hidden (view full) ---

158 mtcr \rx, cr<4, 15>
159.endm
160
161.macro WR_MCIR rx
162 mtcr \rx, cr<8, 15>
163.endm
164
165.macro SETUP_MMU rx
166 lrw \rx, PHYS_OFFSET | 0xe
166 /* Check MMU on | off */
167 mfcr \rx, cr18
168 btsti \rx, 0
169 bt 1f
170 grs \rx, 1f
171 br 2f
1721:
173 /*
174 * cr<30, 15> format:
175 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
176 * BA Reserved SH WA B SO SEC C D V
177 */
178 mfcr \rx, cr<30, 15>
1792:
180 lsri \rx, 28
181 lsli \rx, 28
182 addi \rx, 0x1ce
167 mtcr \rx, cr<30, 15>
183 mtcr \rx, cr<30, 15>
168 lrw \rx, (PHYS_OFFSET + 0x20000000) | 0xe
184
185 lsri \rx, 28
186 addi \rx, 2
187 lsli \rx, 28
188 addi \rx, 0x1ce
169 mtcr \rx, cr<31, 15>
170.endm
171
172.macro ANDI_R3 rx, imm
173 lsri \rx, 3
174 andi \rx, (\imm >> 3)
175.endm
176#endif /* __ASM_CSKY_ENTRY_H */
189 mtcr \rx, cr<31, 15>
190.endm
191
192.macro ANDI_R3 rx, imm
193 lsri \rx, 3
194 andi \rx, (\imm >> 3)
195.endm
196#endif /* __ASM_CSKY_ENTRY_H */