1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. 3 4 #ifndef __ASM_CSKY_ENTRY_H 5 #define __ASM_CSKY_ENTRY_H 6 7 #include <asm/setup.h> 8 #include <abi/regdef.h> 9 10 #define LSAVE_PC 8 11 #define LSAVE_PSR 12 12 #define LSAVE_A0 24 13 #define LSAVE_A1 28 14 #define LSAVE_A2 32 15 #define LSAVE_A3 36 16 17 #define KSPTOUSP 18 #define USPTOKSP 19 20 #define usp cr<14, 1> 21 22 .macro SAVE_ALL epc_inc 23 subi sp, 152 24 stw tls, (sp, 0) 25 stw lr, (sp, 4) 26 27 mfcr lr, epc 28 movi tls, \epc_inc 29 add lr, tls 30 stw lr, (sp, 8) 31 32 mfcr lr, epsr 33 stw lr, (sp, 12) 34 mfcr lr, usp 35 stw lr, (sp, 16) 36 37 stw a0, (sp, 20) 38 stw a0, (sp, 24) 39 stw a1, (sp, 28) 40 stw a2, (sp, 32) 41 stw a3, (sp, 36) 42 43 addi sp, 40 44 stm r4-r13, (sp) 45 46 addi sp, 40 47 stm r16-r30, (sp) 48 #ifdef CONFIG_CPU_HAS_HILO 49 mfhi lr 50 stw lr, (sp, 60) 51 mflo lr 52 stw lr, (sp, 64) 53 mfcr lr, cr14 54 stw lr, (sp, 68) 55 #endif 56 subi sp, 80 57 .endm 58 59 .macro RESTORE_ALL 60 psrclr ie 61 ldw tls, (sp, 0) 62 ldw lr, (sp, 4) 63 ldw a0, (sp, 8) 64 mtcr a0, epc 65 ldw a0, (sp, 12) 66 mtcr a0, epsr 67 ldw a0, (sp, 16) 68 mtcr a0, usp 69 70 #ifdef CONFIG_CPU_HAS_HILO 71 ldw a0, (sp, 140) 72 mthi a0 73 ldw a0, (sp, 144) 74 mtlo a0 75 ldw a0, (sp, 148) 76 mtcr a0, cr14 77 #endif 78 79 ldw a0, (sp, 24) 80 ldw a1, (sp, 28) 81 ldw a2, (sp, 32) 82 ldw a3, (sp, 36) 83 84 addi sp, 40 85 ldm r4-r13, (sp) 86 addi sp, 40 87 ldm r16-r30, (sp) 88 addi sp, 72 89 rte 90 .endm 91 92 .macro SAVE_SWITCH_STACK 93 subi sp, 64 94 stm r4-r11, (sp) 95 stw lr, (sp, 32) 96 stw r16, (sp, 36) 97 stw r17, (sp, 40) 98 stw r26, (sp, 44) 99 stw r27, (sp, 48) 100 stw r28, (sp, 52) 101 stw r29, (sp, 56) 102 stw r30, (sp, 60) 103 #ifdef CONFIG_CPU_HAS_HILO 104 subi sp, 16 105 mfhi lr 106 stw lr, (sp, 0) 107 mflo lr 108 stw lr, (sp, 4) 109 mfcr lr, cr14 110 stw lr, (sp, 8) 111 #endif 112 .endm 113 114 .macro RESTORE_SWITCH_STACK 115 #ifdef CONFIG_CPU_HAS_HILO 116 ldw lr, (sp, 0) 117 mthi lr 118 ldw lr, (sp, 4) 119 mtlo lr 120 ldw lr, (sp, 8) 121 mtcr lr, cr14 122 addi sp, 16 123 #endif 124 ldm r4-r11, (sp) 125 ldw lr, (sp, 32) 126 ldw r16, (sp, 36) 127 ldw r17, (sp, 40) 128 ldw r26, (sp, 44) 129 ldw r27, (sp, 48) 130 ldw r28, (sp, 52) 131 ldw r29, (sp, 56) 132 ldw r30, (sp, 60) 133 addi sp, 64 134 .endm 135 136 /* MMU registers operators. */ 137 .macro RD_MIR rx 138 mfcr \rx, cr<0, 15> 139 .endm 140 141 .macro RD_MEH rx 142 mfcr \rx, cr<4, 15> 143 .endm 144 145 .macro RD_MCIR rx 146 mfcr \rx, cr<8, 15> 147 .endm 148 149 .macro RD_PGDR rx 150 mfcr \rx, cr<29, 15> 151 .endm 152 153 .macro RD_PGDR_K rx 154 mfcr \rx, cr<28, 15> 155 .endm 156 157 .macro WR_MEH rx 158 mtcr \rx, cr<4, 15> 159 .endm 160 161 .macro WR_MCIR rx 162 mtcr \rx, cr<8, 15> 163 .endm 164 165 .macro SETUP_MMU rx 166 lrw \rx, PHYS_OFFSET | 0xe 167 mtcr \rx, cr<30, 15> 168 lrw \rx, (PHYS_OFFSET + 0x20000000) | 0xe 169 mtcr \rx, cr<31, 15> 170 .endm 171 172 .macro ANDI_R3 rx, imm 173 lsri \rx, 3 174 andi \rx, (\imm >> 3) 175 .endm 176 #endif /* __ASM_CSKY_ENTRY_H */ 177