copypage-v4wt.c (d73e60b7144a86baf0fdfcc9537a70bb4f72e11c) copypage-v4wt.c (063b0a4207e43acbeff3d4b09f43e750e0212b48)
1/*
2 * linux/arch/arm/mm/copypage-v4wt.S
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is for CPUs with a writethrough cache and 'flush ID cache' is
11 * the only supported cache operation.
12 */
13#include <linux/init.h>
1/*
2 * linux/arch/arm/mm/copypage-v4wt.S
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is for CPUs with a writethrough cache and 'flush ID cache' is
11 * the only supported cache operation.
12 */
13#include <linux/init.h>
14#include <linux/highmem.h>
14
15
15#include <asm/page.h>
16
17/*
16/*
18 * ARMv4 optimised copy_user_page
17 * ARMv4 optimised copy_user_highpage
19 *
20 * Since we have writethrough caches, we don't have to worry about
21 * dirty data in the cache. However, we do have to ensure that
22 * subsequent reads are up to date.
23 */
18 *
19 * Since we have writethrough caches, we don't have to worry about
20 * dirty data in the cache. However, we do have to ensure that
21 * subsequent reads are up to date.
22 */
24void __attribute__((naked))
25v4wt_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
23static void __attribute__((naked))
24v4wt_copy_user_page(void *kto, const void *kfrom)
26{
27 asm("\
28 stmfd sp!, {r4, lr} @ 2\n\
29 mov r2, %0 @ 1\n\
30 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
311: stmia r0!, {r3, r4, ip, lr} @ 4\n\
32 ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\
33 stmia r0!, {r3, r4, ip, lr} @ 4\n\

--- 5 unchanged lines hidden (view full) ---

39 ldmneia r1!, {r3, r4, ip, lr} @ 4\n\
40 bne 1b @ 1\n\
41 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\
42 ldmfd sp!, {r4, pc} @ 3"
43 :
44 : "I" (PAGE_SIZE / 64));
45}
46
25{
26 asm("\
27 stmfd sp!, {r4, lr} @ 2\n\
28 mov r2, %0 @ 1\n\
29 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
301: stmia r0!, {r3, r4, ip, lr} @ 4\n\
31 ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\
32 stmia r0!, {r3, r4, ip, lr} @ 4\n\

--- 5 unchanged lines hidden (view full) ---

38 ldmneia r1!, {r3, r4, ip, lr} @ 4\n\
39 bne 1b @ 1\n\
40 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\
41 ldmfd sp!, {r4, pc} @ 3"
42 :
43 : "I" (PAGE_SIZE / 64));
44}
45
46void v4wt_copy_user_highpage(struct page *to, struct page *from,
47 unsigned long vaddr)
48{
49 void *kto, *kfrom;
50
51 kto = kmap_atomic(to, KM_USER0);
52 kfrom = kmap_atomic(from, KM_USER1);
53 v4wt_copy_user_page(kto, kfrom);
54 kunmap_atomic(kfrom, KM_USER1);
55 kunmap_atomic(kto, KM_USER0);
56}
57
47/*
48 * ARMv4 optimised clear_user_page
49 *
50 * Same story as above.
51 */
52void __attribute__((naked))
53v4wt_clear_user_page(void *kaddr, unsigned long vaddr)
54{

--- 13 unchanged lines hidden (view full) ---

68 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\
69 ldr pc, [sp], #4"
70 :
71 : "I" (PAGE_SIZE / 64));
72}
73
74struct cpu_user_fns v4wt_user_fns __initdata = {
75 .cpu_clear_user_page = v4wt_clear_user_page,
58/*
59 * ARMv4 optimised clear_user_page
60 *
61 * Same story as above.
62 */
63void __attribute__((naked))
64v4wt_clear_user_page(void *kaddr, unsigned long vaddr)
65{

--- 13 unchanged lines hidden (view full) ---

79 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\
80 ldr pc, [sp], #4"
81 :
82 : "I" (PAGE_SIZE / 64));
83}
84
85struct cpu_user_fns v4wt_user_fns __initdata = {
86 .cpu_clear_user_page = v4wt_clear_user_page,
76 .cpu_copy_user_page = v4wt_copy_user_page,
87 .cpu_copy_user_highpage = v4wt_copy_user_highpage,
77};
88};