io.c (8843b119ed65cf88560fce6bbbcf027561c3103a) io.c (7632a02f80eb99e942999e522b2eb0f6592ea5b5)
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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40#include "clock44xx.h"
41#include "omap-pm.h"
42#include "sdrc.h"
43#include "control.h"
44#include "serial.h"
45#include "sram.h"
46#include "cm2xxx.h"
47#include "cm3xxx.h"
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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40#include "clock44xx.h"
41#include "omap-pm.h"
42#include "sdrc.h"
43#include "control.h"
44#include "serial.h"
45#include "sram.h"
46#include "cm2xxx.h"
47#include "cm3xxx.h"
48#include "cm33xx.h"
48#include "prm.h"
49#include "cm.h"
50#include "prcm_mpu44xx.h"
51#include "prminst44xx.h"
52#include "cminst44xx.h"
53#include "prm2xxx.h"
54#include "prm3xxx.h"
55#include "prm44xx.h"

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560 omap2_set_globals_tap(AM335X_CLASS,
561 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
562 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
563 NULL);
564 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
565 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
566 omap3xxx_check_revision();
567 am33xx_check_features();
49#include "prm.h"
50#include "cm.h"
51#include "prcm_mpu44xx.h"
52#include "prminst44xx.h"
53#include "cminst44xx.h"
54#include "prm2xxx.h"
55#include "prm3xxx.h"
56#include "prm44xx.h"

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561 omap2_set_globals_tap(AM335X_CLASS,
562 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
563 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
564 NULL);
565 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
566 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
567 omap3xxx_check_revision();
568 am33xx_check_features();
569 am33xx_cm_init();
568 am33xx_powerdomains_init();
569 am33xx_clockdomains_init();
570 am33xx_hwmod_init();
571 omap_hwmod_init_postsetup();
572 omap_clk_soc_init = am33xx_dt_clk_init;
573}
574
575void __init am33xx_init_late(void)

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587 NULL);
588 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
589 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
590 omap_prm_base_init();
591 omap_cm_base_init();
592 omap3xxx_check_revision();
593 am33xx_check_features();
594 omap44xx_prm_init();
570 am33xx_powerdomains_init();
571 am33xx_clockdomains_init();
572 am33xx_hwmod_init();
573 omap_hwmod_init_postsetup();
574 omap_clk_soc_init = am33xx_dt_clk_init;
575}
576
577void __init am33xx_init_late(void)

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589 NULL);
590 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
591 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
592 omap_prm_base_init();
593 omap_cm_base_init();
594 omap3xxx_check_revision();
595 am33xx_check_features();
596 omap44xx_prm_init();
597 omap4_cm_init();
595 am43xx_powerdomains_init();
596 am43xx_clockdomains_init();
597 am43xx_hwmod_init();
598 omap_hwmod_init_postsetup();
599 omap_l2_cache_init();
600 omap_clk_soc_init = am43xx_dt_clk_init;
601}
602

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616 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
617 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
618 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
619 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
620 omap_prm_base_init();
621 omap_cm_base_init();
622 omap4xxx_check_revision();
623 omap4xxx_check_features();
598 am43xx_powerdomains_init();
599 am43xx_clockdomains_init();
600 am43xx_hwmod_init();
601 omap_hwmod_init_postsetup();
602 omap_l2_cache_init();
603 omap_clk_soc_init = am43xx_dt_clk_init;
604}
605

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619 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
620 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
621 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
622 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
623 omap_prm_base_init();
624 omap_cm_base_init();
625 omap4xxx_check_revision();
626 omap4xxx_check_features();
627 omap4_cm_init();
624 omap4_pm_init_early();
625 omap44xx_prm_init();
626 omap44xx_voltagedomains_init();
627 omap44xx_powerdomains_init();
628 omap44xx_clockdomains_init();
629 omap44xx_hwmod_init();
630 omap_hwmod_init_postsetup();
631 omap_l2_cache_init();

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651 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
652 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
653 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
654 omap4_pm_init_early();
655 omap_prm_base_init();
656 omap_cm_base_init();
657 omap44xx_prm_init();
658 omap5xxx_check_revision();
628 omap4_pm_init_early();
629 omap44xx_prm_init();
630 omap44xx_voltagedomains_init();
631 omap44xx_powerdomains_init();
632 omap44xx_clockdomains_init();
633 omap44xx_hwmod_init();
634 omap_hwmod_init_postsetup();
635 omap_l2_cache_init();

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655 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
656 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
657 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
658 omap4_pm_init_early();
659 omap_prm_base_init();
660 omap_cm_base_init();
661 omap44xx_prm_init();
662 omap5xxx_check_revision();
663 omap4_cm_init();
659 omap54xx_voltagedomains_init();
660 omap54xx_powerdomains_init();
661 omap54xx_clockdomains_init();
662 omap54xx_hwmod_init();
663 omap_hwmod_init_postsetup();
664 omap_clk_soc_init = omap5xxx_dt_clk_init;
665}
666

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682 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
683 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
684 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
685 omap4_pm_init_early();
686 omap_prm_base_init();
687 omap_cm_base_init();
688 omap44xx_prm_init();
689 dra7xxx_check_revision();
664 omap54xx_voltagedomains_init();
665 omap54xx_powerdomains_init();
666 omap54xx_clockdomains_init();
667 omap54xx_hwmod_init();
668 omap_hwmod_init_postsetup();
669 omap_clk_soc_init = omap5xxx_dt_clk_init;
670}
671

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687 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
688 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
689 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
690 omap4_pm_init_early();
691 omap_prm_base_init();
692 omap_cm_base_init();
693 omap44xx_prm_init();
694 dra7xxx_check_revision();
695 omap4_cm_init();
690 dra7xx_powerdomains_init();
691 dra7xx_clockdomains_init();
692 dra7xx_hwmod_init();
693 omap_hwmod_init_postsetup();
694 omap_clk_soc_init = dra7xx_dt_clk_init;
695}
696
697void __init dra7xx_init_late(void)

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697 dra7xx_clockdomains_init();
698 dra7xx_hwmod_init();
699 omap_hwmod_init_postsetup();
700 omap_clk_soc_init = dra7xx_dt_clk_init;
701}
702
703void __init dra7xx_init_late(void)

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