1 /* 2 * linux/arch/arm/mach-omap2/io.c 3 * 4 * OMAP2 I/O mapping code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Copyright (C) 2007-2009 Texas Instruments 8 * 9 * Author: 10 * Juha Yrjola <juha.yrjola@nokia.com> 11 * Syed Khasim <x0khasim@ti.com> 12 * 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 25 #include <asm/tlb.h> 26 #include <asm/mach/map.h> 27 28 #include <linux/omap-dma.h> 29 30 #include "omap_hwmod.h" 31 #include "soc.h" 32 #include "iomap.h" 33 #include "voltage.h" 34 #include "powerdomain.h" 35 #include "clockdomain.h" 36 #include "common.h" 37 #include "clock.h" 38 #include "clock2xxx.h" 39 #include "clock3xxx.h" 40 #include "clock44xx.h" 41 #include "omap-pm.h" 42 #include "sdrc.h" 43 #include "control.h" 44 #include "serial.h" 45 #include "sram.h" 46 #include "cm2xxx.h" 47 #include "cm3xxx.h" 48 #include "cm33xx.h" 49 #include "prm.h" 50 #include "cm.h" 51 #include "prcm_mpu44xx.h" 52 #include "prminst44xx.h" 53 #include "cminst44xx.h" 54 #include "prm2xxx.h" 55 #include "prm3xxx.h" 56 #include "prm44xx.h" 57 #include "opp2xxx.h" 58 59 /* 60 * omap_clk_soc_init: points to a function that does the SoC-specific 61 * clock initializations 62 */ 63 static int (*omap_clk_soc_init)(void); 64 65 /* 66 * The machine specific code may provide the extra mapping besides the 67 * default mapping provided here. 68 */ 69 70 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) 71 static struct map_desc omap24xx_io_desc[] __initdata = { 72 { 73 .virtual = L3_24XX_VIRT, 74 .pfn = __phys_to_pfn(L3_24XX_PHYS), 75 .length = L3_24XX_SIZE, 76 .type = MT_DEVICE 77 }, 78 { 79 .virtual = L4_24XX_VIRT, 80 .pfn = __phys_to_pfn(L4_24XX_PHYS), 81 .length = L4_24XX_SIZE, 82 .type = MT_DEVICE 83 }, 84 }; 85 86 #ifdef CONFIG_SOC_OMAP2420 87 static struct map_desc omap242x_io_desc[] __initdata = { 88 { 89 .virtual = DSP_MEM_2420_VIRT, 90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), 91 .length = DSP_MEM_2420_SIZE, 92 .type = MT_DEVICE 93 }, 94 { 95 .virtual = DSP_IPI_2420_VIRT, 96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), 97 .length = DSP_IPI_2420_SIZE, 98 .type = MT_DEVICE 99 }, 100 { 101 .virtual = DSP_MMU_2420_VIRT, 102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), 103 .length = DSP_MMU_2420_SIZE, 104 .type = MT_DEVICE 105 }, 106 }; 107 108 #endif 109 110 #ifdef CONFIG_SOC_OMAP2430 111 static struct map_desc omap243x_io_desc[] __initdata = { 112 { 113 .virtual = L4_WK_243X_VIRT, 114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 115 .length = L4_WK_243X_SIZE, 116 .type = MT_DEVICE 117 }, 118 { 119 .virtual = OMAP243X_GPMC_VIRT, 120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), 121 .length = OMAP243X_GPMC_SIZE, 122 .type = MT_DEVICE 123 }, 124 { 125 .virtual = OMAP243X_SDRC_VIRT, 126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), 127 .length = OMAP243X_SDRC_SIZE, 128 .type = MT_DEVICE 129 }, 130 { 131 .virtual = OMAP243X_SMS_VIRT, 132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), 133 .length = OMAP243X_SMS_SIZE, 134 .type = MT_DEVICE 135 }, 136 }; 137 #endif 138 #endif 139 140 #ifdef CONFIG_ARCH_OMAP3 141 static struct map_desc omap34xx_io_desc[] __initdata = { 142 { 143 .virtual = L3_34XX_VIRT, 144 .pfn = __phys_to_pfn(L3_34XX_PHYS), 145 .length = L3_34XX_SIZE, 146 .type = MT_DEVICE 147 }, 148 { 149 .virtual = L4_34XX_VIRT, 150 .pfn = __phys_to_pfn(L4_34XX_PHYS), 151 .length = L4_34XX_SIZE, 152 .type = MT_DEVICE 153 }, 154 { 155 .virtual = OMAP34XX_GPMC_VIRT, 156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 157 .length = OMAP34XX_GPMC_SIZE, 158 .type = MT_DEVICE 159 }, 160 { 161 .virtual = OMAP343X_SMS_VIRT, 162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), 163 .length = OMAP343X_SMS_SIZE, 164 .type = MT_DEVICE 165 }, 166 { 167 .virtual = OMAP343X_SDRC_VIRT, 168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), 169 .length = OMAP343X_SDRC_SIZE, 170 .type = MT_DEVICE 171 }, 172 { 173 .virtual = L4_PER_34XX_VIRT, 174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), 175 .length = L4_PER_34XX_SIZE, 176 .type = MT_DEVICE 177 }, 178 { 179 .virtual = L4_EMU_34XX_VIRT, 180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), 181 .length = L4_EMU_34XX_SIZE, 182 .type = MT_DEVICE 183 }, 184 }; 185 #endif 186 187 #ifdef CONFIG_SOC_TI81XX 188 static struct map_desc omapti81xx_io_desc[] __initdata = { 189 { 190 .virtual = L4_34XX_VIRT, 191 .pfn = __phys_to_pfn(L4_34XX_PHYS), 192 .length = L4_34XX_SIZE, 193 .type = MT_DEVICE 194 } 195 }; 196 #endif 197 198 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 199 static struct map_desc omapam33xx_io_desc[] __initdata = { 200 { 201 .virtual = L4_34XX_VIRT, 202 .pfn = __phys_to_pfn(L4_34XX_PHYS), 203 .length = L4_34XX_SIZE, 204 .type = MT_DEVICE 205 }, 206 { 207 .virtual = L4_WK_AM33XX_VIRT, 208 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), 209 .length = L4_WK_AM33XX_SIZE, 210 .type = MT_DEVICE 211 } 212 }; 213 #endif 214 215 #ifdef CONFIG_ARCH_OMAP4 216 static struct map_desc omap44xx_io_desc[] __initdata = { 217 { 218 .virtual = L3_44XX_VIRT, 219 .pfn = __phys_to_pfn(L3_44XX_PHYS), 220 .length = L3_44XX_SIZE, 221 .type = MT_DEVICE, 222 }, 223 { 224 .virtual = L4_44XX_VIRT, 225 .pfn = __phys_to_pfn(L4_44XX_PHYS), 226 .length = L4_44XX_SIZE, 227 .type = MT_DEVICE, 228 }, 229 { 230 .virtual = L4_PER_44XX_VIRT, 231 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 232 .length = L4_PER_44XX_SIZE, 233 .type = MT_DEVICE, 234 }, 235 }; 236 #endif 237 238 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 239 static struct map_desc omap54xx_io_desc[] __initdata = { 240 { 241 .virtual = L3_54XX_VIRT, 242 .pfn = __phys_to_pfn(L3_54XX_PHYS), 243 .length = L3_54XX_SIZE, 244 .type = MT_DEVICE, 245 }, 246 { 247 .virtual = L4_54XX_VIRT, 248 .pfn = __phys_to_pfn(L4_54XX_PHYS), 249 .length = L4_54XX_SIZE, 250 .type = MT_DEVICE, 251 }, 252 { 253 .virtual = L4_WK_54XX_VIRT, 254 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), 255 .length = L4_WK_54XX_SIZE, 256 .type = MT_DEVICE, 257 }, 258 { 259 .virtual = L4_PER_54XX_VIRT, 260 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), 261 .length = L4_PER_54XX_SIZE, 262 .type = MT_DEVICE, 263 }, 264 }; 265 #endif 266 267 #ifdef CONFIG_SOC_OMAP2420 268 void __init omap242x_map_io(void) 269 { 270 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 271 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 272 } 273 #endif 274 275 #ifdef CONFIG_SOC_OMAP2430 276 void __init omap243x_map_io(void) 277 { 278 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 279 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 280 } 281 #endif 282 283 #ifdef CONFIG_ARCH_OMAP3 284 void __init omap3_map_io(void) 285 { 286 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 287 } 288 #endif 289 290 #ifdef CONFIG_SOC_TI81XX 291 void __init ti81xx_map_io(void) 292 { 293 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); 294 } 295 #endif 296 297 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 298 void __init am33xx_map_io(void) 299 { 300 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 301 } 302 #endif 303 304 #ifdef CONFIG_ARCH_OMAP4 305 void __init omap4_map_io(void) 306 { 307 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 308 omap_barriers_init(); 309 } 310 #endif 311 312 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 313 void __init omap5_map_io(void) 314 { 315 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 316 omap_barriers_init(); 317 } 318 #endif 319 /* 320 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 321 * 322 * Sets the CORE DPLL3 M2 divider to the same value that it's at 323 * currently. This has the effect of setting the SDRC SDRAM AC timing 324 * registers to the values currently defined by the kernel. Currently 325 * only defined for OMAP3; will return 0 if called on OMAP2. Returns 326 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, 327 * or passes along the return value of clk_set_rate(). 328 */ 329 static int __init _omap2_init_reprogram_sdrc(void) 330 { 331 struct clk *dpll3_m2_ck; 332 int v = -EINVAL; 333 long rate; 334 335 if (!cpu_is_omap34xx()) 336 return 0; 337 338 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); 339 if (IS_ERR(dpll3_m2_ck)) 340 return -EINVAL; 341 342 rate = clk_get_rate(dpll3_m2_ck); 343 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); 344 v = clk_set_rate(dpll3_m2_ck, rate); 345 if (v) 346 pr_err("dpll3_m2_clk rate change failed: %d\n", v); 347 348 clk_put(dpll3_m2_ck); 349 350 return v; 351 } 352 353 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) 354 { 355 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 356 } 357 358 static void __init omap_hwmod_init_postsetup(void) 359 { 360 u8 postsetup_state; 361 362 /* Set the default postsetup state for all hwmods */ 363 #ifdef CONFIG_PM_RUNTIME 364 postsetup_state = _HWMOD_STATE_IDLE; 365 #else 366 postsetup_state = _HWMOD_STATE_ENABLED; 367 #endif 368 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 369 370 omap_pm_if_early_init(); 371 } 372 373 static void __init __maybe_unused omap_common_late_init(void) 374 { 375 omap_mux_late_init(); 376 omap2_common_pm_late_init(); 377 omap_soc_device_init(); 378 } 379 380 #ifdef CONFIG_SOC_OMAP2420 381 void __init omap2420_init_early(void) 382 { 383 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); 384 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), 385 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); 386 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), 387 NULL); 388 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); 389 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); 390 omap2xxx_check_revision(); 391 omap2xxx_prm_init(); 392 omap2xxx_cm_init(); 393 omap2xxx_voltagedomains_init(); 394 omap242x_powerdomains_init(); 395 omap242x_clockdomains_init(); 396 omap2420_hwmod_init(); 397 omap_hwmod_init_postsetup(); 398 omap_clk_soc_init = omap2420_dt_clk_init; 399 rate_table = omap2420_rate_table; 400 } 401 402 void __init omap2420_init_late(void) 403 { 404 omap_common_late_init(); 405 omap2_pm_init(); 406 omap2_clk_enable_autoidle_all(); 407 } 408 #endif 409 410 #ifdef CONFIG_SOC_OMAP2430 411 void __init omap2430_init_early(void) 412 { 413 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); 414 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), 415 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); 416 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), 417 NULL); 418 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); 419 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); 420 omap2xxx_check_revision(); 421 omap2xxx_prm_init(); 422 omap2xxx_cm_init(); 423 omap2xxx_voltagedomains_init(); 424 omap243x_powerdomains_init(); 425 omap243x_clockdomains_init(); 426 omap2430_hwmod_init(); 427 omap_hwmod_init_postsetup(); 428 omap_clk_soc_init = omap2430_dt_clk_init; 429 rate_table = omap2430_rate_table; 430 } 431 432 void __init omap2430_init_late(void) 433 { 434 omap_common_late_init(); 435 omap2_pm_init(); 436 omap2_clk_enable_autoidle_all(); 437 } 438 #endif 439 440 /* 441 * Currently only board-omap3beagle.c should call this because of the 442 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. 443 */ 444 #ifdef CONFIG_ARCH_OMAP3 445 void __init omap3_init_early(void) 446 { 447 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); 448 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), 449 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); 450 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), 451 NULL); 452 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); 453 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); 454 omap3xxx_check_revision(); 455 omap3xxx_check_features(); 456 omap3xxx_prm_init(); 457 omap3xxx_cm_init(); 458 omap3xxx_voltagedomains_init(); 459 omap3xxx_powerdomains_init(); 460 omap3xxx_clockdomains_init(); 461 omap3xxx_hwmod_init(); 462 omap_hwmod_init_postsetup(); 463 omap_clk_soc_init = omap3xxx_clk_init; 464 } 465 466 void __init omap3430_init_early(void) 467 { 468 omap3_init_early(); 469 if (of_have_populated_dt()) 470 omap_clk_soc_init = omap3430_dt_clk_init; 471 } 472 473 void __init omap35xx_init_early(void) 474 { 475 omap3_init_early(); 476 if (of_have_populated_dt()) 477 omap_clk_soc_init = omap3430_dt_clk_init; 478 } 479 480 void __init omap3630_init_early(void) 481 { 482 omap3_init_early(); 483 if (of_have_populated_dt()) 484 omap_clk_soc_init = omap3630_dt_clk_init; 485 } 486 487 void __init am35xx_init_early(void) 488 { 489 omap3_init_early(); 490 if (of_have_populated_dt()) 491 omap_clk_soc_init = am35xx_dt_clk_init; 492 } 493 494 void __init ti81xx_init_early(void) 495 { 496 omap2_set_globals_tap(OMAP343X_CLASS, 497 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 498 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), 499 NULL); 500 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); 501 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); 502 omap3xxx_check_revision(); 503 ti81xx_check_features(); 504 omap3xxx_voltagedomains_init(); 505 omap3xxx_powerdomains_init(); 506 omap3xxx_clockdomains_init(); 507 omap3xxx_hwmod_init(); 508 omap_hwmod_init_postsetup(); 509 if (of_have_populated_dt()) 510 omap_clk_soc_init = ti81xx_dt_clk_init; 511 else 512 omap_clk_soc_init = omap3xxx_clk_init; 513 } 514 515 void __init omap3_init_late(void) 516 { 517 omap_common_late_init(); 518 omap3_pm_init(); 519 omap2_clk_enable_autoidle_all(); 520 } 521 522 void __init omap3430_init_late(void) 523 { 524 omap_common_late_init(); 525 omap3_pm_init(); 526 omap2_clk_enable_autoidle_all(); 527 } 528 529 void __init omap35xx_init_late(void) 530 { 531 omap_common_late_init(); 532 omap3_pm_init(); 533 omap2_clk_enable_autoidle_all(); 534 } 535 536 void __init omap3630_init_late(void) 537 { 538 omap_common_late_init(); 539 omap3_pm_init(); 540 omap2_clk_enable_autoidle_all(); 541 } 542 543 void __init am35xx_init_late(void) 544 { 545 omap_common_late_init(); 546 omap3_pm_init(); 547 omap2_clk_enable_autoidle_all(); 548 } 549 550 void __init ti81xx_init_late(void) 551 { 552 omap_common_late_init(); 553 omap3_pm_init(); 554 omap2_clk_enable_autoidle_all(); 555 } 556 #endif 557 558 #ifdef CONFIG_SOC_AM33XX 559 void __init am33xx_init_early(void) 560 { 561 omap2_set_globals_tap(AM335X_CLASS, 562 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 563 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 564 NULL); 565 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); 566 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); 567 omap3xxx_check_revision(); 568 am33xx_check_features(); 569 am33xx_cm_init(); 570 am33xx_powerdomains_init(); 571 am33xx_clockdomains_init(); 572 am33xx_hwmod_init(); 573 omap_hwmod_init_postsetup(); 574 omap_clk_soc_init = am33xx_dt_clk_init; 575 } 576 577 void __init am33xx_init_late(void) 578 { 579 omap_common_late_init(); 580 } 581 #endif 582 583 #ifdef CONFIG_SOC_AM43XX 584 void __init am43xx_init_early(void) 585 { 586 omap2_set_globals_tap(AM335X_CLASS, 587 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 588 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 589 NULL); 590 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); 591 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); 592 omap_prm_base_init(); 593 omap_cm_base_init(); 594 omap3xxx_check_revision(); 595 am33xx_check_features(); 596 omap44xx_prm_init(); 597 omap4_cm_init(); 598 am43xx_powerdomains_init(); 599 am43xx_clockdomains_init(); 600 am43xx_hwmod_init(); 601 omap_hwmod_init_postsetup(); 602 omap_l2_cache_init(); 603 omap_clk_soc_init = am43xx_dt_clk_init; 604 } 605 606 void __init am43xx_init_late(void) 607 { 608 omap_common_late_init(); 609 } 610 #endif 611 612 #ifdef CONFIG_ARCH_OMAP4 613 void __init omap4430_init_early(void) 614 { 615 omap2_set_globals_tap(OMAP443X_CLASS, 616 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); 617 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), 618 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); 619 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); 620 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), 621 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE)); 622 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); 623 omap_prm_base_init(); 624 omap_cm_base_init(); 625 omap4xxx_check_revision(); 626 omap4xxx_check_features(); 627 omap4_cm_init(); 628 omap4_pm_init_early(); 629 omap44xx_prm_init(); 630 omap44xx_voltagedomains_init(); 631 omap44xx_powerdomains_init(); 632 omap44xx_clockdomains_init(); 633 omap44xx_hwmod_init(); 634 omap_hwmod_init_postsetup(); 635 omap_l2_cache_init(); 636 omap_clk_soc_init = omap4xxx_dt_clk_init; 637 } 638 639 void __init omap4430_init_late(void) 640 { 641 omap_common_late_init(); 642 omap4_pm_init(); 643 omap2_clk_enable_autoidle_all(); 644 } 645 #endif 646 647 #ifdef CONFIG_SOC_OMAP5 648 void __init omap5_init_early(void) 649 { 650 omap2_set_globals_tap(OMAP54XX_CLASS, 651 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); 652 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), 653 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); 654 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); 655 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), 656 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); 657 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 658 omap4_pm_init_early(); 659 omap_prm_base_init(); 660 omap_cm_base_init(); 661 omap44xx_prm_init(); 662 omap5xxx_check_revision(); 663 omap4_cm_init(); 664 omap54xx_voltagedomains_init(); 665 omap54xx_powerdomains_init(); 666 omap54xx_clockdomains_init(); 667 omap54xx_hwmod_init(); 668 omap_hwmod_init_postsetup(); 669 omap_clk_soc_init = omap5xxx_dt_clk_init; 670 } 671 672 void __init omap5_init_late(void) 673 { 674 omap_common_late_init(); 675 omap4_pm_init(); 676 omap2_clk_enable_autoidle_all(); 677 } 678 #endif 679 680 #ifdef CONFIG_SOC_DRA7XX 681 void __init dra7xx_init_early(void) 682 { 683 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); 684 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), 685 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE)); 686 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); 687 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE), 688 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); 689 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 690 omap4_pm_init_early(); 691 omap_prm_base_init(); 692 omap_cm_base_init(); 693 omap44xx_prm_init(); 694 dra7xxx_check_revision(); 695 omap4_cm_init(); 696 dra7xx_powerdomains_init(); 697 dra7xx_clockdomains_init(); 698 dra7xx_hwmod_init(); 699 omap_hwmod_init_postsetup(); 700 omap_clk_soc_init = dra7xx_dt_clk_init; 701 } 702 703 void __init dra7xx_init_late(void) 704 { 705 omap_common_late_init(); 706 omap4_pm_init(); 707 omap2_clk_enable_autoidle_all(); 708 } 709 #endif 710 711 712 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 713 struct omap_sdrc_params *sdrc_cs1) 714 { 715 omap_sram_init(); 716 717 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 718 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 719 _omap2_init_reprogram_sdrc(); 720 } 721 } 722 723 int __init omap_clk_init(void) 724 { 725 int ret = 0; 726 727 if (!omap_clk_soc_init) 728 return 0; 729 730 ti_clk_init_features(); 731 732 ret = of_prcm_init(); 733 if (ret) 734 return ret; 735 736 of_clk_init(NULL); 737 738 ti_dt_clk_init_retry_clks(); 739 740 ti_dt_clockdomains_setup(); 741 742 ret = omap_clk_soc_init(); 743 744 return ret; 745 } 746