control.c (59fb659b065f52fcc2deed293cfbfc58f890376c) control.c (c4d7e58fb52c632d8e33cd23a4917d7a7f8302ac)
1/*
2 * OMAP2/3 System Control Module register access
3 *
4 * Copyright (C) 2007 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *

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247 * called during bootup
248 */
249void omap3_clear_scratchpad_contents(void)
250{
251 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
252 void __iomem *v_addr;
253 u32 offset = 0;
254 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
1/*
2 * OMAP2/3 System Control Module register access
3 *
4 * Copyright (C) 2007 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *

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247 * called during bootup
248 */
249void omap3_clear_scratchpad_contents(void)
250{
251 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
252 void __iomem *v_addr;
253 u32 offset = 0;
254 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
255 if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
255 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
256 OMAP3430_GLOBAL_COLD_RST_MASK) {
257 for ( ; offset <= max_offset; offset += 0x4)
258 __raw_writel(0x0, (v_addr + offset));
256 OMAP3430_GLOBAL_COLD_RST_MASK) {
257 for ( ; offset <= max_offset; offset += 0x4)
258 __raw_writel(0x0, (v_addr + offset));
259 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
260 OMAP3430_GR_MOD,
261 OMAP3_PRM_RSTST_OFFSET);
259 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
260 OMAP3430_GR_MOD,
261 OMAP3_PRM_RSTST_OFFSET);
262 }
263}
264
265/* Populate the scratchpad structure with restore structure */
266void omap3_save_scratchpad_contents(void)
267{
268 void __iomem *scratchpad_address;
269 u32 arm_context_addr;

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295 else
296 scratchpad_contents.secure_ram_restore_ptr =
297 (u32) __pa(omap3_secure_ram_storage);
298 scratchpad_contents.sdrc_module_semaphore = 0x0;
299 scratchpad_contents.prcm_block_offset = 0x2C;
300 scratchpad_contents.sdrc_block_offset = 0x64;
301
302 /* Populate the PRCM block contents */
262 }
263}
264
265/* Populate the scratchpad structure with restore structure */
266void omap3_save_scratchpad_contents(void)
267{
268 void __iomem *scratchpad_address;
269 u32 arm_context_addr;

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295 else
296 scratchpad_contents.secure_ram_restore_ptr =
297 (u32) __pa(omap3_secure_ram_storage);
298 scratchpad_contents.sdrc_module_semaphore = 0x0;
299 scratchpad_contents.prcm_block_offset = 0x2C;
300 scratchpad_contents.sdrc_block_offset = 0x64;
301
302 /* Populate the PRCM block contents */
303 prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
304 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
305 prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
306 OMAP3_PRM_CLKSEL_OFFSET);
303 prcm_block_contents.prm_clksrc_ctrl =
304 omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
305 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
306 prcm_block_contents.prm_clksel =
307 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
308 OMAP3_PRM_CLKSEL_OFFSET);
307 prcm_block_contents.cm_clksel_core =
309 prcm_block_contents.cm_clksel_core =
308 cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
310 omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
309 prcm_block_contents.cm_clksel_wkup =
311 prcm_block_contents.cm_clksel_wkup =
310 cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
312 omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
311 prcm_block_contents.cm_clken_pll =
313 prcm_block_contents.cm_clken_pll =
312 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
314 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
313 prcm_block_contents.cm_autoidle_pll =
315 prcm_block_contents.cm_autoidle_pll =
314 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
316 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
315 prcm_block_contents.cm_clksel1_pll =
317 prcm_block_contents.cm_clksel1_pll =
316 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
318 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
317 prcm_block_contents.cm_clksel2_pll =
319 prcm_block_contents.cm_clksel2_pll =
318 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
320 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
319 prcm_block_contents.cm_clksel3_pll =
321 prcm_block_contents.cm_clksel3_pll =
320 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
322 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
321 prcm_block_contents.cm_clken_pll_mpu =
323 prcm_block_contents.cm_clken_pll_mpu =
322 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
324 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
323 prcm_block_contents.cm_autoidle_pll_mpu =
325 prcm_block_contents.cm_autoidle_pll_mpu =
324 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
326 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
325 prcm_block_contents.cm_clksel1_pll_mpu =
327 prcm_block_contents.cm_clksel1_pll_mpu =
326 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
328 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
327 prcm_block_contents.cm_clksel2_pll_mpu =
329 prcm_block_contents.cm_clksel2_pll_mpu =
328 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
330 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
329 prcm_block_contents.prcm_block_size = 0x0;
330
331 /* Populate the SDRC block contents */
332 sdrc_block_contents.sysconfig =
333 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
334 sdrc_block_contents.cs_cfg =
335 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
336 sdrc_block_contents.sharing =

--- 195 unchanged lines hidden --- 		331 prcm_block_contents.prcm_block_size = 0x0;
332
333 /* Populate the SDRC block contents */
334 sdrc_block_contents.sysconfig =
335 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
336 sdrc_block_contents.cs_cfg =
337 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
338 sdrc_block_contents.sharing =

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