1 /* 2 * OMAP2/3 System Control Module register access 3 * 4 * Copyright (C) 2007 Texas Instruments, Inc. 5 * Copyright (C) 2007 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #undef DEBUG 14 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 18 #include <plat/common.h> 19 #include <plat/sdrc.h> 20 21 #include "cm-regbits-34xx.h" 22 #include "prm-regbits-34xx.h" 23 #include "prm2xxx_3xxx.h" 24 #include "cm2xxx_3xxx.h" 25 #include "sdrc.h" 26 #include "pm.h" 27 #include "control.h" 28 29 static void __iomem *omap2_ctrl_base; 30 static void __iomem *omap4_ctrl_pad_base; 31 32 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 33 struct omap3_scratchpad { 34 u32 boot_config_ptr; 35 u32 public_restore_ptr; 36 u32 secure_ram_restore_ptr; 37 u32 sdrc_module_semaphore; 38 u32 prcm_block_offset; 39 u32 sdrc_block_offset; 40 }; 41 42 struct omap3_scratchpad_prcm_block { 43 u32 prm_clksrc_ctrl; 44 u32 prm_clksel; 45 u32 cm_clksel_core; 46 u32 cm_clksel_wkup; 47 u32 cm_clken_pll; 48 u32 cm_autoidle_pll; 49 u32 cm_clksel1_pll; 50 u32 cm_clksel2_pll; 51 u32 cm_clksel3_pll; 52 u32 cm_clken_pll_mpu; 53 u32 cm_autoidle_pll_mpu; 54 u32 cm_clksel1_pll_mpu; 55 u32 cm_clksel2_pll_mpu; 56 u32 prcm_block_size; 57 }; 58 59 struct omap3_scratchpad_sdrc_block { 60 u16 sysconfig; 61 u16 cs_cfg; 62 u16 sharing; 63 u16 err_type; 64 u32 dll_a_ctrl; 65 u32 dll_b_ctrl; 66 u32 power; 67 u32 cs_0; 68 u32 mcfg_0; 69 u16 mr_0; 70 u16 emr_1_0; 71 u16 emr_2_0; 72 u16 emr_3_0; 73 u32 actim_ctrla_0; 74 u32 actim_ctrlb_0; 75 u32 rfr_ctrl_0; 76 u32 cs_1; 77 u32 mcfg_1; 78 u16 mr_1; 79 u16 emr_1_1; 80 u16 emr_2_1; 81 u16 emr_3_1; 82 u32 actim_ctrla_1; 83 u32 actim_ctrlb_1; 84 u32 rfr_ctrl_1; 85 u16 dcdl_1_ctrl; 86 u16 dcdl_2_ctrl; 87 u32 flags; 88 u32 block_size; 89 }; 90 91 void *omap3_secure_ram_storage; 92 93 /* 94 * This is used to store ARM registers in SDRAM before attempting 95 * an MPU OFF. The save and restore happens from the SRAM sleep code. 96 * The address is stored in scratchpad, so that it can be used 97 * during the restore path. 98 */ 99 u32 omap3_arm_context[128]; 100 101 struct omap3_control_regs { 102 u32 sysconfig; 103 u32 devconf0; 104 u32 mem_dftrw0; 105 u32 mem_dftrw1; 106 u32 msuspendmux_0; 107 u32 msuspendmux_1; 108 u32 msuspendmux_2; 109 u32 msuspendmux_3; 110 u32 msuspendmux_4; 111 u32 msuspendmux_5; 112 u32 sec_ctrl; 113 u32 devconf1; 114 u32 csirxfe; 115 u32 iva2_bootaddr; 116 u32 iva2_bootmod; 117 u32 debobs_0; 118 u32 debobs_1; 119 u32 debobs_2; 120 u32 debobs_3; 121 u32 debobs_4; 122 u32 debobs_5; 123 u32 debobs_6; 124 u32 debobs_7; 125 u32 debobs_8; 126 u32 prog_io0; 127 u32 prog_io1; 128 u32 dss_dpll_spreading; 129 u32 core_dpll_spreading; 130 u32 per_dpll_spreading; 131 u32 usbhost_dpll_spreading; 132 u32 pbias_lite; 133 u32 temp_sensor; 134 u32 sramldo4; 135 u32 sramldo5; 136 u32 csi; 137 u32 padconf_sys_nirq; 138 }; 139 140 static struct omap3_control_regs control_context; 141 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 142 143 #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 144 #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) 145 146 void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 147 { 148 /* Static mapping, never released */ 149 if (omap2_globals->ctrl) { 150 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); 151 WARN_ON(!omap2_ctrl_base); 152 } 153 154 /* Static mapping, never released */ 155 if (omap2_globals->ctrl_pad) { 156 omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K); 157 WARN_ON(!omap4_ctrl_pad_base); 158 } 159 } 160 161 void __iomem *omap_ctrl_base_get(void) 162 { 163 return omap2_ctrl_base; 164 } 165 166 u8 omap_ctrl_readb(u16 offset) 167 { 168 return __raw_readb(OMAP_CTRL_REGADDR(offset)); 169 } 170 171 u16 omap_ctrl_readw(u16 offset) 172 { 173 return __raw_readw(OMAP_CTRL_REGADDR(offset)); 174 } 175 176 u32 omap_ctrl_readl(u16 offset) 177 { 178 return __raw_readl(OMAP_CTRL_REGADDR(offset)); 179 } 180 181 void omap_ctrl_writeb(u8 val, u16 offset) 182 { 183 __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); 184 } 185 186 void omap_ctrl_writew(u16 val, u16 offset) 187 { 188 __raw_writew(val, OMAP_CTRL_REGADDR(offset)); 189 } 190 191 void omap_ctrl_writel(u32 val, u16 offset) 192 { 193 __raw_writel(val, OMAP_CTRL_REGADDR(offset)); 194 } 195 196 /* 197 * On OMAP4 control pad are not addressable from control 198 * core base. So the common omap_ctrl_read/write APIs breaks 199 * Hence export separate APIs to manage the omap4 pad control 200 * registers. This APIs will work only for OMAP4 201 */ 202 203 u32 omap4_ctrl_pad_readl(u16 offset) 204 { 205 return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); 206 } 207 208 void omap4_ctrl_pad_writel(u32 val, u16 offset) 209 { 210 __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); 211 } 212 213 #ifdef CONFIG_ARCH_OMAP3 214 215 /** 216 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot 217 * @bootmode: 8-bit value to pass to some boot code 218 * 219 * Set the bootmode in the scratchpad RAM. This is used after the 220 * system restarts. Not sure what actually uses this - it may be the 221 * bootloader, rather than the boot ROM - contrary to the preserved 222 * comment below. No return value. 223 */ 224 void omap3_ctrl_write_boot_mode(u8 bootmode) 225 { 226 u32 l; 227 228 l = ('B' << 24) | ('M' << 16) | bootmode; 229 230 /* 231 * Reserve the first word in scratchpad for communicating 232 * with the boot ROM. A pointer to a data structure 233 * describing the boot process can be stored there, 234 * cf. OMAP34xx TRM, Initialization / Software Booting 235 * Configuration. 236 * 237 * XXX This should use some omap_ctrl_writel()-type function 238 */ 239 __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); 240 } 241 242 #endif 243 244 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 245 /* 246 * Clears the scratchpad contents in case of cold boot- 247 * called during bootup 248 */ 249 void omap3_clear_scratchpad_contents(void) 250 { 251 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; 252 void __iomem *v_addr; 253 u32 offset = 0; 254 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 255 if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & 256 OMAP3430_GLOBAL_COLD_RST_MASK) { 257 for ( ; offset <= max_offset; offset += 0x4) 258 __raw_writel(0x0, (v_addr + offset)); 259 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, 260 OMAP3430_GR_MOD, 261 OMAP3_PRM_RSTST_OFFSET); 262 } 263 } 264 265 /* Populate the scratchpad structure with restore structure */ 266 void omap3_save_scratchpad_contents(void) 267 { 268 void __iomem *scratchpad_address; 269 u32 arm_context_addr; 270 struct omap3_scratchpad scratchpad_contents; 271 struct omap3_scratchpad_prcm_block prcm_block_contents; 272 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 273 274 /* 275 * Populate the Scratchpad contents 276 * 277 * The "get_*restore_pointer" functions are used to provide a 278 * physical restore address where the ROM code jumps while waking 279 * up from MPU OFF/OSWR state. 280 * The restore pointer is stored into the scratchpad. 281 */ 282 scratchpad_contents.boot_config_ptr = 0x0; 283 if (cpu_is_omap3630()) 284 scratchpad_contents.public_restore_ptr = 285 virt_to_phys(get_omap3630_restore_pointer()); 286 else if (omap_rev() != OMAP3430_REV_ES3_0 && 287 omap_rev() != OMAP3430_REV_ES3_1) 288 scratchpad_contents.public_restore_ptr = 289 virt_to_phys(get_restore_pointer()); 290 else 291 scratchpad_contents.public_restore_ptr = 292 virt_to_phys(get_es3_restore_pointer()); 293 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 294 scratchpad_contents.secure_ram_restore_ptr = 0x0; 295 else 296 scratchpad_contents.secure_ram_restore_ptr = 297 (u32) __pa(omap3_secure_ram_storage); 298 scratchpad_contents.sdrc_module_semaphore = 0x0; 299 scratchpad_contents.prcm_block_offset = 0x2C; 300 scratchpad_contents.sdrc_block_offset = 0x64; 301 302 /* Populate the PRCM block contents */ 303 prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD, 304 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 305 prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD, 306 OMAP3_PRM_CLKSEL_OFFSET); 307 prcm_block_contents.cm_clksel_core = 308 cm_read_mod_reg(CORE_MOD, CM_CLKSEL); 309 prcm_block_contents.cm_clksel_wkup = 310 cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); 311 prcm_block_contents.cm_clken_pll = 312 cm_read_mod_reg(PLL_MOD, CM_CLKEN); 313 prcm_block_contents.cm_autoidle_pll = 314 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); 315 prcm_block_contents.cm_clksel1_pll = 316 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); 317 prcm_block_contents.cm_clksel2_pll = 318 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); 319 prcm_block_contents.cm_clksel3_pll = 320 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); 321 prcm_block_contents.cm_clken_pll_mpu = 322 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); 323 prcm_block_contents.cm_autoidle_pll_mpu = 324 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); 325 prcm_block_contents.cm_clksel1_pll_mpu = 326 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); 327 prcm_block_contents.cm_clksel2_pll_mpu = 328 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); 329 prcm_block_contents.prcm_block_size = 0x0; 330 331 /* Populate the SDRC block contents */ 332 sdrc_block_contents.sysconfig = 333 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 334 sdrc_block_contents.cs_cfg = 335 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 336 sdrc_block_contents.sharing = 337 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 338 sdrc_block_contents.err_type = 339 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 340 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 341 sdrc_block_contents.dll_b_ctrl = 0x0; 342 /* 343 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 344 * be programed to issue automatic self refresh on timeout 345 * of AUTO_CNT = 1 prior to any transition to OFF mode. 346 */ 347 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 348 && (omap_rev() >= OMAP3430_REV_ES3_0)) 349 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 350 ~(SDRC_POWER_AUTOCOUNT_MASK| 351 SDRC_POWER_CLKCTRL_MASK)) | 352 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 353 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 354 else 355 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 356 357 sdrc_block_contents.cs_0 = 0x0; 358 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 359 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 360 sdrc_block_contents.emr_1_0 = 0x0; 361 sdrc_block_contents.emr_2_0 = 0x0; 362 sdrc_block_contents.emr_3_0 = 0x0; 363 sdrc_block_contents.actim_ctrla_0 = 364 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 365 sdrc_block_contents.actim_ctrlb_0 = 366 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 367 sdrc_block_contents.rfr_ctrl_0 = 368 sdrc_read_reg(SDRC_RFR_CTRL_0); 369 sdrc_block_contents.cs_1 = 0x0; 370 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 371 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 372 sdrc_block_contents.emr_1_1 = 0x0; 373 sdrc_block_contents.emr_2_1 = 0x0; 374 sdrc_block_contents.emr_3_1 = 0x0; 375 sdrc_block_contents.actim_ctrla_1 = 376 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 377 sdrc_block_contents.actim_ctrlb_1 = 378 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 379 sdrc_block_contents.rfr_ctrl_1 = 380 sdrc_read_reg(SDRC_RFR_CTRL_1); 381 sdrc_block_contents.dcdl_1_ctrl = 0x0; 382 sdrc_block_contents.dcdl_2_ctrl = 0x0; 383 sdrc_block_contents.flags = 0x0; 384 sdrc_block_contents.block_size = 0x0; 385 386 arm_context_addr = virt_to_phys(omap3_arm_context); 387 388 /* Copy all the contents to the scratchpad location */ 389 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 390 memcpy_toio(scratchpad_address, &scratchpad_contents, 391 sizeof(scratchpad_contents)); 392 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 393 memcpy_toio(scratchpad_address + 394 scratchpad_contents.prcm_block_offset, 395 &prcm_block_contents, sizeof(prcm_block_contents)); 396 memcpy_toio(scratchpad_address + 397 scratchpad_contents.sdrc_block_offset, 398 &sdrc_block_contents, sizeof(sdrc_block_contents)); 399 /* 400 * Copies the address of the location in SDRAM where ARM 401 * registers get saved during a MPU OFF transition. 402 */ 403 memcpy_toio(scratchpad_address + 404 scratchpad_contents.sdrc_block_offset + 405 sizeof(sdrc_block_contents), &arm_context_addr, 4); 406 } 407 408 void omap3_control_save_context(void) 409 { 410 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 411 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 412 control_context.mem_dftrw0 = 413 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 414 control_context.mem_dftrw1 = 415 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 416 control_context.msuspendmux_0 = 417 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 418 control_context.msuspendmux_1 = 419 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 420 control_context.msuspendmux_2 = 421 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 422 control_context.msuspendmux_3 = 423 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 424 control_context.msuspendmux_4 = 425 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 426 control_context.msuspendmux_5 = 427 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 428 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 429 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 430 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 431 control_context.iva2_bootaddr = 432 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 433 control_context.iva2_bootmod = 434 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 435 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 436 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 437 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 438 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 439 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 440 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 441 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 442 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 443 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 444 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 445 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 446 control_context.dss_dpll_spreading = 447 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 448 control_context.core_dpll_spreading = 449 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 450 control_context.per_dpll_spreading = 451 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 452 control_context.usbhost_dpll_spreading = 453 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 454 control_context.pbias_lite = 455 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 456 control_context.temp_sensor = 457 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 458 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 459 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 460 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 461 control_context.padconf_sys_nirq = 462 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); 463 return; 464 } 465 466 void omap3_control_restore_context(void) 467 { 468 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 469 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 470 omap_ctrl_writel(control_context.mem_dftrw0, 471 OMAP343X_CONTROL_MEM_DFTRW0); 472 omap_ctrl_writel(control_context.mem_dftrw1, 473 OMAP343X_CONTROL_MEM_DFTRW1); 474 omap_ctrl_writel(control_context.msuspendmux_0, 475 OMAP2_CONTROL_MSUSPENDMUX_0); 476 omap_ctrl_writel(control_context.msuspendmux_1, 477 OMAP2_CONTROL_MSUSPENDMUX_1); 478 omap_ctrl_writel(control_context.msuspendmux_2, 479 OMAP2_CONTROL_MSUSPENDMUX_2); 480 omap_ctrl_writel(control_context.msuspendmux_3, 481 OMAP2_CONTROL_MSUSPENDMUX_3); 482 omap_ctrl_writel(control_context.msuspendmux_4, 483 OMAP2_CONTROL_MSUSPENDMUX_4); 484 omap_ctrl_writel(control_context.msuspendmux_5, 485 OMAP2_CONTROL_MSUSPENDMUX_5); 486 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 487 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 488 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 489 omap_ctrl_writel(control_context.iva2_bootaddr, 490 OMAP343X_CONTROL_IVA2_BOOTADDR); 491 omap_ctrl_writel(control_context.iva2_bootmod, 492 OMAP343X_CONTROL_IVA2_BOOTMOD); 493 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 494 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 495 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 496 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 497 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 498 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 499 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 500 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 501 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 502 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 503 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 504 omap_ctrl_writel(control_context.dss_dpll_spreading, 505 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 506 omap_ctrl_writel(control_context.core_dpll_spreading, 507 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 508 omap_ctrl_writel(control_context.per_dpll_spreading, 509 OMAP343X_CONTROL_PER_DPLL_SPREADING); 510 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 511 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 512 omap_ctrl_writel(control_context.pbias_lite, 513 OMAP343X_CONTROL_PBIAS_LITE); 514 omap_ctrl_writel(control_context.temp_sensor, 515 OMAP343X_CONTROL_TEMP_SENSOR); 516 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 517 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 518 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 519 omap_ctrl_writel(control_context.padconf_sys_nirq, 520 OMAP343X_CONTROL_PADCONF_SYSNIRQ); 521 return; 522 } 523 524 void omap3630_ctrl_disable_rta(void) 525 { 526 if (!cpu_is_omap3630()) 527 return; 528 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); 529 } 530 531 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 532