common.c (81d2ef7c40eceb7189872ecea5964f2041118d4a) common.c (c3c5a2815d0b7ebde157556685a0ef8ffa34b98c)
1/*
2 * arch/arm/mach-dove/common.c
3 *
4 * Core functions for Marvell Dove 88AP510 System On Chip
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/pci.h>
16#include <linux/clk-provider.h>
17#include <linux/ata_platform.h>
18#include <linux/gpio.h>
1/*
2 * arch/arm/mach-dove/common.c
3 *
4 * Core functions for Marvell Dove 88AP510 System On Chip
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/pci.h>
16#include <linux/clk-provider.h>
17#include <linux/ata_platform.h>
18#include <linux/gpio.h>
19#include <linux/of.h>
20#include <linux/of_platform.h>
21#include <asm/page.h>
22#include <asm/setup.h>
23#include <asm/timex.h>
24#include <asm/hardware/cache-tauros2.h>
25#include <asm/mach/map.h>
26#include <asm/mach/time.h>
27#include <asm/mach/pci.h>
28#include <mach/dove.h>
19#include <asm/page.h>
20#include <asm/setup.h>
21#include <asm/timex.h>
22#include <asm/hardware/cache-tauros2.h>
23#include <asm/mach/map.h>
24#include <asm/mach/time.h>
25#include <asm/mach/pci.h>
26#include <mach/dove.h>
29#include <mach/pm.h>
30#include <mach/bridge-regs.h>
31#include <asm/mach/arch.h>
32#include <linux/irq.h>
33#include <plat/time.h>
27#include <mach/bridge-regs.h>
28#include <asm/mach/arch.h>
29#include <linux/irq.h>
30#include <plat/time.h>
34#include <plat/irq.h>
35#include <plat/ehci-orion.h>
36#include <plat/common.h>
37#include <plat/addr-map.h>
38#include "common.h"
39
31#include <plat/ehci-orion.h>
32#include <plat/common.h>
33#include <plat/addr-map.h>
34#include "common.h"
35
36static int get_tclk(void);
37
40/*****************************************************************************
41 * I/O Address Mapping
42 ****************************************************************************/
43static struct map_desc dove_io_desc[] __initdata = {
44 {
38/*****************************************************************************
39 * I/O Address Mapping
40 ****************************************************************************/
41static struct map_desc dove_io_desc[] __initdata = {
42 {
45 .virtual = DOVE_SB_REGS_VIRT_BASE,
43 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
46 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
47 .length = DOVE_SB_REGS_SIZE,
48 .type = MT_DEVICE,
49 }, {
44 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
45 .length = DOVE_SB_REGS_SIZE,
46 .type = MT_DEVICE,
47 }, {
50 .virtual = DOVE_NB_REGS_VIRT_BASE,
48 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
51 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
52 .length = DOVE_NB_REGS_SIZE,
53 .type = MT_DEVICE,
54 }, {
49 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
50 .length = DOVE_NB_REGS_SIZE,
51 .type = MT_DEVICE,
52 }, {
55 .virtual = DOVE_PCIE0_IO_VIRT_BASE,
53 .virtual = (unsigned long) DOVE_PCIE0_IO_VIRT_BASE,
56 .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
57 .length = DOVE_PCIE0_IO_SIZE,
58 .type = MT_DEVICE,
59 }, {
54 .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
55 .length = DOVE_PCIE0_IO_SIZE,
56 .type = MT_DEVICE,
57 }, {
60 .virtual = DOVE_PCIE1_IO_VIRT_BASE,
58 .virtual = (unsigned long) DOVE_PCIE1_IO_VIRT_BASE,
61 .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
62 .length = DOVE_PCIE1_IO_SIZE,
63 .type = MT_DEVICE,
64 },
65};
66
67void __init dove_map_io(void)
68{
69 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
70}
71
72/*****************************************************************************
73 * CLK tree
74 ****************************************************************************/
59 .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
60 .length = DOVE_PCIE1_IO_SIZE,
61 .type = MT_DEVICE,
62 },
63};
64
65void __init dove_map_io(void)
66{
67 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
68}
69
70/*****************************************************************************
71 * CLK tree
72 ****************************************************************************/
75static int dove_tclk;
76
77static DEFINE_SPINLOCK(gating_lock);
78static struct clk *tclk;
79
73static struct clk *tclk;
74
80static struct clk __init *dove_register_gate(const char *name,
81 const char *parent, u8 bit_idx)
75static void __init clk_init(void)
82{
76{
83 return clk_register_gate(NULL, name, parent, 0,
84 (void __iomem *)CLOCK_GATING_CONTROL,
85 bit_idx, 0, &gating_lock);
86}
87
88static void __init dove_clk_init(void)
89{
90 struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
91 struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
92 struct clk *xor0, *xor1, *ge, *gephy;
93
94 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
77 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
95 dove_tclk);
78 get_tclk());
96
79
97 usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
98 usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
99 sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
100 pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
101 pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
102 sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
103 sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
104 nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
105 camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
106 i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
107 i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
108 crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
109 ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
110 pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
111 xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
112 xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
113 gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
114 ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
115
116 orion_clkdev_add(NULL, "orion_spi.0", tclk);
117 orion_clkdev_add(NULL, "orion_spi.1", tclk);
118 orion_clkdev_add(NULL, "orion_wdt", tclk);
119 orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
120
121 orion_clkdev_add(NULL, "orion-ehci.0", usb0);
122 orion_clkdev_add(NULL, "orion-ehci.1", usb1);
123 orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
124 orion_clkdev_add("0", "sata_mv.0", sata);
125 orion_clkdev_add("0", "pcie", pex0);
126 orion_clkdev_add("1", "pcie", pex1);
127 orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
128 orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
129 orion_clkdev_add(NULL, "orion_nand", nand);
130 orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
131 orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
132 orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
133 orion_clkdev_add(NULL, "mv_crypto", crypto);
134 orion_clkdev_add(NULL, "dove-ac97", ac97);
135 orion_clkdev_add(NULL, "dove-pdma", pdma);
136 orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
137 orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
80 orion_clkdev_init(tclk);
138}
139
140/*****************************************************************************
141 * EHCI0
142 ****************************************************************************/
143void __init dove_ehci0_init(void)
144{
145 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);

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180
181}
182
183/*****************************************************************************
184 * UART0
185 ****************************************************************************/
186void __init dove_uart0_init(void)
187{
81}
82
83/*****************************************************************************
84 * EHCI0
85 ****************************************************************************/
86void __init dove_ehci0_init(void)
87{
88 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);

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123
124}
125
126/*****************************************************************************
127 * UART0
128 ****************************************************************************/
129void __init dove_uart0_init(void)
130{
188 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
131 orion_uart0_init((unsigned long) DOVE_UART0_VIRT_BASE,
132 DOVE_UART0_PHYS_BASE,
189 IRQ_DOVE_UART_0, tclk);
190}
191
192/*****************************************************************************
193 * UART1
194 ****************************************************************************/
195void __init dove_uart1_init(void)
196{
133 IRQ_DOVE_UART_0, tclk);
134}
135
136/*****************************************************************************
137 * UART1
138 ****************************************************************************/
139void __init dove_uart1_init(void)
140{
197 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
141 orion_uart1_init((unsigned long) DOVE_UART1_VIRT_BASE,
142 DOVE_UART1_PHYS_BASE,
198 IRQ_DOVE_UART_1, tclk);
199}
200
201/*****************************************************************************
202 * UART2
203 ****************************************************************************/
204void __init dove_uart2_init(void)
205{
143 IRQ_DOVE_UART_1, tclk);
144}
145
146/*****************************************************************************
147 * UART2
148 ****************************************************************************/
149void __init dove_uart2_init(void)
150{
206 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
151 orion_uart2_init((unsigned long) DOVE_UART2_VIRT_BASE,
152 DOVE_UART2_PHYS_BASE,
207 IRQ_DOVE_UART_2, tclk);
208}
209
210/*****************************************************************************
211 * UART3
212 ****************************************************************************/
213void __init dove_uart3_init(void)
214{
153 IRQ_DOVE_UART_2, tclk);
154}
155
156/*****************************************************************************
157 * UART3
158 ****************************************************************************/
159void __init dove_uart3_init(void)
160{
215 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
161 orion_uart3_init((unsigned long) DOVE_UART3_VIRT_BASE,
162 DOVE_UART3_PHYS_BASE,
216 IRQ_DOVE_UART_3, tclk);
217}
218
219/*****************************************************************************
220 * SPI
221 ****************************************************************************/
222void __init dove_spi0_init(void)
223{

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237 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
238}
239
240/*****************************************************************************
241 * Time handling
242 ****************************************************************************/
243void __init dove_init_early(void)
244{
163 IRQ_DOVE_UART_3, tclk);
164}
165
166/*****************************************************************************
167 * SPI
168 ****************************************************************************/
169void __init dove_spi0_init(void)
170{

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184 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
185}
186
187/*****************************************************************************
188 * Time handling
189 ****************************************************************************/
190void __init dove_init_early(void)
191{
245 orion_time_set_base(TIMER_VIRT_BASE);
192 orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
246}
247
193}
194
248static int __init dove_find_tclk(void)
195static int get_tclk(void)
249{
196{
197 /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
250 return 166666667;
251}
252
253static void __init dove_timer_init(void)
254{
198 return 166666667;
199}
200
201static void __init dove_timer_init(void)
202{
255 dove_tclk = dove_find_tclk();
256 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
257 IRQ_DOVE_BRIDGE, dove_tclk);
203 orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
204 BRIDGE_INT_TIMER1_CLR,
205 IRQ_DOVE_BRIDGE, get_tclk());
258}
259
260struct sys_timer dove_timer = {
261 .init = dove_timer_init,
262};
263
264/*****************************************************************************
206}
207
208struct sys_timer dove_timer = {
209 .init = dove_timer_init,
210};
211
212/*****************************************************************************
265 * Cryptographic Engines and Security Accelerator (CESA)
266 ****************************************************************************/
267void __init dove_crypto_init(void)
268{
269 orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
270 DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
271}
272
273/*****************************************************************************
274 * XOR 0
275 ****************************************************************************/
276void __init dove_xor0_init(void)
277{
278 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
279 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
280}
281

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346
347void __init dove_sdio1_init(void)
348{
349 platform_device_register(&dove_sdio1);
350}
351
352void __init dove_init(void)
353{
213 * XOR 0
214 ****************************************************************************/
215void __init dove_xor0_init(void)
216{
217 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
218 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
219}
220

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285
286void __init dove_sdio1_init(void)
287{
288 platform_device_register(&dove_sdio1);
289}
290
291void __init dove_init(void)
292{
354 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
355 (dove_tclk + 499999) / 1000000);
293 printk(KERN_INFO "Dove 88AP510 SoC, ");
294 printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
356
357#ifdef CONFIG_CACHE_TAUROS2
358 tauros2_init();
359#endif
360 dove_setup_cpu_mbus();
361
362 /* Setup root of clk tree */
295
296#ifdef CONFIG_CACHE_TAUROS2
297 tauros2_init();
298#endif
299 dove_setup_cpu_mbus();
300
301 /* Setup root of clk tree */
363 dove_clk_init();
302 clk_init();
364
365 /* internal devices that every board has */
366 dove_rtc_init();
367 dove_xor0_init();
368 dove_xor1_init();
369}
370
371void dove_restart(char mode, const char *cmd)

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378 /*
379 * Assert soft reset.
380 */
381 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
382
383 while (1)
384 ;
385}
303
304 /* internal devices that every board has */
305 dove_rtc_init();
306 dove_xor0_init();
307 dove_xor1_init();
308}
309
310void dove_restart(char mode, const char *cmd)

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317 /*
318 * Assert soft reset.
319 */
320 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
321
322 while (1)
323 ;
324}
386
387#if defined(CONFIG_MACH_DOVE_DT)
388/*
389 * Auxdata required until real OF clock provider
390 */
391struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
392 OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
393 OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
394 OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
395 OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
396 NULL),
397 OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
398 OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
399 OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
400 {},
401};
402
403static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
404 .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
405};
406
407static void __init dove_dt_init(void)
408{
409 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
410 (dove_tclk + 499999) / 1000000);
411
412#ifdef CONFIG_CACHE_TAUROS2
413 tauros2_init();
414#endif
415 dove_setup_cpu_mbus();
416
417 /* Setup root of clk tree */
418 dove_clk_init();
419
420 /* Internal devices not ported to DT yet */
421 dove_rtc_init();
422 dove_xor0_init();
423 dove_xor1_init();
424
425 dove_ge00_init(&dove_dt_ge00_data);
426 dove_ehci0_init();
427 dove_ehci1_init();
428 dove_pcie_init(1, 1);
429 dove_crypto_init();
430
431 of_platform_populate(NULL, of_default_bus_match_table,
432 dove_auxdata_lookup, NULL);
433}
434
435static const char * const dove_dt_board_compat[] = {
436 "marvell,dove",
437 NULL
438};
439
440DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
441 .map_io = dove_map_io,
442 .init_early = dove_init_early,
443 .init_irq = orion_dt_init_irq,
444 .timer = &dove_timer,
445 .init_machine = dove_dt_init,
446 .restart = dove_restart,
447 .dt_compat = dove_dt_board_compat,
448MACHINE_END
449#endif