1 /* 2 * arch/arm/mach-dove/common.c 3 * 4 * Core functions for Marvell Dove 88AP510 System On Chip 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/platform_device.h> 15 #include <linux/pci.h> 16 #include <linux/clk-provider.h> 17 #include <linux/ata_platform.h> 18 #include <linux/gpio.h> 19 #include <asm/page.h> 20 #include <asm/setup.h> 21 #include <asm/timex.h> 22 #include <asm/hardware/cache-tauros2.h> 23 #include <asm/mach/map.h> 24 #include <asm/mach/time.h> 25 #include <asm/mach/pci.h> 26 #include <mach/dove.h> 27 #include <mach/bridge-regs.h> 28 #include <asm/mach/arch.h> 29 #include <linux/irq.h> 30 #include <plat/time.h> 31 #include <plat/ehci-orion.h> 32 #include <plat/common.h> 33 #include <plat/addr-map.h> 34 #include "common.h" 35 36 static int get_tclk(void); 37 38 /***************************************************************************** 39 * I/O Address Mapping 40 ****************************************************************************/ 41 static struct map_desc dove_io_desc[] __initdata = { 42 { 43 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, 44 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), 45 .length = DOVE_SB_REGS_SIZE, 46 .type = MT_DEVICE, 47 }, { 48 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, 49 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), 50 .length = DOVE_NB_REGS_SIZE, 51 .type = MT_DEVICE, 52 }, { 53 .virtual = (unsigned long) DOVE_PCIE0_IO_VIRT_BASE, 54 .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), 55 .length = DOVE_PCIE0_IO_SIZE, 56 .type = MT_DEVICE, 57 }, { 58 .virtual = (unsigned long) DOVE_PCIE1_IO_VIRT_BASE, 59 .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), 60 .length = DOVE_PCIE1_IO_SIZE, 61 .type = MT_DEVICE, 62 }, 63 }; 64 65 void __init dove_map_io(void) 66 { 67 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); 68 } 69 70 /***************************************************************************** 71 * CLK tree 72 ****************************************************************************/ 73 static struct clk *tclk; 74 75 static void __init clk_init(void) 76 { 77 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, 78 get_tclk()); 79 80 orion_clkdev_init(tclk); 81 } 82 83 /***************************************************************************** 84 * EHCI0 85 ****************************************************************************/ 86 void __init dove_ehci0_init(void) 87 { 88 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); 89 } 90 91 /***************************************************************************** 92 * EHCI1 93 ****************************************************************************/ 94 void __init dove_ehci1_init(void) 95 { 96 orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); 97 } 98 99 /***************************************************************************** 100 * GE00 101 ****************************************************************************/ 102 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 103 { 104 orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, 105 IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, 106 1600); 107 } 108 109 /***************************************************************************** 110 * SoC RTC 111 ****************************************************************************/ 112 void __init dove_rtc_init(void) 113 { 114 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); 115 } 116 117 /***************************************************************************** 118 * SATA 119 ****************************************************************************/ 120 void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 121 { 122 orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); 123 124 } 125 126 /***************************************************************************** 127 * UART0 128 ****************************************************************************/ 129 void __init dove_uart0_init(void) 130 { 131 orion_uart0_init((unsigned long) DOVE_UART0_VIRT_BASE, 132 DOVE_UART0_PHYS_BASE, 133 IRQ_DOVE_UART_0, tclk); 134 } 135 136 /***************************************************************************** 137 * UART1 138 ****************************************************************************/ 139 void __init dove_uart1_init(void) 140 { 141 orion_uart1_init((unsigned long) DOVE_UART1_VIRT_BASE, 142 DOVE_UART1_PHYS_BASE, 143 IRQ_DOVE_UART_1, tclk); 144 } 145 146 /***************************************************************************** 147 * UART2 148 ****************************************************************************/ 149 void __init dove_uart2_init(void) 150 { 151 orion_uart2_init((unsigned long) DOVE_UART2_VIRT_BASE, 152 DOVE_UART2_PHYS_BASE, 153 IRQ_DOVE_UART_2, tclk); 154 } 155 156 /***************************************************************************** 157 * UART3 158 ****************************************************************************/ 159 void __init dove_uart3_init(void) 160 { 161 orion_uart3_init((unsigned long) DOVE_UART3_VIRT_BASE, 162 DOVE_UART3_PHYS_BASE, 163 IRQ_DOVE_UART_3, tclk); 164 } 165 166 /***************************************************************************** 167 * SPI 168 ****************************************************************************/ 169 void __init dove_spi0_init(void) 170 { 171 orion_spi_init(DOVE_SPI0_PHYS_BASE); 172 } 173 174 void __init dove_spi1_init(void) 175 { 176 orion_spi_1_init(DOVE_SPI1_PHYS_BASE); 177 } 178 179 /***************************************************************************** 180 * I2C 181 ****************************************************************************/ 182 void __init dove_i2c_init(void) 183 { 184 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); 185 } 186 187 /***************************************************************************** 188 * Time handling 189 ****************************************************************************/ 190 void __init dove_init_early(void) 191 { 192 orion_time_set_base((unsigned long) TIMER_VIRT_BASE); 193 } 194 195 static int get_tclk(void) 196 { 197 /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */ 198 return 166666667; 199 } 200 201 static void __init dove_timer_init(void) 202 { 203 orion_time_init((unsigned long) BRIDGE_VIRT_BASE, 204 BRIDGE_INT_TIMER1_CLR, 205 IRQ_DOVE_BRIDGE, get_tclk()); 206 } 207 208 struct sys_timer dove_timer = { 209 .init = dove_timer_init, 210 }; 211 212 /***************************************************************************** 213 * XOR 0 214 ****************************************************************************/ 215 void __init dove_xor0_init(void) 216 { 217 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, 218 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); 219 } 220 221 /***************************************************************************** 222 * XOR 1 223 ****************************************************************************/ 224 void __init dove_xor1_init(void) 225 { 226 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, 227 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); 228 } 229 230 /***************************************************************************** 231 * SDIO 232 ****************************************************************************/ 233 static u64 sdio_dmamask = DMA_BIT_MASK(32); 234 235 static struct resource dove_sdio0_resources[] = { 236 { 237 .start = DOVE_SDIO0_PHYS_BASE, 238 .end = DOVE_SDIO0_PHYS_BASE + 0xff, 239 .flags = IORESOURCE_MEM, 240 }, { 241 .start = IRQ_DOVE_SDIO0, 242 .end = IRQ_DOVE_SDIO0, 243 .flags = IORESOURCE_IRQ, 244 }, 245 }; 246 247 static struct platform_device dove_sdio0 = { 248 .name = "sdhci-dove", 249 .id = 0, 250 .dev = { 251 .dma_mask = &sdio_dmamask, 252 .coherent_dma_mask = DMA_BIT_MASK(32), 253 }, 254 .resource = dove_sdio0_resources, 255 .num_resources = ARRAY_SIZE(dove_sdio0_resources), 256 }; 257 258 void __init dove_sdio0_init(void) 259 { 260 platform_device_register(&dove_sdio0); 261 } 262 263 static struct resource dove_sdio1_resources[] = { 264 { 265 .start = DOVE_SDIO1_PHYS_BASE, 266 .end = DOVE_SDIO1_PHYS_BASE + 0xff, 267 .flags = IORESOURCE_MEM, 268 }, { 269 .start = IRQ_DOVE_SDIO1, 270 .end = IRQ_DOVE_SDIO1, 271 .flags = IORESOURCE_IRQ, 272 }, 273 }; 274 275 static struct platform_device dove_sdio1 = { 276 .name = "sdhci-dove", 277 .id = 1, 278 .dev = { 279 .dma_mask = &sdio_dmamask, 280 .coherent_dma_mask = DMA_BIT_MASK(32), 281 }, 282 .resource = dove_sdio1_resources, 283 .num_resources = ARRAY_SIZE(dove_sdio1_resources), 284 }; 285 286 void __init dove_sdio1_init(void) 287 { 288 platform_device_register(&dove_sdio1); 289 } 290 291 void __init dove_init(void) 292 { 293 printk(KERN_INFO "Dove 88AP510 SoC, "); 294 printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); 295 296 #ifdef CONFIG_CACHE_TAUROS2 297 tauros2_init(); 298 #endif 299 dove_setup_cpu_mbus(); 300 301 /* Setup root of clk tree */ 302 clk_init(); 303 304 /* internal devices that every board has */ 305 dove_rtc_init(); 306 dove_xor0_init(); 307 dove_xor1_init(); 308 } 309 310 void dove_restart(char mode, const char *cmd) 311 { 312 /* 313 * Enable soft reset to assert RSTOUTn. 314 */ 315 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); 316 317 /* 318 * Assert soft reset. 319 */ 320 writel(SOFT_RESET, SYSTEM_SOFT_RESET); 321 322 while (1) 323 ; 324 } 325