| /openbmc/u-boot/arch/arm/mach-rockchip/ |
| H A D | rk3368-board-tpl.c | 54 rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); in sgrf_init()
55 rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); in sgrf_init()
56 rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); in sgrf_init()
67 rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); in sgrf_init()
68 rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); in sgrf_init()
72 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); in sgrf_init()
73 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); in sgrf_init()
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| H A D | rk3399-board-spl.c | 151 rk_setreg(&grf->io_vsel, 1 << 0); in board_debug_uart_init()
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| H A D | rk3288-board.c | 350 rk_setreg(GRF_SOC_CON2, 1 << 0); in board_early_init_f()
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| /openbmc/u-boot/arch/arm/mach-rockchip/rk3288/ |
| H A D | rk3288.c | 15 rk_setreg(GRF_SOC_CON2, 1 << 0); in arch_cpu_init()
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | hardware.h | 18 #define rk_setreg(addr, set) writel((set) << 16 | (set), addr) macro
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| /openbmc/u-boot/drivers/video/rockchip/ |
| H A D | rk_lvds.c | 70 rk_setreg(&priv->grf->soc_con6, val); in rk_lvds_enable()
81 rk_setreg(&priv->grf->soc_con7, val); in rk_lvds_enable()
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| H A D | rk3288_vop.c | 40 rk_setreg(&grf->io_vsel, 1 << 0); in rk3288_set_io_vsel()
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| H A D | rk3288_hdmi.c | 31 rk_setreg(&grf->soc_con6, 1 << 15); in rk3288_hdmi_enable()
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| H A D | rk_edp.c | 1058 rk_setreg(&priv->grf->soc_con12, 1 << 4); in rk_edp_probe()
1061 rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5)); in rk_edp_probe()
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3128.c | 55 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
57 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
380 rk_setreg(&cru->cru_clksel_con[10], in rk3128_peri_set_pclk()
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| H A D | clk_rk3288.c | 160 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
829 rk_setreg(&cru->cru_clksel_con[28], 1 << 15); in rk3288_clk_set_rate()
832 rk_setreg(&cru->cru_clksel_con[6], 1 << 15); in rk3288_clk_set_rate()
865 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); in rk3288_clk_set_rate()
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| H A D | clk_rk322x.c | 58 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
60 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
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| H A D | clk_rk3328.c | 684 rk_setreg(&grf->mac_con[1], BIT(10)); in rk3328_gmac2io_set_parent()
721 rk_setreg(&grf->soc_con[4], BIT(14)); in rk3328_gmac2io_ext_set_parent()
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| H A D | clk_rv1108.c | 89 rk_setreg(&pll->con3, 1 << DSMPD_SHIFT); in rkclk_set_pll()
91 rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT); in rkclk_set_pll()
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| H A D | clk_rk3036.c | 62 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
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| H A D | clk_rk3188.c | 101 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
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| H A D | clk_rk3368.c | 551 rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK); in rk3368_gmac_set_parent()
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| H A D | clk_rk3399.c | 1043 rk_setreg(&priv->cru->clksel_con[19], BIT(4)); in rk3399_gmac_set_parent()
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| /openbmc/u-boot/drivers/reset/ |
| H A D | reset-rockchip.c | 57 rk_setreg(priv->base + (bank * 4), BIT(offset)); in rockchip_reset_assert()
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| /openbmc/u-boot/board/theobroma-systems/puma_rk3399/ |
| H A D | puma-rk3399.c | 196 rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT); in setup_iodomain()
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| /openbmc/u-boot/drivers/ram/rockchip/ |
| H A D | dmc-rk3368.c | 141 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
149 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
342 rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset); in ddrctl_reset()
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| H A D | sdram_rk3288.c | 443 rk_setreg(&grf->soc_con0, 1 << (8 + channel)); in set_bandwidth_ratio()
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| /openbmc/u-boot/arch/arm/mach-rockchip/rk3036/ |
| H A D | sdram_rk3036.c | 336 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkdclk_init()
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