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Searched refs:regUVD_VCPU_CACHE_OFFSET0 (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c349 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v4_0_3_mc_resume()
358 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, in vcn_v4_0_3_mc_resume()
425 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
432 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
444 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), in vcn_v4_0_3_mc_resume_dpg_mode()
910 regUVD_VCPU_CACHE_OFFSET0), 0); in vcn_v4_0_3_start_sriov()
920 regUVD_VCPU_CACHE_OFFSET0), in vcn_v4_0_3_start_sriov()
H A Dvcn_v4_0.c389 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v4_0_mc_resume()
397 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_mc_resume()
453 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
460 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
472 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), in vcn_v4_0_mc_resume_dpg_mode()
1279 regUVD_VCPU_CACHE_OFFSET0), in vcn_v4_0_start_sriov()
1290 regUVD_VCPU_CACHE_OFFSET0), in vcn_v4_0_start_sriov()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h30 #define regUVD_VCPU_CACHE_OFFSET0 … macro
H A Dvcn_4_0_0_offset.h378 #define regUVD_VCPU_CACHE_OFFSET0 … macro
H A Dvcn_4_0_3_offset.h380 #define regUVD_VCPU_CACHE_OFFSET0 … macro