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Searched refs:mtvec (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/tests/tcg/riscv64/
H A Dtest-mepc-masking.S16 csrw mtvec, t0
H A Dissue1060.S7 csrw mtvec, t0
/openbmc/qemu/target/riscv/
H A Dmachine.c468 VMSTATE_UINTTL(env.mtvec, RISCVCPU),
H A Dcpu.h325 target_ulong mtvec;
324 target_ulong mtvec; global() member
H A Dcpu_helper.c2453 env->pc = (env->mtvec >> 2 << 2) + in riscv_cpu_do_interrupt()
2454 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); in riscv_cpu_do_interrupt()
H A Dcsr.c2980 *val = env->mtvec; in read_mtvec()
2989 env->mtvec = val; in write_mtvec()
5871 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },