Searched refs:mtvec (Results 1 – 5 of 5) sorted by relevance
7 csrw mtvec, t0
393 VMSTATE_UINTTL(env.mtvec, RISCVCPU),
286 target_ulong mtvec; member
1835 env->pc = (env->mtvec >> 2 << 2) + in riscv_cpu_do_interrupt()1836 ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0); in riscv_cpu_do_interrupt()
2149 *val = env->mtvec; in read_mtvec()2158 env->mtvec = val; in write_mtvec()