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Searched refs:mmUVD_MPC_SET_MUXB1 (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h57 #define mmUVD_MPC_SET_MUXB1 0x3d7c macro
H A Duvd_4_0_d.h59 #define mmUVD_MPC_SET_MUXB1 0x3D7C macro
H A Duvd_3_1_d.h59 #define mmUVD_MPC_SET_MUXB1 0x3d7c macro
H A Duvd_5_0_d.h63 #define mmUVD_MPC_SET_MUXB1 0x3d7c macro
H A Duvd_6_0_d.h79 #define mmUVD_MPC_SET_MUXB1 0x3d7c macro
H A Duvd_7_0_offset.h172 #define mmUVD_MPC_SET_MUXB1 … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h352 #define mmUVD_MPC_SET_MUXB1 … macro
H A Dvcn_2_5_offset.h767 #define mmUVD_MPC_SET_MUXB1 … macro
H A Dvcn_2_0_0_offset.h602 #define mmUVD_MPC_SET_MUXB1 … macro
H A Dvcn_3_0_0_offset.h1147 #define mmUVD_MPC_SET_MUXB1 … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c320 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); in uvd_v4_2_start()
H A Duvd_v3_1.c364 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); in uvd_v3_1_start()
H A Duvd_v5_0.c366 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); in uvd_v5_0_start()
H A Duvd_v6_0.c780 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); in uvd_v6_0_start()
H A Duvd_v7_0.c1022 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); in uvd_v7_0_start()