1c54a60dbSLeo Liu /* 2c54a60dbSLeo Liu * Copyright (C) 2019 Advanced Micro Devices, Inc. 3c54a60dbSLeo Liu * 4c54a60dbSLeo Liu * Permission is hereby granted, free of charge, to any person obtaining a 5c54a60dbSLeo Liu * copy of this software and associated documentation files (the "Software"), 6c54a60dbSLeo Liu * to deal in the Software without restriction, including without limitation 7c54a60dbSLeo Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c54a60dbSLeo Liu * and/or sell copies of the Software, and to permit persons to whom the 9c54a60dbSLeo Liu * Software is furnished to do so, subject to the following conditions: 10c54a60dbSLeo Liu * 11c54a60dbSLeo Liu * The above copyright notice and this permission notice shall be included 12c54a60dbSLeo Liu * in all copies or substantial portions of the Software. 13c54a60dbSLeo Liu * 14c54a60dbSLeo Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15c54a60dbSLeo Liu * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c54a60dbSLeo Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c54a60dbSLeo Liu * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18c54a60dbSLeo Liu * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19c54a60dbSLeo Liu * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20c54a60dbSLeo Liu */ 21c54a60dbSLeo Liu 22c54a60dbSLeo Liu #ifndef _vcn_2_5_OFFSET_HEADER 23c54a60dbSLeo Liu #define _vcn_2_5_OFFSET_HEADER 24c54a60dbSLeo Liu 25c54a60dbSLeo Liu // addressBlock: uvd0_mmsch_dec 26c54a60dbSLeo Liu // base address: 0x1e000 276aec5bb4SJane Jian #define mmMMSCH_VF_VMID 0x000b 286aec5bb4SJane Jian #define mmMMSCH_VF_VMID_BASE_IDX 0 296aec5bb4SJane Jian #define mmMMSCH_VF_CTX_ADDR_LO 0x000c 306aec5bb4SJane Jian #define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0 316aec5bb4SJane Jian #define mmMMSCH_VF_CTX_ADDR_HI 0x000d 326aec5bb4SJane Jian #define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0 336aec5bb4SJane Jian #define mmMMSCH_VF_CTX_SIZE 0x000e 346aec5bb4SJane Jian #define mmMMSCH_VF_CTX_SIZE_BASE_IDX 0 356aec5bb4SJane Jian #define mmMMSCH_VF_MAILBOX_HOST 0x0012 366aec5bb4SJane Jian #define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX 0 376aec5bb4SJane Jian #define mmMMSCH_VF_MAILBOX_RESP 0x0013 386aec5bb4SJane Jian #define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX 0 39c54a60dbSLeo Liu 40c54a60dbSLeo Liu 41c54a60dbSLeo Liu // addressBlock: uvd0_jpegnpdec 42c54a60dbSLeo Liu // base address: 0x1e200 43c54a60dbSLeo Liu #define mmUVD_JPEG_CNTL 0x0080 44c54a60dbSLeo Liu #define mmUVD_JPEG_CNTL_BASE_IDX 0 45c54a60dbSLeo Liu #define mmUVD_JPEG_RB_BASE 0x0081 46c54a60dbSLeo Liu #define mmUVD_JPEG_RB_BASE_BASE_IDX 0 47c54a60dbSLeo Liu #define mmUVD_JPEG_RB_WPTR 0x0082 48c54a60dbSLeo Liu #define mmUVD_JPEG_RB_WPTR_BASE_IDX 0 49c54a60dbSLeo Liu #define mmUVD_JPEG_RB_RPTR 0x0083 50c54a60dbSLeo Liu #define mmUVD_JPEG_RB_RPTR_BASE_IDX 0 51c54a60dbSLeo Liu #define mmUVD_JPEG_RB_SIZE 0x0084 52c54a60dbSLeo Liu #define mmUVD_JPEG_RB_SIZE_BASE_IDX 0 53c54a60dbSLeo Liu #define mmUVD_JPEG_DEC_SCRATCH0 0x0089 54c54a60dbSLeo Liu #define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0 55c54a60dbSLeo Liu #define mmUVD_JPEG_INT_EN 0x008a 56c54a60dbSLeo Liu #define mmUVD_JPEG_INT_EN_BASE_IDX 0 57c54a60dbSLeo Liu #define mmUVD_JPEG_INT_STAT 0x008b 58c54a60dbSLeo Liu #define mmUVD_JPEG_INT_STAT_BASE_IDX 0 59c54a60dbSLeo Liu #define mmUVD_JPEG_PITCH 0x009f 60c54a60dbSLeo Liu #define mmUVD_JPEG_PITCH_BASE_IDX 0 61c54a60dbSLeo Liu #define mmUVD_JPEG_UV_PITCH 0x00a0 62c54a60dbSLeo Liu #define mmUVD_JPEG_UV_PITCH_BASE_IDX 0 63c54a60dbSLeo Liu #define mmJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1 64c54a60dbSLeo Liu #define mmJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0 65c54a60dbSLeo Liu #define mmJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2 66c54a60dbSLeo Liu #define mmJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0 67c54a60dbSLeo Liu #define mmJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3 68c54a60dbSLeo Liu #define mmJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0 69c54a60dbSLeo Liu #define mmJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4 70c54a60dbSLeo Liu #define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 71c54a60dbSLeo Liu #define mmJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5 72c54a60dbSLeo Liu #define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 73c54a60dbSLeo Liu #define mmJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6 74c54a60dbSLeo Liu #define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0 75c54a60dbSLeo Liu #define mmJPEG_DEC_ADDR_MODE 0x00a7 76c54a60dbSLeo Liu #define mmJPEG_DEC_ADDR_MODE_BASE_IDX 0 77c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_CMD 0x00a9 78c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 0 79c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_DATA0 0x00aa 80c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX 0 81c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_DATA1 0x00ab 82c54a60dbSLeo Liu #define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX 0 83c54a60dbSLeo Liu #define mmUVD_JPEG_SCRATCH1 0x00ae 84c54a60dbSLeo Liu #define mmUVD_JPEG_SCRATCH1_BASE_IDX 0 85c54a60dbSLeo Liu #define mmUVD_JPEG_DEC_SOFT_RST 0x00af 86c54a60dbSLeo Liu #define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0 87c54a60dbSLeo Liu 88c54a60dbSLeo Liu 89c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jpeg_enc_dec 90c54a60dbSLeo Liu // base address: 0x1e300 91c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_INT_EN 0x00c1 92c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_INT_EN_BASE_IDX 0 93c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_INT_STATUS 0x00c2 94c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0 95c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_ENGINE_CNTL 0x00c5 96c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0 97c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SCRATCH1 0x00ce 98c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0 99c54a60dbSLeo Liu 100c54a60dbSLeo Liu 101c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 102c54a60dbSLeo Liu // base address: 0x1e380 103c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_STATUS 0x00e5 104c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_STATUS_BASE_IDX 0 105c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PITCH 0x00e6 106c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PITCH_BASE_IDX 0 107c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_LUMA_BASE 0x00e7 108c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0 109c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CHROMAU_BASE 0x00e8 110c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0 111c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CHROMAV_BASE 0x00e9 112c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX 0 113c54a60dbSLeo Liu #define mmJPEG_ENC_Y_GFX10_TILING_SURFACE 0x00ea 114c54a60dbSLeo Liu #define mmJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 115c54a60dbSLeo Liu #define mmJPEG_ENC_UV_GFX10_TILING_SURFACE 0x00eb 116c54a60dbSLeo Liu #define mmJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 117c54a60dbSLeo Liu #define mmJPEG_ENC_GFX10_ADDR_CONFIG 0x00ec 118c54a60dbSLeo Liu #define mmJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX 0 119c54a60dbSLeo Liu #define mmJPEG_ENC_ADDR_MODE 0x00ed 120c54a60dbSLeo Liu #define mmJPEG_ENC_ADDR_MODE_BASE_IDX 0 121c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_CMD 0x00ee 122c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX 0 123c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_DATA0 0x00ef 124c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX 0 125c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_DATA1 0x00f0 126c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX 0 127c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CGC_CNTL 0x00f5 128c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_CGC_CNTL_BASE_IDX 0 129c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SCRATCH0 0x00f6 130c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SCRATCH0_BASE_IDX 0 131c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SOFT_RST 0x00f7 132c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_SOFT_RST_BASE_IDX 0 133c54a60dbSLeo Liu 134c54a60dbSLeo Liu 135c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jrbc_dec 136c54a60dbSLeo Liu // base address: 0x1e400 137c54a60dbSLeo Liu #define mmUVD_JRBC_RB_WPTR 0x0100 138c54a60dbSLeo Liu #define mmUVD_JRBC_RB_WPTR_BASE_IDX 0 139c54a60dbSLeo Liu #define mmUVD_JRBC_RB_CNTL 0x0101 140c54a60dbSLeo Liu #define mmUVD_JRBC_RB_CNTL_BASE_IDX 0 141c54a60dbSLeo Liu #define mmUVD_JRBC_IB_SIZE 0x0102 142c54a60dbSLeo Liu #define mmUVD_JRBC_IB_SIZE_BASE_IDX 0 143c54a60dbSLeo Liu #define mmUVD_JRBC_URGENT_CNTL 0x0103 144c54a60dbSLeo Liu #define mmUVD_JRBC_URGENT_CNTL_BASE_IDX 0 145c54a60dbSLeo Liu #define mmUVD_JRBC_RB_REF_DATA 0x0104 146c54a60dbSLeo Liu #define mmUVD_JRBC_RB_REF_DATA_BASE_IDX 0 147c54a60dbSLeo Liu #define mmUVD_JRBC_RB_COND_RD_TIMER 0x0105 148c54a60dbSLeo Liu #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 149c54a60dbSLeo Liu #define mmUVD_JRBC_SOFT_RESET 0x0108 150c54a60dbSLeo Liu #define mmUVD_JRBC_SOFT_RESET_BASE_IDX 0 151c54a60dbSLeo Liu #define mmUVD_JRBC_STATUS 0x0109 152c54a60dbSLeo Liu #define mmUVD_JRBC_STATUS_BASE_IDX 0 153c54a60dbSLeo Liu #define mmUVD_JRBC_RB_RPTR 0x010a 154c54a60dbSLeo Liu #define mmUVD_JRBC_RB_RPTR_BASE_IDX 0 155c54a60dbSLeo Liu #define mmUVD_JRBC_RB_BUF_STATUS 0x010b 156c54a60dbSLeo Liu #define mmUVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 157c54a60dbSLeo Liu #define mmUVD_JRBC_IB_BUF_STATUS 0x010c 158c54a60dbSLeo Liu #define mmUVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 159c54a60dbSLeo Liu #define mmUVD_JRBC_IB_SIZE_UPDATE 0x010d 160c54a60dbSLeo Liu #define mmUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 161c54a60dbSLeo Liu #define mmUVD_JRBC_IB_COND_RD_TIMER 0x010e 162c54a60dbSLeo Liu #define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 163c54a60dbSLeo Liu #define mmUVD_JRBC_IB_REF_DATA 0x010f 164c54a60dbSLeo Liu #define mmUVD_JRBC_IB_REF_DATA_BASE_IDX 0 165c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_CMD 0x0110 166c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_CMD_BASE_IDX 0 167c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_FENCE_DATA0 0x0111 168c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 169c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_FENCE_DATA1 0x0112 170c54a60dbSLeo Liu #define mmUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 171c54a60dbSLeo Liu #define mmUVD_JRBC_RB_SIZE 0x0113 172c54a60dbSLeo Liu #define mmUVD_JRBC_RB_SIZE_BASE_IDX 0 173c54a60dbSLeo Liu #define mmUVD_JRBC_SCRATCH0 0x0114 174c54a60dbSLeo Liu #define mmUVD_JRBC_SCRATCH0_BASE_IDX 0 175c54a60dbSLeo Liu 176c54a60dbSLeo Liu 177c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jrbc_enc_dec 178c54a60dbSLeo Liu // base address: 0x1e480 179c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_WPTR 0x0120 180c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_WPTR_BASE_IDX 0 181c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_CNTL 0x0121 182c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_CNTL_BASE_IDX 0 183c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_SIZE 0x0122 184c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_SIZE_BASE_IDX 0 185c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_URGENT_CNTL 0x0123 186c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX 0 187c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_REF_DATA 0x0124 188c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX 0 189c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER 0x0125 190c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX 0 191c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_SOFT_RESET 0x0128 192c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_SOFT_RESET_BASE_IDX 0 193c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_STATUS 0x0129 194c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_STATUS_BASE_IDX 0 195c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_RPTR 0x012a 196c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_RPTR_BASE_IDX 0 197c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_BUF_STATUS 0x012b 198c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX 0 199c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_BUF_STATUS 0x012c 200c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX 0 201c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_SIZE_UPDATE 0x012d 202c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX 0 203c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_COND_RD_TIMER 0x012e 204c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX 0 205c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_REF_DATA 0x012f 206c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX 0 207c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_CMD 0x0130 208c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX 0 209c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0x0131 210c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX 0 211c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0x0132 212c54a60dbSLeo Liu #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX 0 213c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_SIZE 0x0133 214c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_RB_SIZE_BASE_IDX 0 215c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_SCRATCH0 0x0134 216c54a60dbSLeo Liu #define mmUVD_JRBC_ENC_SCRATCH0_BASE_IDX 0 217c54a60dbSLeo Liu 218c54a60dbSLeo Liu 219c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jmi_dec 220c54a60dbSLeo Liu // base address: 0x1e500 221c54a60dbSLeo Liu #define mmUVD_JMI_CTRL 0x0145 222c54a60dbSLeo Liu #define mmUVD_JMI_CTRL_BASE_IDX 0 223c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_CTRL 0x0146 224c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_CTRL_BASE_IDX 0 225c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_CTRL 0x0147 226c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_CTRL_BASE_IDX 0 227c54a60dbSLeo Liu #define mmUVD_JMI_EJRBC_CTRL 0x0148 228c54a60dbSLeo Liu #define mmUVD_JMI_EJRBC_CTRL_BASE_IDX 0 229c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_CTRL 0x0149 230c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_CTRL_BASE_IDX 0 231c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_VMID 0x014f 232c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 0 233c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_VMID 0x0150 234c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX 0 235c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_VMID 0x0151 236c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_VMID_BASE_IDX 0 237c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JRBC_IB_VMID 0x0152 238c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 0 239c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JRBC_RB_VMID 0x0153 240c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 0 241c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JPEG_VMID 0x0154 242c54a60dbSLeo Liu #define mmUVD_JMI_ENC_JPEG_VMID_BASE_IDX 0 243c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_CTRL 0x015c 244c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_CTRL_BASE_IDX 0 245c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_COUNT_LO 0x015d 246c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 0 247c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_COUNT_HI 0x015e 248c54a60dbSLeo Liu #define mmUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 0 249c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0160 250c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 251c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0161 252c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 253c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0162 254c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 255c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0163 256c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 257c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0164 258c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 259c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0165 260c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 261c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166 262c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 263c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167 264c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 265c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0168 266c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 267c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0169 268c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 269c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016a 270c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 271c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b 272c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 273c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x016c 274c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 275c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x016d 276c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 277c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x016e 278c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 279c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x016f 280c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 281c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0170 282c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 283c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0171 284c54a60dbSLeo Liu #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 285c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x017a 286c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 287c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x017b 288c54a60dbSLeo Liu #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 289c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x017c 290c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 291c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x017d 292c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 293c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x017e 294c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 295c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x017f 296c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 297c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x0180 298c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 299c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x0181 300c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 301c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0182 302c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 303c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0183 304c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 305c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0184 306c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 307c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0185 308c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 309c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0186 310c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 311c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0187 312c54a60dbSLeo Liu #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 313c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_VMID 0x0188 314c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 315c54a60dbSLeo Liu #define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x0189 316c54a60dbSLeo Liu #define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 0 317c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_VMID 0x018a 318c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_VMID_BASE_IDX 0 319c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x018b 320c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 0 321c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x018c 322c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 0 323c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x018d 324c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 0 325c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x018e 326c54a60dbSLeo Liu #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 327c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_CTRL2 0x018f 328c54a60dbSLeo Liu #define mmUVD_LMI_JPEG_CTRL2_BASE_IDX 0 329c54a60dbSLeo Liu #define mmUVD_JMI_DEC_SWAP_CNTL 0x0190 330c54a60dbSLeo Liu #define mmUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 331c54a60dbSLeo Liu #define mmUVD_JMI_ENC_SWAP_CNTL 0x0191 332c54a60dbSLeo Liu #define mmUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 0 333c54a60dbSLeo Liu #define mmUVD_JMI_CNTL 0x0192 334c54a60dbSLeo Liu #define mmUVD_JMI_CNTL_BASE_IDX 0 335c54a60dbSLeo Liu #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x019a 336c54a60dbSLeo Liu #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 0 337c54a60dbSLeo Liu #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x019b 338c54a60dbSLeo Liu #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 339c54a60dbSLeo Liu #define mmUVD_JMI_DEC_SWAP_CNTL2 0x019c 340c54a60dbSLeo Liu #define mmUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 0 341c54a60dbSLeo Liu 342c54a60dbSLeo Liu 343c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jpeg_common_dec 344c54a60dbSLeo Liu // base address: 0x1e700 345c54a60dbSLeo Liu #define mmJPEG_SOFT_RESET_STATUS 0x01c0 346c54a60dbSLeo Liu #define mmJPEG_SOFT_RESET_STATUS_BASE_IDX 0 347c54a60dbSLeo Liu #define mmJPEG_SYS_INT_EN 0x01c1 348c54a60dbSLeo Liu #define mmJPEG_SYS_INT_EN_BASE_IDX 0 349c54a60dbSLeo Liu #define mmJPEG_SYS_INT_STATUS 0x01c2 350c54a60dbSLeo Liu #define mmJPEG_SYS_INT_STATUS_BASE_IDX 0 351c54a60dbSLeo Liu #define mmJPEG_SYS_INT_ACK 0x01c3 352c54a60dbSLeo Liu #define mmJPEG_SYS_INT_ACK_BASE_IDX 0 353c54a60dbSLeo Liu #define mmJPEG_MASTINT_EN 0x01c8 354c54a60dbSLeo Liu #define mmJPEG_MASTINT_EN_BASE_IDX 0 355c54a60dbSLeo Liu #define mmJPEG_IH_CTRL 0x01c9 356c54a60dbSLeo Liu #define mmJPEG_IH_CTRL_BASE_IDX 0 357c54a60dbSLeo Liu #define mmJRBBM_ARB_CTRL 0x01cb 358c54a60dbSLeo Liu #define mmJRBBM_ARB_CTRL_BASE_IDX 0 359c54a60dbSLeo Liu 360c54a60dbSLeo Liu 361c54a60dbSLeo Liu // addressBlock: uvd0_uvd_jpeg_common_sclk_dec 362c54a60dbSLeo Liu // base address: 0x1e780 363c54a60dbSLeo Liu #define mmJPEG_CGC_GATE 0x01e0 364c54a60dbSLeo Liu #define mmJPEG_CGC_GATE_BASE_IDX 0 365c54a60dbSLeo Liu #define mmJPEG_CGC_CTRL 0x01e1 366c54a60dbSLeo Liu #define mmJPEG_CGC_CTRL_BASE_IDX 0 367c54a60dbSLeo Liu #define mmJPEG_CGC_STATUS 0x01e2 368c54a60dbSLeo Liu #define mmJPEG_CGC_STATUS_BASE_IDX 0 369c54a60dbSLeo Liu #define mmJPEG_COMN_CGC_MEM_CTRL 0x01e3 370c54a60dbSLeo Liu #define mmJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 0 371c54a60dbSLeo Liu #define mmJPEG_DEC_CGC_MEM_CTRL 0x01e4 372c54a60dbSLeo Liu #define mmJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 0 373c54a60dbSLeo Liu #define mmJPEG2_DEC_CGC_MEM_CTRL 0x01e5 374c54a60dbSLeo Liu #define mmJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 0 375c54a60dbSLeo Liu #define mmJPEG_ENC_CGC_MEM_CTRL 0x01e6 376c54a60dbSLeo Liu #define mmJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 0 377c54a60dbSLeo Liu #define mmJPEG_SOFT_RESET2 0x01e7 378c54a60dbSLeo Liu #define mmJPEG_SOFT_RESET2_BASE_IDX 0 379c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_CONF 0x01e8 380c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_CONF_BASE_IDX 0 381c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_EVENT_SEL 0x01e9 382c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 0 383c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT0 0x01ea 384c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT0_BASE_IDX 0 385c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT1 0x01eb 386c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT1_BASE_IDX 0 387c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT2 0x01ec 388c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT2_BASE_IDX 0 389c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT3 0x01ed 390c54a60dbSLeo Liu #define mmJPEG_PERF_BANK_COUNT3_BASE_IDX 0 391c54a60dbSLeo Liu 392c54a60dbSLeo Liu 393c54a60dbSLeo Liu // addressBlock: uvd0_uvd_pg_dec 394c54a60dbSLeo Liu // base address: 0x1f800 395c54a60dbSLeo Liu #define mmUVD_PGFSM_CONFIG 0x0000 396c54a60dbSLeo Liu #define mmUVD_PGFSM_CONFIG_BASE_IDX 1 397c54a60dbSLeo Liu #define mmUVD_PGFSM_STATUS 0x0001 398c54a60dbSLeo Liu #define mmUVD_PGFSM_STATUS_BASE_IDX 1 399c54a60dbSLeo Liu #define mmUVD_POWER_STATUS 0x0004 400c54a60dbSLeo Liu #define mmUVD_POWER_STATUS_BASE_IDX 1 401c54a60dbSLeo Liu #define mmUVD_PG_IND_INDEX 0x0005 402c54a60dbSLeo Liu #define mmUVD_PG_IND_INDEX_BASE_IDX 1 403c54a60dbSLeo Liu #define mmUVD_PG_IND_DATA 0x0006 404c54a60dbSLeo Liu #define mmUVD_PG_IND_DATA_BASE_IDX 1 405c54a60dbSLeo Liu #define mmCC_UVD_HARVESTING 0x0007 406c54a60dbSLeo Liu #define mmCC_UVD_HARVESTING_BASE_IDX 1 407c54a60dbSLeo Liu #define mmUVD_JPEG_POWER_STATUS 0x000a 408c54a60dbSLeo Liu #define mmUVD_JPEG_POWER_STATUS_BASE_IDX 1 409c54a60dbSLeo Liu #define mmUVD_DPG_LMA_CTL 0x0011 410c54a60dbSLeo Liu #define mmUVD_DPG_LMA_CTL_BASE_IDX 1 411c54a60dbSLeo Liu #define mmUVD_DPG_LMA_DATA 0x0012 412c54a60dbSLeo Liu #define mmUVD_DPG_LMA_DATA_BASE_IDX 1 413c54a60dbSLeo Liu #define mmUVD_DPG_LMA_MASK 0x0013 414c54a60dbSLeo Liu #define mmUVD_DPG_LMA_MASK_BASE_IDX 1 415c54a60dbSLeo Liu #define mmUVD_DPG_PAUSE 0x0014 416c54a60dbSLeo Liu #define mmUVD_DPG_PAUSE_BASE_IDX 1 417c54a60dbSLeo Liu #define mmUVD_SCRATCH1 0x0015 418c54a60dbSLeo Liu #define mmUVD_SCRATCH1_BASE_IDX 1 419c54a60dbSLeo Liu #define mmUVD_SCRATCH2 0x0016 420c54a60dbSLeo Liu #define mmUVD_SCRATCH2_BASE_IDX 1 421c54a60dbSLeo Liu #define mmUVD_SCRATCH3 0x0017 422c54a60dbSLeo Liu #define mmUVD_SCRATCH3_BASE_IDX 1 423c54a60dbSLeo Liu #define mmUVD_SCRATCH4 0x0018 424c54a60dbSLeo Liu #define mmUVD_SCRATCH4_BASE_IDX 1 425c54a60dbSLeo Liu #define mmUVD_SCRATCH5 0x0019 426c54a60dbSLeo Liu #define mmUVD_SCRATCH5_BASE_IDX 1 427c54a60dbSLeo Liu #define mmUVD_SCRATCH6 0x001a 428c54a60dbSLeo Liu #define mmUVD_SCRATCH6_BASE_IDX 1 429c54a60dbSLeo Liu #define mmUVD_SCRATCH7 0x001b 430c54a60dbSLeo Liu #define mmUVD_SCRATCH7_BASE_IDX 1 431c54a60dbSLeo Liu #define mmUVD_SCRATCH8 0x001c 432c54a60dbSLeo Liu #define mmUVD_SCRATCH8_BASE_IDX 1 433c54a60dbSLeo Liu #define mmUVD_SCRATCH9 0x001d 434c54a60dbSLeo Liu #define mmUVD_SCRATCH9_BASE_IDX 1 435c54a60dbSLeo Liu #define mmUVD_SCRATCH10 0x001e 436c54a60dbSLeo Liu #define mmUVD_SCRATCH10_BASE_IDX 1 437c54a60dbSLeo Liu #define mmUVD_SCRATCH11 0x001f 438c54a60dbSLeo Liu #define mmUVD_SCRATCH11_BASE_IDX 1 439c54a60dbSLeo Liu #define mmUVD_SCRATCH12 0x0020 440c54a60dbSLeo Liu #define mmUVD_SCRATCH12_BASE_IDX 1 441c54a60dbSLeo Liu #define mmUVD_SCRATCH13 0x0021 442c54a60dbSLeo Liu #define mmUVD_SCRATCH13_BASE_IDX 1 443c54a60dbSLeo Liu #define mmUVD_SCRATCH14 0x0022 444c54a60dbSLeo Liu #define mmUVD_SCRATCH14_BASE_IDX 1 445c54a60dbSLeo Liu #define mmUVD_FREE_COUNTER_REG 0x0024 446c54a60dbSLeo Liu #define mmUVD_FREE_COUNTER_REG_BASE_IDX 1 447c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0025 448c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 449c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0026 450c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 451c54a60dbSLeo Liu #define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x0027 452c54a60dbSLeo Liu #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 453c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_VMID 0x0028 454c54a60dbSLeo Liu #define mmUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 455c54a60dbSLeo Liu #define mmUVD_PF_STATUS 0x0039 456c54a60dbSLeo Liu #define mmUVD_PF_STATUS_BASE_IDX 1 457c54a60dbSLeo Liu #define mmUVD_DPG_CLK_EN_VCPU_REPORT 0x003c 458c54a60dbSLeo Liu #define mmUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 459c54a60dbSLeo Liu #define mmUVD_GFX8_ADDR_CONFIG 0x0049 460c54a60dbSLeo Liu #define mmUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 461c54a60dbSLeo Liu #define mmUVD_GFX10_ADDR_CONFIG 0x004a 462c54a60dbSLeo Liu #define mmUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 463c54a60dbSLeo Liu #define mmUVD_GPCNT2_CNTL 0x004b 464c54a60dbSLeo Liu #define mmUVD_GPCNT2_CNTL_BASE_IDX 1 465c54a60dbSLeo Liu #define mmUVD_GPCNT2_TARGET_LOWER 0x004c 466c54a60dbSLeo Liu #define mmUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 467c54a60dbSLeo Liu #define mmUVD_GPCNT2_STATUS_LOWER 0x004d 468c54a60dbSLeo Liu #define mmUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 469c54a60dbSLeo Liu #define mmUVD_GPCNT2_TARGET_UPPER 0x004e 470c54a60dbSLeo Liu #define mmUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 471c54a60dbSLeo Liu #define mmUVD_GPCNT2_STATUS_UPPER 0x004f 472c54a60dbSLeo Liu #define mmUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 473c54a60dbSLeo Liu #define mmUVD_GPCNT3_CNTL 0x0050 474c54a60dbSLeo Liu #define mmUVD_GPCNT3_CNTL_BASE_IDX 1 475c54a60dbSLeo Liu #define mmUVD_GPCNT3_TARGET_LOWER 0x0051 476c54a60dbSLeo Liu #define mmUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 477c54a60dbSLeo Liu #define mmUVD_GPCNT3_STATUS_LOWER 0x0052 478c54a60dbSLeo Liu #define mmUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 479c54a60dbSLeo Liu #define mmUVD_GPCNT3_TARGET_UPPER 0x0053 480c54a60dbSLeo Liu #define mmUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 481c54a60dbSLeo Liu #define mmUVD_GPCNT3_STATUS_UPPER 0x0054 482c54a60dbSLeo Liu #define mmUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 483c54a60dbSLeo Liu 484c54a60dbSLeo Liu 485c54a60dbSLeo Liu // addressBlock: uvd0_uvddec 486c54a60dbSLeo Liu // base address: 0x1fa00 487c54a60dbSLeo Liu #define mmUVD_STATUS 0x0080 488c54a60dbSLeo Liu #define mmUVD_STATUS_BASE_IDX 1 489c54a60dbSLeo Liu #define mmUVD_ENC_PIPE_BUSY 0x0081 490c54a60dbSLeo Liu #define mmUVD_ENC_PIPE_BUSY_BASE_IDX 1 491c54a60dbSLeo Liu #define mmUVD_SOFT_RESET 0x0084 492c54a60dbSLeo Liu #define mmUVD_SOFT_RESET_BASE_IDX 1 493c54a60dbSLeo Liu #define mmUVD_SOFT_RESET2 0x0085 494c54a60dbSLeo Liu #define mmUVD_SOFT_RESET2_BASE_IDX 1 495c54a60dbSLeo Liu #define mmUVD_MMSCH_SOFT_RESET 0x0086 496c54a60dbSLeo Liu #define mmUVD_MMSCH_SOFT_RESET_BASE_IDX 1 497c54a60dbSLeo Liu #define mmUVD_CGC_GATE 0x0088 498c54a60dbSLeo Liu #define mmUVD_CGC_GATE_BASE_IDX 1 499c54a60dbSLeo Liu #define mmUVD_CGC_STATUS 0x0089 500c54a60dbSLeo Liu #define mmUVD_CGC_STATUS_BASE_IDX 1 501c54a60dbSLeo Liu #define mmUVD_CGC_CTRL 0x008a 502c54a60dbSLeo Liu #define mmUVD_CGC_CTRL_BASE_IDX 1 503c54a60dbSLeo Liu #define mmUVD_CGC_UDEC_STATUS 0x008b 504c54a60dbSLeo Liu #define mmUVD_CGC_UDEC_STATUS_BASE_IDX 1 505c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_GATE 0x008c 506c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_GATE_BASE_IDX 1 507c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_STATUS 0x008d 508c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_STATUS_BASE_IDX 1 509c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_CTRL 0x008e 510c54a60dbSLeo Liu #define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1 511c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_CMD 0x008f 512c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1 513c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_DATA0 0x0090 514c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 515c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_DATA1 0x0091 516c54a60dbSLeo Liu #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 517c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_CMD 0x0092 518c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_CMD_BASE_IDX 1 519c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_DATA0 0x0093 520c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_DATA0_BASE_IDX 1 521c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_DATA1 0x0094 522c54a60dbSLeo Liu #define mmUVD_GPCOM_SYS_DATA1_BASE_IDX 1 523c54a60dbSLeo Liu #define mmUVD_VCPU_INT_EN 0x0095 524c54a60dbSLeo Liu #define mmUVD_VCPU_INT_EN_BASE_IDX 1 525c54a60dbSLeo Liu #define mmUVD_VCPU_INT_ACK 0x0097 526c54a60dbSLeo Liu #define mmUVD_VCPU_INT_ACK_BASE_IDX 1 527c54a60dbSLeo Liu #define mmUVD_VCPU_INT_ROUTE 0x0098 528c54a60dbSLeo Liu #define mmUVD_VCPU_INT_ROUTE_BASE_IDX 1 529c54a60dbSLeo Liu #define mmUVD_ENC_VCPU_INT_EN 0x009e 530c54a60dbSLeo Liu #define mmUVD_ENC_VCPU_INT_EN_BASE_IDX 1 531c54a60dbSLeo Liu #define mmUVD_ENC_VCPU_INT_ACK 0x00a0 532c54a60dbSLeo Liu #define mmUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 533c54a60dbSLeo Liu #define mmUVD_MASTINT_EN 0x00a1 534c54a60dbSLeo Liu #define mmUVD_MASTINT_EN_BASE_IDX 1 535c54a60dbSLeo Liu #define mmUVD_SYS_INT_EN 0x00a2 536c54a60dbSLeo Liu #define mmUVD_SYS_INT_EN_BASE_IDX 1 537c54a60dbSLeo Liu #define mmUVD_SYS_INT_STATUS 0x00a3 538c54a60dbSLeo Liu #define mmUVD_SYS_INT_STATUS_BASE_IDX 1 539c54a60dbSLeo Liu #define mmUVD_SYS_INT_ACK 0x00a4 540c54a60dbSLeo Liu #define mmUVD_SYS_INT_ACK_BASE_IDX 1 541c54a60dbSLeo Liu #define mmUVD_JOB_DONE 0x00a5 542c54a60dbSLeo Liu #define mmUVD_JOB_DONE_BASE_IDX 1 543c54a60dbSLeo Liu #define mmUVD_CBUF_ID 0x00a6 544c54a60dbSLeo Liu #define mmUVD_CBUF_ID_BASE_IDX 1 545c54a60dbSLeo Liu #define mmUVD_CONTEXT_ID 0x00a7 546c54a60dbSLeo Liu #define mmUVD_CONTEXT_ID_BASE_IDX 1 547c54a60dbSLeo Liu #define mmUVD_CONTEXT_ID2 0x00a8 548c54a60dbSLeo Liu #define mmUVD_CONTEXT_ID2_BASE_IDX 1 549c54a60dbSLeo Liu #define mmUVD_NO_OP 0x00a9 550c54a60dbSLeo Liu #define mmUVD_NO_OP_BASE_IDX 1 551c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO 0x00aa 552c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO_BASE_IDX 1 553c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI 0x00ab 554c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI_BASE_IDX 1 555c54a60dbSLeo Liu #define mmUVD_RB_SIZE 0x00ac 556c54a60dbSLeo Liu #define mmUVD_RB_SIZE_BASE_IDX 1 557c54a60dbSLeo Liu #define mmUVD_RB_RPTR 0x00ad 558c54a60dbSLeo Liu #define mmUVD_RB_RPTR_BASE_IDX 1 559c54a60dbSLeo Liu #define mmUVD_RB_WPTR 0x00ae 560c54a60dbSLeo Liu #define mmUVD_RB_WPTR_BASE_IDX 1 561c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO2 0x00af 562c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO2_BASE_IDX 1 563c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI2 0x00b0 564c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI2_BASE_IDX 1 565c54a60dbSLeo Liu #define mmUVD_RB_SIZE2 0x00b1 566c54a60dbSLeo Liu #define mmUVD_RB_SIZE2_BASE_IDX 1 567c54a60dbSLeo Liu #define mmUVD_RB_RPTR2 0x00b2 568c54a60dbSLeo Liu #define mmUVD_RB_RPTR2_BASE_IDX 1 569c54a60dbSLeo Liu #define mmUVD_RB_WPTR2 0x00b3 570c54a60dbSLeo Liu #define mmUVD_RB_WPTR2_BASE_IDX 1 571c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO3 0x00b4 572c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO3_BASE_IDX 1 573c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI3 0x00b5 574c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI3_BASE_IDX 1 575c54a60dbSLeo Liu #define mmUVD_RB_SIZE3 0x00b6 576c54a60dbSLeo Liu #define mmUVD_RB_SIZE3_BASE_IDX 1 577c54a60dbSLeo Liu #define mmUVD_RB_RPTR3 0x00b7 578c54a60dbSLeo Liu #define mmUVD_RB_RPTR3_BASE_IDX 1 579c54a60dbSLeo Liu #define mmUVD_RB_WPTR3 0x00b8 580c54a60dbSLeo Liu #define mmUVD_RB_WPTR3_BASE_IDX 1 581c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO4 0x00b9 582c54a60dbSLeo Liu #define mmUVD_RB_BASE_LO4_BASE_IDX 1 583c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI4 0x00ba 584c54a60dbSLeo Liu #define mmUVD_RB_BASE_HI4_BASE_IDX 1 585c54a60dbSLeo Liu #define mmUVD_RB_SIZE4 0x00bb 586c54a60dbSLeo Liu #define mmUVD_RB_SIZE4_BASE_IDX 1 587c54a60dbSLeo Liu #define mmUVD_RB_RPTR4 0x00bc 588c54a60dbSLeo Liu #define mmUVD_RB_RPTR4_BASE_IDX 1 589c54a60dbSLeo Liu #define mmUVD_RB_WPTR4 0x00bd 590c54a60dbSLeo Liu #define mmUVD_RB_WPTR4_BASE_IDX 1 591c54a60dbSLeo Liu #define mmUVD_OUT_RB_BASE_LO 0x00be 592c54a60dbSLeo Liu #define mmUVD_OUT_RB_BASE_LO_BASE_IDX 1 593c54a60dbSLeo Liu #define mmUVD_OUT_RB_BASE_HI 0x00bf 594c54a60dbSLeo Liu #define mmUVD_OUT_RB_BASE_HI_BASE_IDX 1 595c54a60dbSLeo Liu #define mmUVD_OUT_RB_SIZE 0x00c0 596c54a60dbSLeo Liu #define mmUVD_OUT_RB_SIZE_BASE_IDX 1 597c54a60dbSLeo Liu #define mmUVD_OUT_RB_RPTR 0x00c1 598c54a60dbSLeo Liu #define mmUVD_OUT_RB_RPTR_BASE_IDX 1 599c54a60dbSLeo Liu #define mmUVD_OUT_RB_WPTR 0x00c2 600c54a60dbSLeo Liu #define mmUVD_OUT_RB_WPTR_BASE_IDX 1 601c54a60dbSLeo Liu #define mmUVD_RB_ARB_CTRL 0x00c6 602c54a60dbSLeo Liu #define mmUVD_RB_ARB_CTRL_BASE_IDX 1 603c54a60dbSLeo Liu #define mmUVD_CTX_INDEX 0x00c7 604c54a60dbSLeo Liu #define mmUVD_CTX_INDEX_BASE_IDX 1 605c54a60dbSLeo Liu #define mmUVD_CTX_DATA 0x00c8 606c54a60dbSLeo Liu #define mmUVD_CTX_DATA_BASE_IDX 1 607c54a60dbSLeo Liu #define mmUVD_CXW_WR 0x00c9 608c54a60dbSLeo Liu #define mmUVD_CXW_WR_BASE_IDX 1 609c54a60dbSLeo Liu #define mmUVD_CXW_WR_INT_ID 0x00ca 610c54a60dbSLeo Liu #define mmUVD_CXW_WR_INT_ID_BASE_IDX 1 611c54a60dbSLeo Liu #define mmUVD_CXW_WR_INT_CTX_ID 0x00cb 612c54a60dbSLeo Liu #define mmUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 613c54a60dbSLeo Liu #define mmUVD_CXW_INT_ID 0x00cc 614c54a60dbSLeo Liu #define mmUVD_CXW_INT_ID_BASE_IDX 1 615c54a60dbSLeo Liu #define mmUVD_TOP_CTRL 0x00cf 616c54a60dbSLeo Liu #define mmUVD_TOP_CTRL_BASE_IDX 1 617c54a60dbSLeo Liu #define mmUVD_YBASE 0x00d0 618c54a60dbSLeo Liu #define mmUVD_YBASE_BASE_IDX 1 619c54a60dbSLeo Liu #define mmUVD_UVBASE 0x00d1 620c54a60dbSLeo Liu #define mmUVD_UVBASE_BASE_IDX 1 621c54a60dbSLeo Liu #define mmUVD_PITCH 0x00d2 622c54a60dbSLeo Liu #define mmUVD_PITCH_BASE_IDX 1 623c54a60dbSLeo Liu #define mmUVD_WIDTH 0x00d3 624c54a60dbSLeo Liu #define mmUVD_WIDTH_BASE_IDX 1 625c54a60dbSLeo Liu #define mmUVD_HEIGHT 0x00d4 626c54a60dbSLeo Liu #define mmUVD_HEIGHT_BASE_IDX 1 627c54a60dbSLeo Liu #define mmUVD_PICCOUNT 0x00d5 628c54a60dbSLeo Liu #define mmUVD_PICCOUNT_BASE_IDX 1 629c54a60dbSLeo Liu #define mmUVD_SCRATCH_NP 0x00db 630c54a60dbSLeo Liu #define mmUVD_SCRATCH_NP_BASE_IDX 1 631c54a60dbSLeo Liu #define mmUVD_VERSION 0x00dd 632c54a60dbSLeo Liu #define mmUVD_VERSION_BASE_IDX 1 633c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH0 0x00de 634c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH0_BASE_IDX 1 635c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH1 0x00df 636c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH1_BASE_IDX 1 637c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH2 0x00e0 638c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH2_BASE_IDX 1 639c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH3 0x00e1 640c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH3_BASE_IDX 1 641c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH4 0x00e2 642c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH4_BASE_IDX 1 643c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH5 0x00e3 644c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH5_BASE_IDX 1 645c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH6 0x00e4 646c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH6_BASE_IDX 1 647c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH7 0x00e5 648c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH7_BASE_IDX 1 649c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH8 0x00e6 650c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH8_BASE_IDX 1 651c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH9 0x00e7 652c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH9_BASE_IDX 1 653c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH10 0x00e8 654c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH10_BASE_IDX 1 655c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH11 0x00e9 656c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH11_BASE_IDX 1 657c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH12 0x00ea 658c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH12_BASE_IDX 1 659c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH13 0x00eb 660c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH13_BASE_IDX 1 661c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH14 0x00ec 662c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH14_BASE_IDX 1 663c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH15 0x00ed 664c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH15_BASE_IDX 1 665c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH16 0x00ee 666c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH16_BASE_IDX 1 667c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH17 0x00ef 668c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH17_BASE_IDX 1 669c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH18 0x00f0 670c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH18_BASE_IDX 1 671c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH19 0x00f1 672c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH19_BASE_IDX 1 673c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH20 0x00f2 674c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH20_BASE_IDX 1 675c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH21 0x00f3 676c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH21_BASE_IDX 1 677c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH22 0x00f4 678c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH22_BASE_IDX 1 679c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH23 0x00f5 680c54a60dbSLeo Liu #define mmUVD_GP_SCRATCH23_BASE_IDX 1 681c54a60dbSLeo Liu 682c54a60dbSLeo Liu 683c54a60dbSLeo Liu // addressBlock: uvd0_ecpudec 684c54a60dbSLeo Liu // base address: 0x1fd00 685c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET0 0x0140 686c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 687c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE0 0x0141 688c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 689c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET1 0x0142 690c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 691c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE1 0x0143 692c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 693c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET2 0x0144 694c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 695c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE2 0x0145 696c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 697c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET3 0x0146 698c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 699c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE3 0x0147 700c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 701c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET4 0x0148 702c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 703c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE4 0x0149 704c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 705c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET5 0x014a 706c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 707c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE5 0x014b 708c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 709c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET6 0x014c 710c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 711c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE6 0x014d 712c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 713c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET7 0x014e 714c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 715c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE7 0x014f 716c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 717c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET8 0x0150 718c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 719c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE8 0x0151 720c54a60dbSLeo Liu #define mmUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 721c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_OFFSET0 0x0152 722c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 723c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_SIZE0 0x0153 724c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 725c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_OFFSET1 0x0154 726c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 727c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_SIZE1 0x0155 728c54a60dbSLeo Liu #define mmUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 729c54a60dbSLeo Liu #define mmUVD_VCPU_CNTL 0x0156 730c54a60dbSLeo Liu #define mmUVD_VCPU_CNTL_BASE_IDX 1 731c54a60dbSLeo Liu #define mmUVD_VCPU_PRID 0x0157 732c54a60dbSLeo Liu #define mmUVD_VCPU_PRID_BASE_IDX 1 733c54a60dbSLeo Liu #define mmUVD_VCPU_TRCE 0x0158 734c54a60dbSLeo Liu #define mmUVD_VCPU_TRCE_BASE_IDX 1 735c54a60dbSLeo Liu #define mmUVD_VCPU_TRCE_RD 0x0159 736c54a60dbSLeo Liu #define mmUVD_VCPU_TRCE_RD_BASE_IDX 1 737c54a60dbSLeo Liu 738c54a60dbSLeo Liu 739c54a60dbSLeo Liu // addressBlock: uvd0_uvd_mpcdec 740c54a60dbSLeo Liu // base address: 0x20310 741c54a60dbSLeo Liu #define mmUVD_MP_SWAP_CNTL 0x02c4 742c54a60dbSLeo Liu #define mmUVD_MP_SWAP_CNTL_BASE_IDX 1 743c54a60dbSLeo Liu #define mmUVD_MP_SWAP_CNTL2 0x02c5 744c54a60dbSLeo Liu #define mmUVD_MP_SWAP_CNTL2_BASE_IDX 1 745c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_SRCH 0x02c6 746c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_SRCH_BASE_IDX 1 747c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_HIT 0x02c7 748c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_HIT_BASE_IDX 1 749c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_HITPEND 0x02c8 750c54a60dbSLeo Liu #define mmUVD_MPC_LUMA_HITPEND_BASE_IDX 1 751c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_SRCH 0x02c9 752c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_SRCH_BASE_IDX 1 753c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_HIT 0x02ca 754c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_HIT_BASE_IDX 1 755c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_HITPEND 0x02cb 756c54a60dbSLeo Liu #define mmUVD_MPC_CHROMA_HITPEND_BASE_IDX 1 757c54a60dbSLeo Liu #define mmUVD_MPC_CNTL 0x02cc 758c54a60dbSLeo Liu #define mmUVD_MPC_CNTL_BASE_IDX 1 759c54a60dbSLeo Liu #define mmUVD_MPC_PITCH 0x02cd 760c54a60dbSLeo Liu #define mmUVD_MPC_PITCH_BASE_IDX 1 761c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXA0 0x02ce 762c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 763c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXA1 0x02cf 764c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXA1_BASE_IDX 1 765c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXB0 0x02d0 766c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXB0_BASE_IDX 1 767c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXB1 0x02d1 768c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUXB1_BASE_IDX 1 769c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUX 0x02d2 770c54a60dbSLeo Liu #define mmUVD_MPC_SET_MUX_BASE_IDX 1 771c54a60dbSLeo Liu #define mmUVD_MPC_SET_ALU 0x02d3 772c54a60dbSLeo Liu #define mmUVD_MPC_SET_ALU_BASE_IDX 1 773c54a60dbSLeo Liu #define mmUVD_MPC_PERF0 0x02d4 774c54a60dbSLeo Liu #define mmUVD_MPC_PERF0_BASE_IDX 1 775c54a60dbSLeo Liu #define mmUVD_MPC_PERF1 0x02d5 776c54a60dbSLeo Liu #define mmUVD_MPC_PERF1_BASE_IDX 1 777c54a60dbSLeo Liu 778c54a60dbSLeo Liu 779c54a60dbSLeo Liu // addressBlock: uvd0_uvd_rbcdec 780c54a60dbSLeo Liu // base address: 0x20370 781c54a60dbSLeo Liu #define mmUVD_RBC_IB_SIZE 0x02dc 782c54a60dbSLeo Liu #define mmUVD_RBC_IB_SIZE_BASE_IDX 1 783c54a60dbSLeo Liu #define mmUVD_RBC_IB_SIZE_UPDATE 0x02dd 784c54a60dbSLeo Liu #define mmUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1 785c54a60dbSLeo Liu #define mmUVD_RBC_RB_CNTL 0x02de 786c54a60dbSLeo Liu #define mmUVD_RBC_RB_CNTL_BASE_IDX 1 787c54a60dbSLeo Liu #define mmUVD_RBC_RB_RPTR_ADDR 0x02df 788c54a60dbSLeo Liu #define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 789c54a60dbSLeo Liu #define mmUVD_RBC_RB_RPTR 0x02e0 790c54a60dbSLeo Liu #define mmUVD_RBC_RB_RPTR_BASE_IDX 1 791c54a60dbSLeo Liu #define mmUVD_RBC_RB_WPTR 0x02e1 792c54a60dbSLeo Liu #define mmUVD_RBC_RB_WPTR_BASE_IDX 1 793c54a60dbSLeo Liu #define mmUVD_RBC_VCPU_ACCESS 0x02e2 794c54a60dbSLeo Liu #define mmUVD_RBC_VCPU_ACCESS_BASE_IDX 1 795c54a60dbSLeo Liu #define mmUVD_RBC_READ_REQ_URGENT_CNTL 0x02e5 796c54a60dbSLeo Liu #define mmUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1 797c54a60dbSLeo Liu #define mmUVD_RBC_RB_WPTR_CNTL 0x02e6 798c54a60dbSLeo Liu #define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 799c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_STATUS 0x02e7 800c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_STATUS_BASE_IDX 1 801c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_POLL_CNTL 0x02e8 802c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 803c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_POLL_ADDR 0x02e9 804c54a60dbSLeo Liu #define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 805c54a60dbSLeo Liu #define mmUVD_SEMA_CMD 0x02ea 806c54a60dbSLeo Liu #define mmUVD_SEMA_CMD_BASE_IDX 1 807c54a60dbSLeo Liu #define mmUVD_SEMA_ADDR_LOW 0x02eb 808c54a60dbSLeo Liu #define mmUVD_SEMA_ADDR_LOW_BASE_IDX 1 809c54a60dbSLeo Liu #define mmUVD_SEMA_ADDR_HIGH 0x02ec 810c54a60dbSLeo Liu #define mmUVD_SEMA_ADDR_HIGH_BASE_IDX 1 811c54a60dbSLeo Liu #define mmUVD_ENGINE_CNTL 0x02ed 812c54a60dbSLeo Liu #define mmUVD_ENGINE_CNTL_BASE_IDX 1 813c54a60dbSLeo Liu #define mmUVD_SEMA_TIMEOUT_STATUS 0x02ee 814c54a60dbSLeo Liu #define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 815c54a60dbSLeo Liu #define mmUVD_SEMA_CNTL 0x02ef 816c54a60dbSLeo Liu #define mmUVD_SEMA_CNTL_BASE_IDX 1 817c54a60dbSLeo Liu #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x02f0 818c54a60dbSLeo Liu #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 819c54a60dbSLeo Liu #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x02f1 820c54a60dbSLeo Liu #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 821c54a60dbSLeo Liu #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x02f2 822c54a60dbSLeo Liu #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 823c54a60dbSLeo Liu #define mmUVD_JOB_START 0x02f3 824c54a60dbSLeo Liu #define mmUVD_JOB_START_BASE_IDX 1 825c54a60dbSLeo Liu #define mmUVD_RBC_BUF_STATUS 0x02f4 826c54a60dbSLeo Liu #define mmUVD_RBC_BUF_STATUS_BASE_IDX 1 827c54a60dbSLeo Liu 828c54a60dbSLeo Liu 829c54a60dbSLeo Liu // addressBlock: uvd0_uvdgendec 830c54a60dbSLeo Liu // base address: 0x20470 831c54a60dbSLeo Liu #define mmUVD_LCM_CGC_CNTRL 0x033f 832c54a60dbSLeo Liu #define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 833c54a60dbSLeo Liu #define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x03a0 834c54a60dbSLeo Liu #define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1 835c54a60dbSLeo Liu #define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x03a1 836c54a60dbSLeo Liu #define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1 837c54a60dbSLeo Liu #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x03a2 838c54a60dbSLeo Liu #define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1 839c54a60dbSLeo Liu #define mmUVD_MIF_CURR_ADDR_CONFIG 0x03ae 840c54a60dbSLeo Liu #define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1 841c54a60dbSLeo Liu #define mmUVD_MIF_REF_ADDR_CONFIG 0x03af 842c54a60dbSLeo Liu #define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1 843c54a60dbSLeo Liu #define mmUVD_MIF_RECON1_ADDR_CONFIG 0x03e1 844c54a60dbSLeo Liu #define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1 845c54a60dbSLeo Liu 846c54a60dbSLeo Liu 847c54a60dbSLeo Liu // addressBlock: uvd0_lmi_adpdec 848c54a60dbSLeo Liu // base address: 0x20870 849c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0432 850c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 851c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0433 852c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 853c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0434 854c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 855c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0435 856c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 857c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0438 858c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 859c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0439 860c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 861c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x043a 862c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 863c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x043b 864c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 865c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x043c 866c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 867c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x043d 868c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 869c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0468 870c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 871c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0469 872c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 873c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x046a 874c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 875c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x046b 876c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 877c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x046c 878c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 879c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x046d 880c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 881c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x046e 882c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 883c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x046f 884c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 885c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0470 886c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 887c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0471 888c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 889c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0472 890c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 891c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0473 892c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 893c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0474 894c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 895c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0475 896c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 897c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0476 898c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 899c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x0477 900c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 901c54a60dbSLeo Liu #define mmUVD_LMI_SPH_64BIT_BAR_HIGH 0x047c 902c54a60dbSLeo Liu #define mmUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 903c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x047d 904c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 905c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x047e 906c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 907c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x047f 908c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 909c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0480 910c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 911c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0481 912c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 913c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0482 914c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 915c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0483 916c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 917c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0484 918c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 919c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0485 920c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 921c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0486 922c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 923c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x0487 924c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 925c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x0488 926c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 927c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x0489 928c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 929c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x048a 930c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 931c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x048b 932c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 933c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x048c 934c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 935c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC_VMID 0x048d 936c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 937c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_CTRL 0x048e 938c54a60dbSLeo Liu #define mmUVD_LMI_MMSCH_CTRL_BASE_IDX 1 939c54a60dbSLeo Liu #define mmUVD_LMI_ARB_CTRL2 0x049a 940c54a60dbSLeo Liu #define mmUVD_LMI_ARB_CTRL2_BASE_IDX 1 941c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x049f 942c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 943c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC_VMIDS_MULTI 0x04a0 944c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 945c54a60dbSLeo Liu #define mmUVD_LMI_LAT_CTRL 0x04a1 946c54a60dbSLeo Liu #define mmUVD_LMI_LAT_CTRL_BASE_IDX 1 947c54a60dbSLeo Liu #define mmUVD_LMI_LAT_CNTR 0x04a2 948c54a60dbSLeo Liu #define mmUVD_LMI_LAT_CNTR_BASE_IDX 1 949c54a60dbSLeo Liu #define mmUVD_LMI_AVG_LAT_CNTR 0x04a3 950c54a60dbSLeo Liu #define mmUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 951c54a60dbSLeo Liu #define mmUVD_LMI_SPH 0x04a4 952c54a60dbSLeo Liu #define mmUVD_LMI_SPH_BASE_IDX 1 953c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_VMID 0x04a5 954c54a60dbSLeo Liu #define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 955c54a60dbSLeo Liu #define mmUVD_LMI_CTRL2 0x04a6 956c54a60dbSLeo Liu #define mmUVD_LMI_CTRL2_BASE_IDX 1 957c54a60dbSLeo Liu #define mmUVD_LMI_URGENT_CTRL 0x04a7 958c54a60dbSLeo Liu #define mmUVD_LMI_URGENT_CTRL_BASE_IDX 1 959c54a60dbSLeo Liu #define mmUVD_LMI_CTRL 0x04a8 960c54a60dbSLeo Liu #define mmUVD_LMI_CTRL_BASE_IDX 1 961c54a60dbSLeo Liu #define mmUVD_LMI_STATUS 0x04a9 962c54a60dbSLeo Liu #define mmUVD_LMI_STATUS_BASE_IDX 1 963c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_CTRL 0x04ac 964c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_CTRL_BASE_IDX 1 965c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_COUNT_LO 0x04ad 966c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 967c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_COUNT_HI 0x04ae 968c54a60dbSLeo Liu #define mmUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 969c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_VMID 0x04b0 970c54a60dbSLeo Liu #define mmUVD_LMI_RBC_RB_VMID_BASE_IDX 1 971c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_VMID 0x04b1 972c54a60dbSLeo Liu #define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1 973c54a60dbSLeo Liu #define mmUVD_LMI_MC_CREDITS 0x04b2 974c54a60dbSLeo Liu #define mmUVD_LMI_MC_CREDITS_BASE_IDX 1 975c54a60dbSLeo Liu 976c54a60dbSLeo Liu 977c54a60dbSLeo Liu // addressBlock: uvd0_uvdnpdec 978c54a60dbSLeo Liu // base address: 0x20bd0 979c54a60dbSLeo Liu #define mmMDM_DMA_CMD 0x06f4 980c54a60dbSLeo Liu #define mmMDM_DMA_CMD_BASE_IDX 1 981c54a60dbSLeo Liu #define mmMDM_DMA_STATUS 0x06f5 982c54a60dbSLeo Liu #define mmMDM_DMA_STATUS_BASE_IDX 1 983c54a60dbSLeo Liu #define mmMDM_DMA_CTL 0x06f6 984c54a60dbSLeo Liu #define mmMDM_DMA_CTL_BASE_IDX 1 985c54a60dbSLeo Liu #define mmMDM_ENC_PIPE_BUSY 0x06f7 986c54a60dbSLeo Liu #define mmMDM_ENC_PIPE_BUSY_BASE_IDX 1 987c54a60dbSLeo Liu #define mmMDM_WIG_PIPE_BUSY 0x06f9 988c54a60dbSLeo Liu #define mmMDM_WIG_PIPE_BUSY_BASE_IDX 1 989c54a60dbSLeo Liu 990c54a60dbSLeo Liu 991f0a339a8SMohammad Zafar Ziya /* VCN 2_6_0 regs */ 992f0a339a8SMohammad Zafar Ziya #define mmUVD_RAS_VCPU_VCODEC_STATUS 0x0057 993f0a339a8SMohammad Zafar Ziya #define mmUVD_RAS_VCPU_VCODEC_STATUS_BASE_IDX 1 994f0a339a8SMohammad Zafar Ziya #define mmUVD_RAS_MMSCH_FATAL_ERROR 0x0058 995f0a339a8SMohammad Zafar Ziya #define mmUVD_RAS_MMSCH_FATAL_ERROR_BASE_IDX 1 996*88733d68STao Zhou #define mmVCN_RAS_CNTL 0x04b9 997*88733d68STao Zhou #define mmVCN_RAS_CNTL_BASE_IDX 1 998f0a339a8SMohammad Zafar Ziya 999f0a339a8SMohammad Zafar Ziya /* JPEG 2_6_0 regs */ 1000f0a339a8SMohammad Zafar Ziya #define mmUVD_RAS_JPEG0_STATUS 0x0059 1001f0a339a8SMohammad Zafar Ziya #define mmUVD_RAS_JPEG0_STATUS_BASE_IDX 1 1002f0a339a8SMohammad Zafar Ziya #define mmUVD_RAS_JPEG1_STATUS 0x005a 1003f0a339a8SMohammad Zafar Ziya #define mmUVD_RAS_JPEG1_STATUS_BASE_IDX 1 1004f0a339a8SMohammad Zafar Ziya 1005c54a60dbSLeo Liu #endif 1006