Home
last modified time | relevance | path

Searched refs:mmMP0_SMN_C2PMSG_101 (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dpsp_v11_0_8.c39 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_stop()
44 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_8_ring_stop()
83 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_create()
90 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_8_ring_create()
164 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_8_ring_set_wptr()
H A Dpsp_v12_0.c200 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v12_0_ring_create()
207 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v12_0_ring_create()
244 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v12_0_ring_stop()
255 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v12_0_ring_stop()
335 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); in psp_v12_0_ring_set_wptr()
H A Dpsp_v3_1.c214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg); in psp_v3_1_ring_create()
221 mmMP0_SMN_C2PMSG_101), 0x80000000, in psp_v3_1_ring_create()
259 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v3_1_ring_stop()
270 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v3_1_ring_stop()
359 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v3_1_ring_set_wptr()
H A Dpsp_v11_0.c268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_ring_stop()
279 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_ring_stop()
312 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, in psp_v11_0_ring_create()
319 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_ring_create()
583 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); in psp_v11_0_ring_set_wptr()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_12_0_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 … macro
H A Dmp_10_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 … macro
H A Dmp_9_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 0x00a5 macro
H A Dmp_11_0_8_offset.h166 #define mmMP0_SMN_C2PMSG_101 … macro
H A Dmp_11_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 … macro
H A Dmp_11_5_0_offset.h166 #define mmMP0_SMN_C2PMSG_101 … macro